AD AD5439YRUZ-REEL

Dual 8-/10-/12-Bit, High Bandwidth,
Multiplying DACs with Serial Interface
AD5429/AD5439/AD5449
Data Sheet
FEATURES
GENERAL DESCRIPTION
10 MHz multiplying bandwidth
INL of ±0.25 LSB @ 8 bits
16-lead TSSOP package
2.5 V to 5.5 V supply operation
±10 V reference input
50 MHz serial interface
2.47 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset
0.5 µA typical current consumption
Guaranteed monotonic
Daisy-chain mode
Readback function
The AD5429/AD5439/AD54491 are CMOS, 8-, 10-, and 12-bit,
dual-channel, current output digital-to-analog converters (DAC),
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
As a result of being manufactured on a CMOS submicron process,
these parts offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of 10 MHz.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
APPLICATIONS
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI, QSPI™, MICROWIRE™, and most DSP
interface standards. In addition, a serial data out (SDO) pin allows
daisy-chaining when multiple packages are used. Data readback
allows the user to read the contents of the DAC register via the
SDO pin. On power-up, the internal shift register and latches
are filled with 0s, and the DAC outputs are at zero scale.
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
The AD5429/AD5439/AD5449 DACs are available in 16-lead
TSSOP packages. The EV-AD5415/49SDZ evaluation board is
available for evaluating DAC performance. For more
information, see the UG-297 evaluation board user guide.
FUNCTIONAL BLOCK DIAGRAM
VREFA
AD5429/AD5439/AD5449
RFB
R
VDD
RFBA
SYNC
SCLK
INPUT
REGISTER
SHIFT
REGISTER
DAC
REGISTER
IOUT1A
8-/10-/12-BIT
R-2R DAC A
IOUT2A
SDIN
SDO
LDAC
POWER-ON
RESET
INPUT
REGISTER
DAC
REGISTER
IOUT1B
8-/10-/12-BIT
R-2R DAC B
IOUT2B
RFB
R
LDAC
1
Figure 1.
U.S. Patent Number 5,689,257.
Rev. E
VREFB
RFBB
04464-001
CLR
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Technical Support
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AD5429/AD5439/AD5449
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital-to-Analog Converter .................................................... 15
Applications ....................................................................................... 1
Circuit Operation ....................................................................... 15
General Description ......................................................................... 1
Single-Supply Applications ....................................................... 17
Functional Block Diagram .............................................................. 1
Adding Gain ................................................................................ 18
Revision History ............................................................................... 2
Divider or Programmable Gain Element ................................ 18
Specifications..................................................................................... 3
Reference Selection .................................................................... 19
Timing Characteristics ................................................................ 5
Amplifier Selection .................................................................... 19
Timing Diagrams.......................................................................... 5
Serial Interface ............................................................................ 20
Absolute Maximum Ratings ............................................................ 7
Microprocessor Interfacing ....................................................... 22
ESD Caution .................................................................................. 7
PCB Layout and Power Supply Decoupling ........................... 24
Pin Configuration and Function Descriptions ............................. 8
Overview of AD54xx Devices ....................................................... 25
Typical Performance Characteristics ............................................. 9
Outline Dimensions ....................................................................... 26
Terminology .................................................................................... 14
Ordering Guide .......................................................................... 26
Theory of Operation ...................................................................... 15
REVISION HISTORY
5/13—Rev. D to Rev. E
Changes to General Description .................................................... 1
Changes to Ordering Guide .......................................................... 26
6/11—Rev. C to Rev. D
Changes to General Description .................................................... 1
Deleted Evaluation Board for the DAC Section ......................... 24
Changes to Ordering Guide .......................................................... 30
4/10—Rev. B to Rev. C
Added to Figure 4 ............................................................................. 6
3/08—Rev. A to Rev. B
Added t13 and t14 Parameters to Table 2 ......................................... 5
Changes to Figure 2 .......................................................................... 5
Changes to Figure 3 .......................................................................... 6
Changes to Figure 38 ...................................................................... 16
Changes to Ordering Guide .......................................................... 30
7/05—Rev. 0 to Rev. A
Changes to Features List .................................................................. 1
Changes to Specifications ................................................................ 3
Changes to Timing Characteristics .................................................5
Changes to Absolute Maximum Ratings Section ..........................7
Changes to General Description Section .................................... 15
Changes to Table 5.......................................................................... 15
Changes to Table 6.......................................................................... 16
Changes to Single-Supply Applications Section ......................... 17
Changes to Divider or Programmable Gain Element Section .... 18
Changes to Table 7 Through Table 10 ......................................... 20
Added ADSP-BF5xx-to-AD5429/AD5439/AD5449
Interface Section ........................................................................ 23
Change to PCB Layout and
Power Supply Decoupling Section .......................................... 25
Changes to Power Supplies for the Evaluation Board Section .... 25
Changes to Table 13 ....................................................................... 29
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 30
7/04—Revision 0: Initial Version
Rev. E | Page 2 of 28
Data Sheet
AD5429/AD5439/AD5449
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with the OP177, and ac performance is measured with the AD8038, unless otherwise noted.
Table 1.
Parameter 1
STATIC PERFORMANCE
AD5429
Resolution
Relative Accuracy
Differential Nonlinearity
AD5439
Resolution
Relative Accuracy
Differential Nonlinearity
AD5449
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature
Coefficient
Output Leakage Current
REFERENCE INPUT
Reference Input Range
VREFA, VREFB Input Resistance
VREFA-to-VREFB Input Resistance
Mismatch
Input Capacitance
Code 0
Code 4095
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
Min
Typ
9
±10
11
1.6
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
Digital-to-Analog Glitch Impulse
Conditions
8
±0.5
±1
Bits
LSB
LSB
Guaranteed monotonic
10
±0.5
±1
Bits
LSB
LSB
Guaranteed monotonic
12
±1
−1/+2
±25
Bits
LSB
LSB
mV
ppm FSR/°C
Guaranteed monotonic
±5
±15
nA
nA
Data = 0x0000, TA = 25°C, IOUT1
Data = 0x0000, IOUT1
13
2.5
V
kΩ
%
Input resistance temperature coefficient = −50 ppm/°C
Typical = 25°C, maximum = 125°C
3.5
3.5
pF
pF
VDD = 3.6 V to 5.5 V
VDD = 2.5 V to 3.6 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5.5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5.5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
4
V
V
V
V
V
V
V
V
µA
pF
MHz
VREF = ±3.5 V p-p, DAC loaded all 1s
RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V,
DAC latch alternately loaded with 0s and 1s
1.7
1.7
0.8
0.7
VDD − 1
VDD − 0.5
Output Low Voltage, VOL
Input Leakage Current, IIL
Input Capacitance
DYNAMIC PERFORMANCE
Reference-Multiplying Bandwidth
Output Voltage Settling Time
Unit
±5
Input Low Voltage, VIL
Output High Voltage, VOH
Max
0.4
0.4
1
10
10
80
35
30
20
3
120
70
60
40
ns
ns
ns
ns
nV-sec
Rev. E | Page 3 of 28
1 LSB change around major carry, VREF = 0 V
AD5429/AD5439/AD5449
Parameter 1
Multiplying Feedthrough Error
Data Sheet
Min
Output Capacitance
Digital Feedthrough
Output Noise Spectral Density
Analog THD
Digital THD
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Wide Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Intermodulation Distortion
f1 = 40 kHz, f2 = 50 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
Typ
Max
Unit
12
25
3
70
48
17
30
5
dB
dB
pF
pF
nV-sec
25
81
nV/√Hz
dB
61
66
dB
dB
AD5449, 65k codes, VREF = 3.5 V
55
63
65
dB
dB
dB
50
60
62
dB
dB
dB
AD5449, 65k codes, VREF = 3.5 V
73
80
87
dB
dB
dB
70
75
80
dB
dB
dB
72
65
dB
dB
AD5449, 65k codes, VREF = 3.5 V
Clock = 10 MHz
Clock = 25 MHz
V
µA
µA
%/%
TA = 25°C, logic inputs = 0 V or VDD
TA = −40°C to +125°C, logic inputs = 0 V or VDD
∆VDD = ±5%
2.5
0.5
Power Supply Sensitivity
1
Conditions
DAC latches loaded with all 0s, VREF = ±3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
@ 1 kHz
VREF = 3. 5 V p-p, all 1s loaded, f = 1 kHz
Clock = 10 MHz, VREF = 3.5 V
5.5
0.7
10
0.001
Guaranteed by design and characterization, not subject to production test.
Rev. E | Page 4 of 28
Data Sheet
AD5429/AD5439/AD5449
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12 3
t13
t14
Update Rate
Limit at TMIN, TMAX
50
20
8
8
13
5
4
5
30
0
12
10
25
60
12
4.5
2.47
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Conditions/Comments 2
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
CLR pulse width
SYNC rising edge to LDAC falling edge
Consists of cycle time, SYNC high time, data setup, and output voltage settling time
Guaranteed by design and characterization, not subject to production test.
Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
3
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5.
1
2
TIMING DIAGRAMS
t1
SCLK
t8
t2
t4
t3
t7
SYNC
t6
t5
SDIN
DB15
DB0
t9
t10
LDAC1
t11
LDAC2
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram
Rev. E | Page 5 of 28
04464-002
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
AD5429/AD5439/AD5449
Data Sheet
t1
SCLK
t2
t4
t3
t7
SYNC
t6
t8
t5
SDIN
DB0
(N)
DB15
(N)
DB15
(N + 1)
DB0
(N + 1)
DB15
(N)
DB0
(N)
SDO
04464-003
t12
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON THE FALLING
EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain Timing Diagram
SCLK
16
32
SYNC
DB15
DB0
DB15
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB0
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
Figure 4. Readback Mode Timing Diagram
200µA
TO OUTPUT
PIN
IOL
VOH (MIN) + VOL (MAX)
2
CL
50pF
200µA
IOH
Figure 5. Load Circuit for SDO Timing Specifications
Rev. E | Page 6 of 28
04464-059
DB15
SDO
04464-004
SDIN
Data Sheet
AD5429/AD5439/AD5449
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREFx, RFBx to GND
IOUT1, IOUT2 to GND
Input Current to Any Pin Except Supplies
Logic Inputs and Output 1
Operating Temperature Range
Extended (Y Version)
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
1
Rating
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
±10 mA
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
150°C/W
300°C
235°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
ESD CAUTION
Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes.
Rev. E | Page 7 of 28
AD5429/AD5439/AD5449
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUT1A 1
16
IOUT2A
2
15
IOUT2B
RFBA
3
RFBB
VREFA
4
GND
5
AD5429/
AD5439/
AD5449
14
LDAC
6
TOP VIEW
(Not to Scale)
SCLK
7
10
SDIN
8
9
IOUT1B
13
VREFB
12
VDD
11
CLR
NC = NO CONNECT
04464-005
SYNC
SDO
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
Mnemonic
IOUT1A
IOUT2A
3
RFBA
4
5
6
VREFA
GND
LDAC
7
SCLK
8
SDIN
9
SDO
10
SYNC
11
CLR
12
13
14
VDD
VREFB
RFBB
15
IOUT2B
16
IOUT1B
Description
DAC A Current Output.
DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but it can be
biased to achieve single-supply operation.
DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external
amplifier output.
DAC A Reference Voltage Input Pin.
Ground Pin.
Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling
edge when the device is in standalone mode, or on the rising edge of SYNC when in daisy-chain mode.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked
into the shift register on the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, data is clocked at power-on into the shift register on the falling edge of SCLK. The control bits allow
the user to change the active edge to a rising edge.
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the
shift register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked
out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift
register makes the DAC register contents available for readback on the SDO pin, and they are clocked out on the
next 16 opposite clock edges to the active clock edge.
Active Low Control Input. This pin provides the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded into the
shift register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the
clocks, and data is latched into the shift register on the 16th active clock edge.
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware CLR pin as a clear-to-zero scale or midscale, as required.
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC B Reference Voltage Input Pin.
DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external
amplifier output.
DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but it can be
biased to achieve single-supply operation.
DAC B Current Output.
Rev. E | Page 8 of 28
Data Sheet
AD5429/AD5439/AD5449
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.20
0.10
0.05
0.05
DNL (LSB)
0.10
0
0
–0.05
–0.05
–0.10
–0.10
–0.15
–0.15
–0.20
0
50
TA = 25°C
VREF = 10V
VDD = 5V
0.15
100
150
200
250
CODE
–0.20
04464-017
0
50
200
250
Figure 10. DNL vs. Code (8-Bit DAC)
0.5
TA = 25°C
VREF = 10V
VDD = 5V
0.4
0.3
0.3
0.2
0.1
0.1
DNL (LSB)
0.2
0
–0.1
0
–0.1
–0.2
–0.2
–0.3
–0.3
–0.4
–0.4
200
400
600
800
1000
CODE
–0.5
04464-018
–0.5
0
TA = 25°C
VREF = 10V
VDD = 5V
0.4
0
200
400
600
800
1000
CODE
Figure 8. INL vs. Code (10-Bit DAC)
04464-021
0.5
INL (LSB)
150
CODE
Figure 7. INL vs. Code (8-Bit DAC)
Figure 11. DNL vs. Code (10-Bit DAC)
1.0
1.0
TA = 25°C
VREF = 10V
VDD = 5V
0.8
0.6
0.6
0.4
0.2
0.2
DNL (LSB)
0.4
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
0
500
1000
TA = 25°C
VREF = 10V
VDD = 5V
0.8
1500
2000
2500
3000
CODE
3500
4000
04464-019
INL (LSB)
100
Figure 9. INL vs. Code (12-Bit DAC)
–1.0
0
500
1000
1500
2000
2500
3000
CODE
Figure 12. DNL vs. Code (12-Bit DAC)
Rev. E | Page 9 of 28
3500
4000
04464-022
INL (LSB)
0.15
04464-020
TA = 25°C
VREF = 10V
VDD = 5V
AD5429/AD5439/AD5449
Data Sheet
0.6
8
0.5
7
SUPPLY CURRENT (mA)
TA = 25°C
0.4
MAX INL
INL (LSB)
0.3
0.2
TA = 25°C
VDD = 5V
0.1
6
VDD = 5V
5
4
3
0
MIN INL
2
–0.1
VDD = 3V
1
–0.2
3
4
5
6
7
8
9
04464-035
2
10
REFERENCE VOLTAGE
0
0.5
1.5
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
Figure 13. INL vs. Reference Voltage
04464-038
VDD = 2.5V
0
–0.3
Figure 16. Supply Current vs. Logic Input Voltage
1.6
–0.40
TA = 25°C
VDD = 5V
1.4
–0.45
1.2
IOUT1 VDD = 5V
IOUT1 LEAKAGE (nA)
–0.55
–0.60
MIN DNL
–0.65
1.0
0.8
IOUT1 VDD = 3V
0.6
0.4
3
4
5
6
7
8
9
0
–40
04464-036
2
10
REFERENCE VOLTAGE
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
04464-039
0.2
–0.70
Figure 17. IOUT1 Leakage Current vs. Temperature
Figure 14. DNL vs. Reference Voltage
0.50
5
0.45
4
VDD = 5V
VDD = 5V
0.40
SUPPLY CURRENT (µA)
3
2
1
0
VDD = 2.5V
–1
–2
0.35
ALL 0s
0.30
ALL 1s
0.25
VDD = 2.5V
0.20
0.15
ALL 1s
ALL 0s
0.10
–3
0.05
–4
–5
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
140
0
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 18. Supply Current vs. Temperature
Figure 15. Gain Error vs. Temperature
Rev. E | Page 10 of 28
120
140
04464-040
VREF = 10V
04464-037
GAIN ERROR (mV)
DNL (LSB)
–0.50
Data Sheet
AD5429/AD5439/AD5449
3
14
VDD = 5V
0
8
6
VDD = 3V
4
–3
VREF
VREF
VREF
VREF
VREF
–6
VDD = 2.5V
2
1
10
100
1k
10k
100k
1M
10M
–9
10k
04464-041
0
100M
FREQUENCY (Hz)
0.045
ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
10
100
OUTPUT VOLTAGE (V)
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AMP = AD8038
1k
10k
100k
FREQUENCY (Hz)
1M
100M
TA = 25°C
VREF = 0V
AMP = AD8038
CCOMP = 1.8pF
0x7FF TO 0x800
VDD = 5V
0.035
ALL OFF
1
10M
0.040
10M
100M
0.030
0.025
VDD = 3V
0.020
0.015
0x800 TO 0x7FF
0.010
VDD = 3V
0.005
0
–0.005
04464-042
VDD = 5V
–0.010
0
40
20
60
80
100
120
140
160
180
200
TIME (ns)
Figure 23. Midscale Transition, VREF = 0 V
Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code
0.2
–1.68
TA = 25°C
VREF = 3.5V
AMP = AD8038
CCOMP = 1.8pF
0x7FF TO 0x800
–1.69
VDD = 5V
OUTPUT VOLTAGE (V)
–1.70
–0.2
–0.4
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AMP = AD8038
–0.6
10
100
–1.72
VDD = 3V
–1.73
VDD = 5V
–1.74
VDD = 3V
–1.76
0x800 TO 0x7FF
–0.8
1
–1.71
–1.75
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
04464-043
GAIN (dB)
0
Figure 21. Reference Multiplying Bandwidth—All 1s Loaded
–1.77
0
20
40
60
80
100
120
140
160
TIME (ns)
Figure 24. Midscale Transition, VREF = 3.5 V
Rev. E | Page 11 of 28
180
200
04464-046
GAIN (dB)
TA = 25°C
LOADING
ZS TO FS
1M
FREQUENCY (Hz)
100k
Figure 22. Reference Multiplying Bandwidth vs. Frequency
and Compensation Capacitor
Figure 19. Supply Current vs. Update Rate
6
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
= ±2V, AD8038 C C 1.47pF
= ±2V, AD8038 C C 1pF
= ±0.15V, AD8038 C C 1pF
= ±0.15V, AD8038 C C 1.47pF
= ±3.51V, AD8038 C C 1.8pF
04464-044
GAIN (dB)
10
04464-045
12
IDD (mA)
TA = 25°C
VDD = 5V
TA = 25°C
LOADING ZS TO FS
AD5429/AD5439/AD5449
20
Data Sheet
90
TA = 25°C
VDD = 3V
AMP = AD8038
0
80
MCLK = 5MHz
70
MCLK = 10MHz
–20
SFDR (dB)
PSRR (dB)
60
–40
FULL SCALE
–60
ZERO SCALE
50
MCLK = 25MHz
40
30
–80
20
–100
TA = 25°C
VREF = 3.5V
AMP = AD8038
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
0
100
200
300
400
500
600
700
900
1000
fOUT (kHz)
Figure 28. Wideband SFDR vs. fOUT Frequency
Figure 25. Power Supply Rejection Ratio vs. Frequency
–60
0
TA = 25°C
VDD = 3V
VREF = 3.5V p-p
–65
800
04464-050
–120
04464-047
10
TA = 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–30
SFDR (dB)
THD + N (dB)
–70
–75
–40
–50
–60
–80
–70
–85
1
100
10
1k
10k
100k
1M
FREQUENCY (Hz)
–90
04464-048
–90
2
0
4
6
8
FREQUENCY (MHz)
12
10
04464-051
–80
Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 26. THD + Noise vs. Frequency
100
0
MCLK = 1MHz
TA�
= 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
80
–20
SFDR (dB)
MCLK = 200kHz
60
MCLK = 0.5MHz
40
–40
–50
–60
–70
–80
20
TA = 25°C
VREF = 3.5V
AMP = AD8038
0
20
40
60
80
100
120
140
160
180
fOUT (kHz)
200
Figure 27. Wideband SFDR vs. fOUT Frequency
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
4.0
4.5
5.0
Figure 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Rev. E | Page 12 of 28
04464-052
0
–90
04464-049
SFDR (dB)
–30
Data Sheet
AD5429/AD5439/AD5449
0
0
TA = 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–20
–30
IMD (dB)
–40
–50
–40
–50
–60
–60
–70
–70
–80
–80
0.5
1.0
1.5
3.0
3.5
2.0
2.5
FREQUENCY (MHz)
4.0
4.5
5.0
Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
0
–100
70
–20
90
100 105
95
FREQUENCY (kHz)
0
110
115
120
TA�
= 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–30
IMD (dB)
–30
–40
–50
–40
–50
–60
–60
–70
–80
–90
–90
300
350
400
450 500 550 600
FREQUENCY (kHz)
650
700
750
04464-054
–70
–80
–100
250
85
80
Figure 34. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
TA�
= 25°C
VDD = 3V
AMP = AD8038
65k CODES
–10
75
04464-056
0
04464-053
–90
–90
–100
0
Figure 32. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
20
100
150
200
250
FREQUENCY (kHz)
300
350
400
Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
300
TA�
= 25°C
VDD = 3V
AMP = AD8038
65k CODES
0
50
04464-057
SFDR (dB)
–30
SFDR (dB)
TA�
= 25°C
VDD = 3V
AMP = AD8038
65k CODES
–10
TA = 25°C
AMP = AD8038
ZERO SCALE LOADED TO DAC
250
MIDSCALE LOADED TO DAC
OUTPUT NOISE (nV/ Hz)
FULL SCALE LOADED TO DAC
–40
–60
–80
150
100
50
60
70
80
90
100 110 120
FREQUENCY (kHz)
130
140
150
04464-055
–100
–120
50
200
0
100
1k
10k
FREQUENCY (Hz)
Figure 36. Output Noise Spectral Density
Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Rev. E | Page 13 of 28
100k
04464-058
SFDR (dB)
–20
AD5429/AD5439/AD5449
Data Sheet
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function.
It is measured after adjusting for zero and full scale and is typically
expressed in LSBs or as a percentage of the full-scale reading.
Differential Nonlinearity
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating temperature
range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
VREF − 1 LSB. The gain error of the DACs is adjustable to zero
with an external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the IOUT1x terminal, it can be measured by
loading all 0s to the DAC and measuring the IOUT1 current.
Minimum current flows into the IOUT2x line when the DAC is
loaded with all 1s.
Digital Crosstalk
The glitch impulse transferred to the outputs of one DAC in
response to a full-scale code change (all 0s to all 1s, or vice versa)
in the input register of the other DAC. It is expressed in nV-sec.
Analog Crosstalk
The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s, or vice versa) while keeping LDAC high and
then pulsing LDAC low and monitoring the output of the DAC
whose digital code has not changed. The area of the glitch is
expressed in nV-sec.
Channel-to-Channel Isolation
The portion of input signal from the reference input of a DAC
that appears at the output of another DAC. It is expressed in dB.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as the second to fifth harmonics.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
THD = 20 log
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the digital inputs of the device is capacitively coupled through
the device and produces noise on the IOUT pins and, subsequently,
on the circuitry that follows. This noise is digital feedthrough.
V 2 2 + V3 2 + V 4 2 + V5 2
V1
Intermodulation Distortion (IMD)
The DAC is driven by two combined sine wave references of
Frequency fa and Frequency fb. Distortion products are produced
at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1,
2, 3 … Intermodulation terms are those for which m or n is not
equal to 0. The second-order terms include (fa + fb) and (fa − fb),
and the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa + 2fb),
and (fa − 2fb). IMD is defined as
IMD = 20 log
RMS Sum of the Sum and Diff Distortion Products
RMS Amplitude of the Fundamental
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1x terminal when all 0s are
loaded to the DAC.
Rev. E | Page 14 of 28
Data Sheet
AD5429/AD5439/AD5449
THEORY OF OPERATION
When an output amplifier is connected in unipolar mode, the
output voltage is given by
DIGITAL-TO-ANALOG CONVERTER
The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit, dualchannel, current output DACs consisting of a standard inverting
R-2R ladder configuration. Figure 37 shows a simplified diagram
for a single channel of the AD5449. The feedback resistor, RFBA,
has a value of R. The value of R is typically 10 kΩ (with a
minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT1A and
IOUT2A are kept at the same potential, a constant current flows
into each ladder leg, regardless of digital input code. Therefore,
the input resistance presented at VREFA is always constant.
R
R
VOUT   VREF  D / 2n
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)
n is the number of bits.
R
VREFA
2R
2R
2R
2R
S1
S2
S3
S12
With a fixed 10 V reference, the circuit shown in Figure 38 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
2R
R
RFBA
IOUT1A
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation using the 8-bit
AD5429 DAC.
04464-006
IOUT2A
DAC DATA LATCHES
AND DRIVERS
Table 5. Unipolar Code Table
Figure 37. Simplified Ladder
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Access is provided to the VREFx, RFBx, IOUT1x, and IOUT2x terminals of the DACs, making the devices extremely versatile and
allowing them to be configured in several operating modes, such
as unipolar mode, bipolar output mode, or single-supply mode.
CIRCUIT OPERATION
Analog Output (V)
−VREF (255/256)
−VREF (128/256) = −VREF/2
−VREF (1/256)
−VREF (0/256) = 0
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 38.
VDD
R2
VDD
VREF
VREF x
R1
AD5429/
AD5439/
AD5449
SYNC SCLK SDIN
C1
RFBA
IOUT1A
A1
IOUT2A
GND
VOUT = 0V TO –VREF
MICROCONTROLLER
Figure 38. Unipolar Operation
Rev. E | Page 15 of 28
04464-007
AGND
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
3. DAC B OMITTED FOR CLARITY.
AD5429/AD5439/AD5449
Data Sheet
Bipolar Operation
Stability
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can easily be accomplished by using another external
amplifier and three external resistors, as shown in Figure 39.
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as closely as possible, and
proper PCB layout techniques must be used. Because every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited gain bandwidth product (GBP) and
there is excessive parasitic capacitance at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in the closedloop applications circuit.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. When connected in bipolar mode, the output
voltage is
VOUT = (VREF × D − 2n − 1 ) − VREF
As shown in Figure 38 and Figure 39, an optional compensation
capacitor, C1, can be added in parallel with RFBx for stability.
Too small a value of C1 can produce ringing at the output,
whereas too large a value can adversely affect the settling time.
C1 should be found empirically, but 1 pF to 2 pF is generally
adequate for the compensation.
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)
n is the number of bits.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation with the AD5429.
Table 6. Bipolar Code
Analog Output (V)
+VREF (255/256)
0
−VREF (255/256)
−VREF (256/256)
R3
20kΩ
VDD
VDD
R1
VREF x
VREF ±10V
R1
R2
AD5429/
AD5439/
AD5449
SYNC SCLK SDIN
R5
20kΩ
C1
RFBA
IOUT1A
A1
R4
10kΩ
A2
IOUT2A
VOUT = –VREF TO +VREF
GND
MICROCONTROLLER
AGND
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
4. DAC B AND ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. Bipolar Operation
Rev. E | Page 16 of 28
04464-008
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Data Sheet
AD5429/AD5439/AD5449
Note that VIN is limited to low voltages because the switches
in the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, VIN must not go negative by
more than 0.3 V, or an internal diode turns on, causing the device
to exceed the maximum ratings. In this type of application, the
full range of multiplying capability of the DAC is lost.
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 40 shows the DACs operating in voltage-switching mode.
The reference voltage, VIN, is applied to the IOUT1A pin; IOUT2A
is connected to AGND; and the output voltage is available at the
VREFA terminal. In this configuration, a positive reference voltage
results in a positive output voltage, making single-supply operation
possible. The output from the DAC is voltage at a constant
impedance (the DAC ladder resistance). Therefore, an op amp
is necessary to buffer the output voltage. The reference input
no longer sees a constant input impedance; instead, it sees one
that varies with code. Therefore, the voltage input should be
driven from a low impedance source.
Positive Output Voltage
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier because
of the resistor tolerance errors. To generate a negative reference,
the reference can be level-shifted by an op amp such that the VOUT
and GND pins of the reference become the virtual ground and
−2.5 V, respectively, as shown in Figure 41.
VDD
R1
R2
RFBA VDD
VIN
IOUT1A
IOUT2A
VOUT
8-/10-/12-BIT V
REF A
DAC
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
04464-009
GND
Figure 40. Single-Supply Voltage-Switching Mode
VDD = +5V
ADR03
VOUT
VIN
GND
+5V
C1
VDD
–2.5V
IOUT1A
VREFA 8-/10-/12-BIT
IOUT2A
DAC
VOUT = 0V TO +2.5V
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 41. Positive Voltage Output with Minimum Components
Rev. E | Page 17 of 28
04464-010
–5V
RFBA
AD5429/AD5439/AD5449
Data Sheet
ADDING GAIN
As D is reduced, the output voltage increases. For small values of
the Digital Fraction D, it is important to ensure that the amplifier
does not saturate and the required accuracy is met. For example,
an 8-bit DAC driven with binary code of 0x10 (0001 0000)—that
is, 16 decimal—in the circuit of Figure 43 should cause the output
voltage to be 16 × VIN. However, if the DAC has a linearity specification of ±0.5 LSB, D can have a weight in the range of 15.5/256
to 16.5/256, so that the possible output voltage is in the range of
15.5 VIN to 16.5 VIN. This range represents an error of 3%, even
though the DAC itself has a maximum error of 0.2%.
In applications in which the output voltage must be greater than
VIN, gain can be added with an additional external amplifier, or
it can be achieved in a single stage. Consider the effect of temperature coefficients of the thin film resistors of the DAC. Simply
placing a resistor in series with the RFB resistor causes mismatches
in the temperature coefficients, resulting in larger gain temperature coefficient errors. Instead, the circuit in Figure 42 shows
the recommended method of increasing the gain of the circuit.
R1, R2, and R3 should have similar temperature coefficients,
but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits in which
gains of greater than 1 are required.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current into the VREFx terminal
is routed to the IOUT1 terminal, the output voltage changes as
follows:
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves
to many applications. If this type of DAC is connected as the
feedback element of an op amp and RFBA is used as the input
resistor, as shown in Figure 43, the output voltage is inversely
proportional to the digital input fraction, D.
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREFx terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
For D = 1 − 2−n, the output voltage is
VOUT = − VIN − D = − VIN − (1 − 2 − n )
VDD
R1
IOUT1A
VREFA 8-/10-/12-BIT
DAC
IOUT2A
VOUT
R3
GND
R2
GAIN =
R2 + R3
R2
R2R3
R1 =
R2 + R3
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
04464-011
VIN
C1
RFBA
VDD
Figure 42. Increasing Gain of Current Output DAC
VDD
VIN
RFBA
IOUT1A
IOUT2A
VDD
8-/10-/12-BIT V
REF A
DAC
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
04464-012
VOUT
Figure 43. Current-Steering DAC Used as a Divider or Programmable Gain Element
Rev. E | Page 18 of 28
Data Sheet
AD5429/AD5439/AD5449
REFERENCE SELECTION
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity
error, which, if large enough, could cause the DAC to be nonmonotonic. The input bias current of an op amp also generates
an offset at the voltage output as a result of the bias current flowing
in the feedback resistor, RFB. Most op amps have input bias
currents low enough to prevent significant errors in 12-bit
applications.
When selecting a reference for use with the AD54xx series of
current output DACs, pay attention to the reference output voltage
temperature coefficient specification. This parameter affects not
only the full-scale error, but it can also affect the linearity (INL and
DNL) performance. The reference temperature coefficient should
be consistent with the system accuracy specifications. For example,
an 8-bit system required to hold its overall specification to within
1 LSB over the temperature range of 0°C to 50°C dictates that the
maximum system drift with temperature should be less than
78 ppm/°C. A 12-bit system with the same temperature range
to overall specification within 2 LSBs requires a maximum drift
of 10 ppm/°C. By choosing a precision reference with a low output
temperature coefficient, this error source can be minimized.
Table 7 lists some references available from Analog Devices, Inc.,
that are suitable for use with this range of current output DACs.
Common-mode rejection of the op amp is important in voltageswitching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.
If the DAC switches are driven from true wideband low impedance
sources (VIN and AGND), they settle quickly. Consequently, the
slew rate and settling time of a voltage-switching DAC circuit
is determined largely by the output op amp. To obtain minimum
settling time in this configuration, minimize capacitance at the
VREF node (the voltage output node in this application) of the
DAC by using low input capacitance buffer amplifiers and careful
board design.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier input offset voltage. This output
Most single-supply circuits include ground as part of the analog
signal range, which, in turn, requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a wide range of singlesupply amplifiers (see Table 8 and Table 9).
Table 7. Suitable Analog Devices Precision References
Part No.
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
Output Voltage (V)
10
10
5
5
2.5
2.5
3
3
2.5
5
2.5
5
Initial Tolerance (%)
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
Temp Drift (ppm/°C)
3
9
3
9
3
9
3
9
3
3
9
9
ISS (mA)
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
Output Noise (µV p-p)
20
20
10
10
6
6
10
10
3.5
8
5
8
Package
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
Table 8. Suitable Analog Devices Precision Op Amps
Part No.
OP97
OP1177
AD8551
AD8603
AD8628
Supply Voltage (V)
±2 to ±20
±2.5 to ±15
2.7 to 5
1.8 to 6
2.7 to 6
VOS (Max) (µV)
25
60
5
50
5
IB (Max) (nA)
0.1
2
0.05
0.001
0.1
0.1 Hz to 10 Hz Noise (µV p-p)
0.5
0.4
1
2.3
0.5
Supply Current (µA)
600
500
975
50
850
Package
SOIC-8
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
TSOT, SOIC-8
Table 9. Suitable Analog Devices High Speed Op Amps
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V)
5 to 24
±2.5 to ±12
3 to 12
±3 to ±6
BW @ ACL (MHz)
145
490
350
320
Slew Rate (V/µs)
180
120
425
1300
Rev. E | Page 19 of 28
VOS (Max) (µV)
1500
1000
3000
10,000
IB (Max) (nA)
6000
10,500
750
7000
Package
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
AD5429/AD5439/AD5449
Data Sheet
SERIAL INTERFACE
SDO Control (SDO1 and SDO2)
The AD5429/AD5439/AD5449 have an easy-to-use, 3-wire
interface that is compatible with SPI, QSPI, MICROWIRE, and
most DSP interface standards. Data is written to the device in
16-bit words. Each 16-bit word consists of four control bits and
eight, 10, or 12 data bits, as shown in Figure 44 through Figure 46.
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an open-drain
driver. The strength of the SDO driver affects the timing of t12,
and, when stronger, allows a faster clock cycle.
Low Power Serial Interface
SDO2
0
SDO1
0
Function Implemented
Full SDO driver
0
1
1
1
0
1
Weak SDO driver
SDO configured as open drain
Disable SDO output
Table 10. SDO Control Bits
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and SDIN input buffers
are powered down on the rising edge of SYNC.
DAC Control Bit C3 to Control Bit C0
Daisy-Chain Control (DSY)
Control Bit C3 to Control Bit C0 allow control of various functions
of the DAC, as shown in Table 11. The default settings of the DAC
at power-on are such that data is clocked into the shift register
on falling clock edges and daisy-chain mode is enabled. The device
powers on with a zero-scale load to the DAC register and IOUT lines.
The DAC control bits allow the user to adjust certain features at
power-on. For example, daisy-chaining can be disabled if not in
use, an active clock edge can be changed to a rising edge, and DAC
output can be cleared to either zero scale or midscale. The user
can also initiate a readback of the DAC register contents for verification.
DSY allows the enabling or disabling of daisy-chain mode.
A 1 enables daisy-chain mode; a 0 disables daisy-chain mode.
When disabled, a readback request is accepted; SDO is automatically enabled; the DAC register contents of the relevant
DAC are clocked out on SDO; and, when complete, SDO is
disabled again.
Hardware CLR Bit (HCLR)
The default setting for the hardware CLR bit is to clear the registers
and DAC output to zero code. A 1 in the HCLR bit allows the
CLR pin to clear the DAC outputs to midscale, and a 0 clears to
zero scale.
Control Register (Control Bits = 1101)
Active Clock Edge (SCLK)
While maintaining software compatibility with single-channel
current output DACs (AD5426/AD5432/AD5443), these DACs
also feature additional interface functionality. Set the control bits
to 1101 to enter control register mode. Figure 47 shows the
contents of the control register, the functions of which are
described in the following sections.
The default active clock edge is a falling edge. Write a 1 to this
bit to clock data in on the rising edge, or a 0 to clock it in on the
falling edge.
C3
C2
C1
C0
DB7
DB6
DB5
DB4
DB3
CONTROL BITS
DB2
DB1
DB0
0
0
0
0
DATA BITS
04464-013
DB0 (LSB)
DB15 (MSB)
Figure 44. AD5429 8-Bit Input Shift Register Contents
C3
C2
C1
C0
DB9
DB8
DB7
DB6
DB5
CONTROL BITS
DB4
DB3
DB2
DB1
DB0
0
0
DATA BITS
04464-014
DB0 (LSB)
DB15 (MSB)
Figure 45. AD5439 10-Bit Input Shift Register Contents
C3
C2
C1
C0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
X
X
DB0
DATA BITS
CONTROL BITS
04464-015
DB0 (LSB)
DB15 (MSB)
Figure 46. AD5449 12-Bit Input Shift Register Contents
1
1
0
1
SDO2
SDO1
DSY
HCLR
SCLK
X
X
X
CONTROL BITS
Figure 47. Control Register Loading Sequence
Rev. E | Page 20 of 28
X
X
04464-016
DB0 (LSB)
DB15 (MSB)
Data Sheet
AD5429/AD5439/AD5449
SYNC Function
SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low, observing the minimum SYNC
falling edge to SCLK falling edge setup time, t4.
Daisy-Chain Mode
Daisy-chain mode is the default power-on mode. To disable the
daisy-chain function, write 1001 to the control word. In daisychain mode, the internal gating on SCLK is disabled. SCLK is
continuously applied to the input shift register when SYNC is
low. If more than 16 clock pulses are applied, the data ripples
out of the shift register and appears on the SDO line. This data
is clocked out on the rising edge of SCLK (this is the default; use
the control word to change the active edge) and is valid for the
next device on the falling edge of SCLK (default). By connecting
this line to the SDIN input on the next device in the chain,
a multidevice interface is constructed. For each device in the
system, 16 clock pulses are required. Therefore, the total number
of clock cycles must equal 16n, where n is the total number of
devices in the chain. See Figure 4.
When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents additional data from being clocked
into the input shift register. A burst clock containing the exact
number of clock cycles can be used, after which SYNC can be
taken high. After the rising edge of SYNC, data is automatically
transferred from the input shift register of each device to the
addressed DAC.
When control bits = 0000, the device is in no operation mode.
This may be useful in daisy-chain applications in which the user
does not want to change the settings of a particular DAC in the
chain. Write 0000 to the control bits for that DAC; subsequent
data bits are ignored.
Standalone Mode
After power-on, write 1001 to the control word to disable daisychain mode. The first falling edge of SYNC resets the serial
clock counter to ensure that the correct number of bits are
shifted in and out of the serial shift registers. A SYNC edge
during the 16-bit write cycle causes the device to abort the
current write cycle.
After the falling edge of the 16th SCLK pulse, data is automatically transferred from the input shift register to the DAC. For
another serial transfer to take place, the counter must be reset
by the falling edge of SYNC.
LDAC Function
The LDAC function allows asynchronous and synchronous
updates to the DAC output. The DAC is asynchronously updated
when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected,
whereby the DAC is updated on the 16th clock falling edge when
the device is in standalone mode, or on the rising edge of SYNC
when the device is in daisy-chain mode.
Software LDAC Function
Load-and-update mode can also serve as a software update function, irrespective of the voltage level on the LDAC pin.
Table 11. DAC Control Bits
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC
A and B
A
A
A
B
B
B
A and B
A and B
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Function Implemented
No operation (power-on default)
Load and update
Initiate readback
Load input register
Load and update
Initiate readback
Load input register
Update DAC outputs
Load input registers
Disable daisy-chain
Clock data to shift register on rising edge
Clear DAC output to zero scale
Clear DAC output to midscale
Control word
Reserved
No operation
Rev. E | Page 21 of 28
AD5429/AD5439/AD5449
Data Sheet
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD54xx family of DACs is
through a serial bus that uses standard protocol and is compatible
with microcontrollers and DSP processors. The communication
channel is a 3-wire interface consisting of a clock signal, a data
signal, and a synchronization signal. The AD5429/AD5439/
AD5449 require a 16-bit word, with the default being data valid
on the falling edge of SCLK; however, this is changeable using
the control bits in the data-word.
ADSP-21xx-to-AD5429/AD5439/AD5449 Interface
The ADSP-21xx family of DSPs is easily interfaced to an AD5429/
AD5439/AD5449 DAC without the need for extra glue logic.
Figure 48 is an example of a serial peripheral interface (SPI)
between the DAC and the ADSP-2191. The MOSI (master output,
slave input) pin of the DSP drives the serial data line, SDIN.
SYNC is driven from a port line, in this case SPIxSEL.
*ADDITIONAL PINS OMITTED FOR CLARITY.
SPIxSEL
The ADSP-2101/ADSP-2103/ADSP-2191 processor incorporates
channel synchronous serial ports (SPORT). A serial interface
between the DAC and DSP SPORT is shown in Figure 49. In this
interface example, SPORT0 is used to transfer data to the DAC
shift register. Transmission is initiated by writing a word to the Tx
register after SPORT has been enabled. In a write sequence, data
is clocked out on each rising edge of the DSP serial clock and
clocked into the DAC input shift register on the falling edge of
its SCLK. Updating of the DAC output takes place on the rising
edge of the SYNC signal.
AD5429/AD5439/
AD5449*
TFS
SYNC
DT
SDIN
SDIN
SCK
SCLK
Figure 50. ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface
A serial interface between the DAC and the DSP SPORT is shown
in Figure 51. When SPORT is enabled, initiate transmission by
writing a word to the Tx register. The data is clocked out on each
rising edge of the DSP serial clock and clocked into the DAC
input shift register on the falling edge of its SCLK. The DAC
output is updated by using the transmit frame synchronization
(TFS) line to provide a SYNC signal.
AD5429/AD5439/
AD5449*
ADSP-BF5xx*
TFS
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 49. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-toAD5429/AD5439/AD5449 Interface
SYNC
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY.
DT
04464-028
SCLK
AD5429/AD5439/
AD5449*
ADSP-BF5xx*
Figure 48. ADSP-2191 SPI-to-AD5429/AD5439/AD5449 Interface
ADSP-2101/
ADSP-2103/
ADSP-2191*
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
04464-033
SCLK
04464-027
SDIN
SCK
Setting
1
1
00
1
1
1
1111
The ADSP-BF5xx family of processors has an SPI-compatible port
that enables the processor to communicate with SPI-compatible
devices. A serial interface between the BlackFin® processor and
the AD5429/AD5439/AD5449 DAC is shown in Figure 50. In
this configuration, data is transferred through the MOSI pin.
SYNC is driven by the SPIxSEL pin, which is a reconfigured
programmable flag pin.
SYNC
MOSI
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
SCLK
SYNC
SDIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Communication between two devices at a given clock speed is
possible when the following specifications are compatible: frame
SYNC delay and frame SYNC setup-and-hold, data delay and
data setup-and-hold, and SCLK width. The DAC interface expects
a t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns
minimum.
Figure 51. ADSP-BF5xx SPORT-to-AD5429/AD5439/AD5449 Interface
Rev. E | Page 22 of 28
04464-034
SPIxSEL
Table 12. SPORT Control Register Setup
ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface
AD5429/AD5439/
AD5449*
ADSP-2191*
See the ADSP-21xx user manual at www.analog.com for details
on clock and frame SYNC frequencies for the SPORT register.
Table 12 shows the setup for the SPORT control register.
Data Sheet
AD5429/AD5439/AD5449
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and then a second write cycle is initiated
to transmit the second byte of data. Data on RxD is clocked out
of the microcontroller on the rising edge of TxD and is valid on
the falling edge of TxD. As a result, no glue logic is required
between the DAC and microcontroller interface. P1.1 is taken
high following the completion of this cycle. The 80C51/80L51
provide the LSB of the SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
requirement into account.
To load data to the DAC, leave PC7 low after the first eight bits
are transferred and perform a second serial write operation to
the DAC. PC7 is taken high at the end of this procedure.
If the user wants to verify the data previously written to the input
shift register, the SDO line can be connected to MISO of the
MC68HC11, and, with SYNC low, the shift register clocks data
out on the rising edges of SCLK.
MICROWIRE-to-AD5429/AD5439/AD5449 Interface
Figure 54 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC SCLK.
MICROWIRE*
AD5429/AD5439/
AD5449*
SK
AD5429/AD5439/
AD5449*
80C51*
SCLK
SDIN
P1.1
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 52. 80C51/80L51-to-AD5429/AD5439/AD5449 Interface
MC68HC11-to-AD5429/AD5439/AD5449 Interface
Figure 53 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The SPI on the MC68HC11
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured
by writing to the SPI control register (SPCR); see the MC68HC11
user manual. The SCK of the MC68HC11 drives the SCLK of
the DAC interface; the MOSI output drives the serial data line
(SDIN) of the AD5429/AD5439/AD5449.
MC68HC11*
SYNC
SCLK
PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 microcontroller user manual for
more information. In this example, the I/O port, RA1, is used to
provide a SYNC signal and enable the serial port of the DAC. This
microcontroller transfers only eight bits of data during each serial
transfer operation; therefore, two consecutive write operations
are required. Figure 55 shows the connection diagram.
PIC16C6x/7x*
MOSI
SDIN
AD5429/AD5439/
AD5449*
SCK/RC3
SCLK
SDI/RC4
SDIN
RA1
04464-030
PC7
SYNC
Figure 54. MICROWIRE-to-AD5429/AD5439/AD5449 Interface
AD5429/AD5439/
AD5449*
SCK
SDIN
CS
*ADDITIONAL PINS OMITTED FOR CLARITY.
04464-029
TxD
RxD
SCLK
SO
04464-031
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 52. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line, SDIN.
P1.1 is a bit-programmable pin on the serial port and is used to
drive SYNC. When data is to be transmitted to the switch, P1.1
is taken low. The 80C51/80L51 transmit data in 8-bit bytes only;
therefore, only eight falling clock edges occur in the transmit cycle.
valid on the falling edge of SCK. Serial data from the 68HC11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 53. MCH68HC11/68L11-to-AD5429/AD5439/AD5449 Interface
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5429/AD5439/AD5449, the SYNC
line is taken low (PC7). Data appearing on the MOSI output is
Rev. E | Page 23 of 28
Figure 55. PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
04464-032
80C51/80L51-to-AD5429/AD5439/AD5449 Interface
AD5429/AD5439/AD5449
Data Sheet
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5429/AD5439/AD5449 is mounted should be
designed so that the analog and digital sections are separate
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
The DAC should have ample supply bypassing of 10 µF in parallel
with 0.1 µF on the supply, located as close as possible to the
package, ideally right up against the device. The 0.1 µF capacitor
should have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types of
capacitors that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast-switching signals,
should be shielded with digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
layout reduces the effects of feedthrough on the board. A microstrip technique is by far the best method, but its use is not always
possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, and
signal traces are placed on the soldered side.
It is good practice to use compact, minimum lead-length PCB
layout design. Leads to the input should be as short as possible
to minimize IR drops and stray inductance.
The PCB metal traces between VREFx and RFBx should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close as
possible to the device.
Rev. E | Page 24 of 28
Data Sheet
AD5429/AD5439/AD5449
OVERVIEW OF AD54xx DEVICES
Table 13.
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
1
Resolution
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
No. DACs
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
INL (LSB)
±0.25
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.25
±1
±0.5
±1
±1
±1
±1
±1
±0.5
±1
±2
±1
±1
±1
±1
±2
±2
±2
±2
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package 1
RU-16, CP-20
RM-10
RU-20
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
RU-24
UJ-8
RM-10
RM-8
RU-24
CP-40
RU-20, CP-20
RU-24
RU-16
UJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
RM-8
RU-38
RM-8
RU-28
RU-16
RU-38
RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. E | Page 25 of 28
Features
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
AD5429/AD5439/AD5449
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 56. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5429YRU
AD5429YRU-REEL
AD5429YRU-REEL7
AD5429YRUZ
AD5429YRUZ-REEL
AD5429YRUZ-REEL7
AD5439YRU
AD5439YRU-REEL
AD5439YRU-REEL7
AD5439YRUZ
AD5439YRUZ-REEL
AD5439YRUZ-REEL7
AD5449YRU
AD5449YRU-REEL
AD5449YRU-REEL7
AD5449YRUZ
AD5449YRUZ-REEL
AD5449YRUZ-REEL7
EV-AD5415/49SDZ
1
Resolution
8
8
8
8
8
8
10
10
10
10
10
10
12
12
12
12
12
12
INL (LSB)
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±1
±1
±1
±1
±1
±1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Z = RoHS Compliant Part.
Rev. E | Page 26 of 28
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation Board
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
Data Sheet
AD5429/AD5439/AD5449
NOTES
Rev. E | Page 27 of 28
AD5429/AD5439/AD5449
Data Sheet
NOTES
©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04464-0-5/13(E)
Rev. E | Page 28 of 28