LT1720/LT1721
Dual/Quad,
4.5ns, Single Supply
3V/5V Comparators
with Rail-to-Rail Outputs
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FEATURES
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DESCRIPTIO
UltraFast: 4.5ns at 20mV Overdrive
7ns at 5mV Overdrive
Low Power: 4mA per Comparator
Optimized for 3V and 5V Operation
Pinout Optimized for High Speed Ease of Use
Input Voltage Range Extends 100mV
Below Negative Rail
TTL/CMOS Compatible Rail-to-Rail Outputs
Internal Hysteresis with Specified Limits
Low Dynamic Current Drain; 15µA/(V-MHz),
Dominated by Load In Most Circuits
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APPLICATIO S
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High Speed Differential Line Receiver
Crystal Oscillator Circuits
Window Comparators
Threshold Detectors/Discriminators
Pulse Stretchers
Zero-Crossing Detectors
High Speed Sampling Circuits
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
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The LT ®1720/LT1721 are UltraFastTM dual/quad comparators optimized for single supply operation, with a supply
voltage range of 2.7V to 6V. The input voltage range extends
from 100mV below ground to 1.2V below the supply voltage.
Internal hysteresis makes the LT1720/LT1721 easy to use
even with slow moving input signals. The rail-to-rail outputs
directly interface to TTL and CMOS. Alternatively, the symmetric output drive can be harnessed for analog applications
or for easy translation to other single supply logic levels.
The LT1720 is available in the 8-pin MSOP and SO packages;
three pins per comparator plus power and ground. The
LT1721 is available in the 16-pin SSOP and S packages.
The pinouts of the LT1720/LT1721 minimize parasitic effects
by placing the most sensitive inputs (inverting) away from the
outputs, shielded by the power rails. The LT1720/LT1721 are
ideal for systems where small size and low power are
paramount.
TYPICAL APPLICATIO
2.7V to 6V Crystal Oscillator with TTL/CMOS Output
Propagation Delay vs Overdrive
8
2.7V TO 6V
1MHz TO 10MHz
CRYSTAL (AT-CUT)
2k
7
220Ω
RISING EDGE
(tPDLH)
620Ω
+
DELAY (ns)
6
GROUND
CASE
C1
1/2 LT1720
OUTPUT
–
5
4
FALLING EDGE
(tPDHL)
3
2
2k
1720/21 TA01
0.01µF
25°C
VSTEP = 100mV
VCC = 5V
CLOAD = 10pF
1.8k
1
0
0
10
20
30
OVERDRIVE (mV)
40
50
1720/21 TA02
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LT1720/LT1721
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ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VCC to GND ...................................... 7V
Input Current ...................................................... ±10mA
Output Current (Continuous) ............................. ±20mA
Junction Temperature ........................................... 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Storage Temperature Range ................. – 65°C to 150°C
Operating Temperature Range
C Grade .................................................. 0°C to 70°C
I Grade .............................................. – 40°C to 85°C
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PACKAGE/ORDER INFORMATION
TOP VIEW
TOP VIEW
TOP VIEW
+IN A
–IN A
–IN B
+IN B
8
7
6
5
1
2
3
4
VCC
OUT A
OUT B
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
+IN A 1
8
VCC
–IN A 2
7
OUT A
–IN B 3
6
OUT B
+IN B 4
5
GND
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 230°C/ W
–IN A
1
16 –IN D
+IN A
2
15 +IN D
GND
3
14 VCC
OUT A
4
13 OUT D
OUT B
5
12 OUT C
GND
6
11 VCC
+IN B
7
10 +IN C
–IN B
8
9
GN PACKAGE
16-LEAD NARROW
PLASTIC SSOP
TJMAX = 150°C, θJA = 200°C/ W
–IN C
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 135°C/ W (GN)
TJMAX = 150°C, θJA = 115°C/ W (S)
ORDER PART
NUMBER
MS8
PART MARKING
ORDER PART
NUMBER
S8
PART MARKING
ORDER PART
NUMBER
GN
PART MARKING
LT1720CMS8
LTDS
LT1720CS8
LT1720IS8
1720
1720I
LT1721CGN
LT1721CS
LT1721IGN
LT1721IS
1721
1721I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 5V, VCM = 1V, COUT = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL
PARAMETER
VCC
Supply Voltage
VCMR
Common Mode Voltage Range
(Note 2)
VTRIP+
Input Trip Points
(Note 3)
VTRIP
–
VOS
Input Trip Points
Input Offset Voltage
CONDITIONS
MIN
TYP
Input Hysteresis Voltage
∆VOS/∆T
Input Offset Voltage Drift
2.7
6
●
– 0.1
VCC – 1.2
●
– 2.0
– 3.0
5.5
6.5
mV
mV
●
– 5.5
– 6.5
2.0
3.0
mV
mV
1.0
3.0
4.5
mV
mV
3.5
5.0
(Note 3)
(Note 3)
2
(Note 3)
UNITS
●
●
VHYST
MAX
●
●
2.0
10
V
V
mV
µV/°C
LT1720/LT1721
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 5V, VCM = 1V, COUT = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
IB
Input Bias Current
IOS
Input Offset Current
CMRR
Common Mode Rejection Ratio
(Note 4)
●
55
70
dB
PSRR
Power Supply Rejection Ratio
(Note 5)
●
65
80
dB
AV
Voltage Gain
(Note 6)
VOH
Output High Voltage
ISOURCE = 4mA, VIN = VTRIP+ + 10mV
●
VCC – 0.4
VOL
Output Low Voltage
ISINK = 10mA, VIN = VTRIP–
●
ICC
Supply Current (Per Comparator)
VCC = 5V
VCC = 3V
tPD20
Propagation Delay
VOVERDRIVE = 20mV (Note 7)
●
TYP
–6
●
Propagation Delay
Differential Propagation Delay
– 10mV
●
●
VOVERDRIVE = 5mV (Notes 7, 8)
(Note 9) Between Channels
+/t
tSKEW
Propagation Delay Skew
(Note 10) Between tPD PD
tr
Output Rise Time
10% to 90%
tf
Output Fall Time
90% to 10%
–
tJITTER
Output Timing Jitter
VIN = 1.2VP-P (6dBm), ZIN = 50Ω
VCM = 2V, f = 20MHz
fMAX
Maximum Toggle Frequency
VOVERDRIVE = 50mV, VCC = 3V
VOVERDRIVE = 50mV, VCC = 5V
Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.
Note 2: If one input is within these common mode limits, the other
input can go outside the common mode limits and the output will be
valid.
Note 3: The LT1720/LT1721 comparators include internal hysteresis.
The trip points are the input voltage needed to change the output state
in each direction. The offset voltage is defined as the average of VTRIP+
and VTRIP–, while the hysteresis voltage is the difference of these two.
Note 4: The common mode rejection ratio is measured with VCC = 5V
and is defined as the change in offset voltage measured from VCM =
– 0.1V to VCM = 3.8V, divided by 3.9V.
Note 5: The power supply rejection ratio is measured with VCM = 1V
and is defined as the change in offset voltage measured from VCC =
2.7V to VCC = 6V, divided by 3.3V.
Note 6: Because of internal hysteresis, there is no small-signal region
in which to measure gain. Proper operation of internal circuity is
ensured by measuring VOH and VOL with only 10mV of overdrive.
0
µA
0.6
µA
V
0.4
+
tPD
tPD–
V
4
3.5
7
6
mA
mA
4.5
6.5
8.0
ns
ns
7
10
13
ns
ns
0.3
1.0
ns
0.5
1.5
ns
●
∆tPD
UNITS
∞
●
tPD5
MAX
2.5
ns
2.2
ns
15
11
psRMS
psRMS
70.0
62.5
MHz
MHz
Note 7: Propagation delay measurements made with 100mV steps.
Overdrive is measured relative to VTRIP±.
Note 8: t PD cannot be measured in automatic handling equipment with
low values of overdrive. The LT1720/LT1721 are 100% tested with a
100mV step and 20mV overdrive. Correlation tests have shown that
t PD limits can be guaranteed with this test, if additional DC tests are
performed to guarantee that all internal bias conditions are correct.
Note 9: Differential propagation delay is defined as the larger of the
two:
∆t PDLH = tPDLH(MAX) – t PDLH(MIN)
∆t PDHL = tPDHL(MAX) – t PDHL(MIN)
where (MAX) and (MIN) denote the maximum and minimum values of
a given measurement across the different comparator channels.
Note 10: Propagation Delay Skew is defined as:
tSKEW = |tPDLH – tPDHL|
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LT1720/LT1721
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TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset and Trip Voltages
vs Supply Voltage
Input Offset and Trip Voltages
vs Temperature
3
2
1
VOS
0
VTRIP–
–2
25°C
VCM = 1V
–3
2.5
5.0
3.5 4.0 4.5
SUPPLY VOLTAGE (V)
3.0
5.5
1
VOS
0
–1
VTRIP–
–2
–3
–50
6.0
VCC = 5V
0
50
75
25
TEMPERATURE (°C)
– 25
25°C
VCC = 5V
1
INPUT CURRENT (µA)
0
–1
–2
–3
–4
–5
–6
–7
– 5 – 4 – 3 – 2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
5
QUIESCENT SUPPLY CURRENT PER COMPARATOR (mA)
2
7
DELAY (ns)
– 0.2
5.0
4.5
VCC = 5V
4.0
VCC = 3V
3.5
3.0
2.5
75
50
25
TEMPERATURE (˚C)
0
4
2
VCC = 3V
7.0
6.5
7
125°C
6
5
25°C
4
– 55°C
3
2
1
100
0
125
1
10
20
40
30
OUTPUT LOAD CAPACITANCE (pF)
50
1720/21 G07
4
3
2
5
SUPPLY VOLTAGE (V)
7
Propagation Delay
vs Supply Voltage
5.0
tPDLH
VCM = 1V
VSTEP = 100mV
CLOAD = 10pF
VCC = 5V
OVERDRIVE = 5mV
6.0
6
1720/21 G06
25°C
VSTEP = 100mV
OVERDRIVE = 20mV
CLOAD = 10pF
5.5
RISING EDGE
(tPDLH)
4.5
VCC = 5V
5.0
FALLING EDGE
(tPDHL)
OVERDRIVE = 20mV
0
125
1720/21 G03
4.5
1
100
0
2.0
– 50 – 25
7.5
FALLING EDGE
(tPDHL)
50
25
75
0
TEMPERATURE (°C)
Quiescent Supply Current
vs Supply Voltage
5.5
8.0
RISING EDGE
(tPDLH)
3
4
0
Propagation Delay
vs Temperature
6
5
0.2
1720/21 G05
PROPAGATION DELAY (ns)
25°C
VSTEP = 100mV
OVERDRIVE = 20mV
VCC = 5V
3.6
– 0.4
– 50 – 25
125
6.0
Propagation Delay
vs Load Capacitance
8
3.8
Quiescent Supply Current
vs Temperature
1720/21 G04
9
4.0
1720/21 G02
1720/21 G01
Input Current
vs Differential Input Voltage
100
DELAY (ns)
–1
2
COMMON MODE INPUT VOLTAGE (V)
VTRIP
4.2
VTRIP+
SUPPLY CURRENT PER COMPARATOR (mA)
+
VOS AND TRIP POINT VOLTAGE (mV)
VOS AND TRIP POINT VOLTAGE (mV)
3
0
Input Common Mode Limits
vs Temperature
VCC = 3V
4.0
75
0
50
25
– 50 – 25
TEMPERATURE (°C)
100
125
1720/21 G08
4.0
2.5
3.0
3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
5.5
6.0
1720/21 G09
LT1720/LT1721
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TYPICAL PERFORMANCE CHARACTERISTICS
Output High Voltage
vs Load Current
Output Low Voltage
vs Load Current
0.4
OUTPUT VOLTAGE RELATIVE TO VCC (V)
VCC = 5V
VCM = 1V
VIN = – 15mV
125°C
125°C
VCC = 2.7V
25°C
0.3
– 55°C
0.2
VCC = 5V
VCM = 1V
VIN = 15mV
125°C
– 0.2
SUPPLY CURRENT PER COMPARATOR (mA)
0.0
0.5
OUTPUT VOLTAGE (V)
Supply Current vs Frequency
– 55°C
25°C
– 0.4
– 0.6
– 0.8
0.1
25°C
VCC = 2.7V
–1.0
0
4
12
16
8
OUTPUT SINK CURRENT (mA)
20
10
25°C
VCC = 5V
9
8
CLOAD = 20pF
7
6
NO LOAD
5
4
3
0
4
12
16
8
OUTPUT SOURCE CURRENT (mA)
20
0
10
20
1720/21 G11
1720/21 G10
40
30
FREQUENCY (MHz)
1720/21 G12
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PIN FUNCTIONS
LT1720
LT1721
+IN A (Pin 1): Noninverting Input of Comparator A.
–IN A (Pin 1): Inverting Input of Comparator A.
–IN A (Pin 2): Inverting Input of Comparator A.
+IN A (Pin 2): Noninverting Input of Comparator A.
–IN B (Pin 3): Inverting Input of Comparator B.
GND (Pins 3, 6): Ground.
+IN B (Pin 4): Noninverting Input of Comparator B.
OUT A (Pin 4): Output of Comparator A.
GND (Pin 5): Ground.
OUT B (Pin 5): Output of Comparator B.
OUT B (Pin 6): Output of Comparator B.
+IN B (Pin 7): Noninverting Input of Comparator B.
OUT A (Pin 7): Output of Comparator A.
–IN B (Pin 8): Inverting Input of Comparator B.
VCC (Pin 8): Positive Supply Voltage.
–IN C (Pin 9): Inverting Input of Comparator C.
+IN C (Pin 10): Noninverting Input of Comparator C.
VCC (Pins 11, 14): Positive Supply Voltage.
OUT C (Pin 12): Output of Comparator C.
OUT D (Pin 13): Output of Comparator D.
+IN D (Pin 15): Noninverting Input of Comparator D.
–IN D (Pin 16): Inverting Input of Comparator D.
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LT1720/LT1721
TEST CIRCUITS
±VTRIP Test Circuit
15VP-P
BANDWIDTH-LIMITED
TRIANGLE WAVE
~ 1kHz
LTC203
14
VCC
15
3
2
0.1µF
1000 × VTRIP+
50k
1µF
10nF
+
16
1
9
8
10k
50Ω
50Ω
VCM
–
200k
1/2 LT1112
–
DUT
1/2 LT1720 OR
1/4 LT1721
11
10
6
+
1000 × VHYST
7
1000 × VOS
10k
LTC203
3
1/2 LT1638
+
100k
15
1000 × VTRIP–
1µF
10nF
+
1
16
8
9
2.4k
–
100k
14
100k
–
100k
2
1/2 LT1638
1/2 LT1112
–
0.15µF
6
7
11
+
10
NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ±15V.
200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS
WHEN DUT IS NOT POWERED
1720/21 TC01
Response Time Test Circuit
+VCC – VCM
0V
DUT
1/2 LT1720 OR
1/4 LT1721
–100mV
25Ω
0.01µF
+
25Ω
50k
10 × SCOPE PROBE
(CIN ≈ 10pF)
–
0.01µF
0.1µF
0V
PULSE
IN
V1*
130Ω
50Ω
2N3866
1N5711
–VCM
–3V
50Ω
400Ω
–5V
6
750Ω
*V1 = –1000 • (OVERDRIVE + VTRIP+)
NOTE: RISING EDGE TEST SHOWN.
FOR FALLING EDGE, REVERSE LT1720 INPUTS
1720/21 TC02
LT1720/LT1721
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APPLICATIONS INFORMATION
Input Voltage Considerations
Input Protection
The LT1720/LT1721 are specified for a common mode
range of –100mV to 3.8V when used with a single 5V
supply. In general the common mode range is 100mV
below ground to 1.2V below VCC. The criterion for this
common mode limit is that the output still responds
correctly to a small differential input signal. Also, if one
input is within the common mode limit, the other input
signal can go outside the common mode limits, up to the
absolute maximum limits (a diode drop past either rail at
10mA input current) and the output will retain the correct
polarity.
The input stage is protected against damage from large
differential signals, up to and beyond a differential voltage
equal to the supply voltage, limited only by the absolute
maximum currents noted. External input protection circuitry is only needed if currents would otherwise exceed
these absolute maximums. The internal catch diodes can
conduct current up to these rated maximums without
latchup, even when the supply voltage is at the absolute
maximum rating.
When either input signal falls below the negative common
mode limit, the internal PN diode formed with the substrate can turn on, resulting in significant current flow
through the die. An external Schottky clamp diode
between the input and the negative rail can speed up
recovery from negative overdrive by preventing the substrate diode from turning on.
When both input signals are below the negative common
mode limit, phase reversal protection circuitry prevents
false output inversion to at least – 400mV common mode.
However, the offset and hysteresis in this mode will
increase dramatically, to as much as 15mV each. The input
bias currents will also increase.
When both input signals are above the positive common
mode limit, the input stage will become debiased and the
output polarity will be random. However, the internal
hysteresis will hold the output to a valid logic level, and
because the biasing of each comparator is completely
independent, there will be no impact on any other comparator. When at least one of the inputs returns to within
the common mode limits, recovery from this state will take
as long as 1µs.
The propagation delay does not increase significantly
when driven with large differential voltages. However, with
low levels of overdrive, an apparent increase may be seen
with large source resistances due to an RC delay caused
by the 2pF typical input capacitance.
The LT1720/LT1721 input stage has general purpose
internal ESD protection for the human body model. For use
as a line receiver, additional external protection may be
required. As with most integrated circuits, the level of
immunity to ESD is much greater when residing on a
printed circuit board where the power supply decoupling
capacitance will limit the voltage rise caused by an ESD
pulse.
Input Bias Current
Input bias current is measured with both inputs held at 1V.
As with any PNP differential input stage, the LT1720/
LT1721 bias current flows out of the device. With a
differential input voltage of even just 100mV or so, there
will be zero bias current into the higher of the two inputs,
while the current flowing out of the lower input will be
twice the measured bias current. With more than two
diode drops of differential input voltage, the LT1720/
LT1721’s input protection circuitry activates, and current
out of the lower input will increase an additional 30% and
there will be a small bias current into the higher of the two
input pins, of 4µA or less. See the Typical Performance
curve “Input Current vs Differential Input Voltage.”
High Speed Design Considerations
Application of high speed comparators is often plagued
by oscillations. The LT1720/LT1721 have 4mV of internal
hysteresis, which will prevent oscillations as long as
parasitic output to input feedback is kept below 4mV.
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LT1720/LT1721
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APPLICATIONS INFORMATION
However, with the 2V/ns slew rate of the LT1720/LT1721
outputs, a 4mV step can be created at a 100Ω input
source with only 0.02pF of output to input coupling. The
pinouts of the LT1720/LT1721 have been arranged to
minimize problems by placing the most sensitive inputs
(inverting) away from the outputs, shielded by the power
rails. The input and output traces of the circuit board
should also be separated, and the requisite level of
isolation is readily achieved if a topside ground plane runs
between the outputs and the inputs. For multilayer boards
where the ground plane is internal, a topside ground or
supply trace should be run between the inputs and
outputs, as illustrated in Figure 1.
The supply bypass should include an adjacent
10nF ceramic capacitor and a 2.2µF tantalum capacitor no
farther than 5cm away; use more capacitance if driving
more than 4mA loads. To prevent oscillations, it is helpful
to balance the impedance at the inverting and noninverting
inputs; source impedances should be kept low, preferably
1kΩ or less.
The outputs of the LT1720/LT1721 are capable of very
high slew rates. To prevent overshoot, ringing and other
problems with transmission line effects, keep the output
traces shorter than 10cm, or be sure to terminate the lines
to maintain signal integrity. The LT1720/LT1721 can drive
DC terminations of 250Ω or more, but lower characteristic
impedance traces can be driven with series termination or
AC termination topologies.
Hysteresis
(a)
The LT1720/LT1721 include internal hysteresis, which
makes them easier to use than many other comparable
speed comparators.
(b)
1720/21 F01
Figure 1a shows a typical topside layout of the LT1720 on
such a multilayer board. Shown is the topside metal etch
including traces, pin escape vias, and the land pads for an
SO-8 LT1720 and its adjacent X7R 10nF bypass capacitor
in a 1206 case.
The input-output transfer characteristic is illustrated in
Figure 2 showing the definitions of VOS and VHYST based
upon the two measurable trip points. The hysteresis band
makes the LT1720/LT1721 well behaved, even with slowly
moving inputs.
VOUT
Figure 1. Typical Topside Metal for Multilayer PCB Layouts
The ground trace from Pin 5 runs under the device up to
the bypass capacitor, shielding the inputs from the
outputs. Note the use of a common via for the LT1720 and
the bypass capacitor, which minimizes interference from
high frequency energy running around the ground plane or
power distribution traces.
Figure 1b shows a typical topside layout of the LT1721 on
a multilayer board. In this case, the power and ground
traces have been extended to the bottom of the device
solely to act as high frequency shields between input and
output traces.
Although both VCC pins are electrically shorted internal to
the LT1721, they must be shorted together externally as
well in order for both to function as shields. The same is
true for the two GND pins.
8
VOH
VHYST
(= VTRIP+ – VTRIP–)
VHYST/2
VOL
∆VIN = VIN+ – VIN–
0
VTRIP–
VTRIP+
++V
V
VOS = TRIP
2
–
TRIP
1720/21 F02
Figure 2. Hysteresis I/O Characteristics
LT1720/LT1721
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The exact amount of hysteresis will vary from part to part
as indicated in the specifications table. The hysteresis level
will also vary slightly with changes in supply voltage and
common mode voltage. A key advantage of the LT1720/
LT1721 is the significant reduction in these effects, which
is important whenever an LT1720/LT1721 is used to detect a threshold crossing in one direction only. In such a
case, the relevant trip point will be all that matters, and a
stable offset voltage with an unpredictable level of hysteresis, as seen in competing comparators, is of little value.
The LT1720/LT1721 are many times better than prior comparators in these regards. In fact, the CMRR and PSRR
tests are performed by checking for changes in either trip
point to the limits indicated in the specifications table.
Because the offset voltage is the average of the trip points,
the CMRR and PSRR of the offset voltage is therefore
guaranteed to be at least as good as those limits. This
more stringent test also puts a limit on the common mode
and power supply dependence of the hysteresis voltage.
Additional hysteresis may be added externally. The rail-torail outputs of the LT1720/LT1721 make this more predictable than with TTL output comparators due to the
LT1720/LT1721’s small variability of VOH (output high
voltage).
To add additional hysteresis, set up positive feedback by
adding additional external resistor R3 as shown in Figure
3. Resistor R3 adds a portion of the output to the threshold
set by the resistor string. The LT1720/LT1721 pulls the
outputs to the supply rail and ground to within 200mV of
the rails with light loads, and to within 400mV with heavy
loads. For the load of most circuits, a good model for the
voltage on the right side of R3 is 300mV or VCC – 300mV,
for a total voltage swing of (VCC – 300mV) – 300mV =
VCC – 600mV.
With this in mind, calculation of the resistor values needed
is a two-step process. First, calculate the value of R3 based
on the additional hysteresis desired, the output voltage
swing, and the impedance of the primary bias string:
R3 = (R1R2)(VCC – 0.6V)/(additional hysteresis)
Additional hysteresis is the desired overall hysteresis less
the internal 3.5mV hysteresis.
The second step is to recalculate R2 to set the same
average threshold as before. The average threshold before
was set at VTH = (VREF)(R1)/(R1 + R2). The new R2 is
calculated based on the average output voltage (VCC /2)
and the simplified circuit model in Figure 4. To assure that
the comparator’s noninverting input is, on average, the
same VTH as before:
R2′ = (VREF – VTH)/(VTH/R1 + (VTH – VCC /2)/R3)
For additional hysteresis of 10mV or less, it is not uncommon for R2′ to be the same as R2 within 1% resistor
tolerances.
This method will work for additional hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R3
is low enough to effect the bias string, and adjustment of
R1 may also be required. Note that the currents through
the R1/R2 bias string should be many times the input
currents of the LT1720/LT1721. For 5% accuracy, the
current must be at least 120µA(6µA IB ÷ 0.05); more for
higher accuracy.
VREF
R2′
VREF
VTH
R3
R2
R1
R3
V
VAVERAGE = CC
2
R1
+
+
1/2 LT1720
1/2 LT1720
–
–
1720/21 F04
INPUT
1720/21 F03
Figure 3. Additional External Hysteresis
Figure 4. Model for Additional Hysteresis Calculations
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Interfacing the LT1720/LT1721 to ECL
The LT1720/LT1721 comparators can be used in high
speed applications where Emitter-Coupled Logic (ECL) is
deployed. To interface the outputs of the LT1720/LT1721
to ECL logic inputs, standard TTL/CMOS to ECL level
translators such as the 10H124, 10H424 and 100124 can
be used. These components come at a cost of a few
nanoseconds additional delay as well as supply currents of
50mA or more, and are only available in quads. A faster,
simpler and lower power translator can be constructed
with resistors as shown in Figure 5.
Figure 5a shows the standard TTL to Positive ECL (PECL)
resistive level translator. This translator cannot be used
for the LT1720/LT1721, or with CMOS logic, because it
depends on the 820Ω resistor to limit the output swing
(VOH) of the all-NPN TTL gate with its so-called totem-pole
output. The LT1720/LT1721 are fabricated in a complementary bipolar process and their output stage has a PNP
driver that pulls the output nearly all the way to the supply
rail, even when sourcing 10mA.
Figure 5b shows a three resistor level translator for interfacing the LT1720/LT1721 to ECL running off the same
supply rail. No pull-down on the output of the LT1720/
LT1721 is needed, but pull-down R3 limits the VIH seen by
the PECL gate. This is needed because ECL inputs have
both a minimum and maximum VIH specification for
proper operation. Resistor values are given for both ECL
interface types; in both cases it is assumed that the
LT1720/LT1721 operates from the same supply rail.
Figure 5c shows the case of translating to PECL from an
LT1720/LT1721 powered by a 3V supply rail. Again,
resistor values are given for both ECL interface types. This
time four resistors are needed, although with 10KH/E, R3
is not needed. In that case, the circuit resembles the
standard TTL translator of Figure 5a, but the function of
the new resistor, R4, is much different. R4 loads the
LT1720/LT1721 output when high so that the current
flowing through R1 doesn’t forward bias the LT1720/
LT1721’s internal ESD clamp diode. Although this diode
can handle 20mA without damage, normal operation and
performance of the output stage can be impaired above
10
100µA of forward current. R4 prevents this with the
minimum additional power dissipation.
Finally, Figure 5d shows the case of driving standard,
negative-rail, ECL with the LT1720/LT1721. Resistor values are given for both ECL interface types and for both a
5V and 3V LT1720/LT1721 supply rail. Again, a fourth
resistor, R4 is needed to prevent the low state current from
flowing out of the LT1720/LT1721, turning on the internal
ESD/substrate diodes. Not only can the output stage functionality and speed suffer, but in this case the substrate is
common to all the comparators in the LT1720/LT1721, so
operation of the other comparator(s) in the same package
could also be affected. Resistor R4 again prevents this
with the minimum additional power dissipation.
For all the dividers shown, the output impedance is about
110Ω. This makes these fast, less than a nanosecond,
with most layouts. Avoid the temptation to use speedup
capacitors. Not only can they foul up the operation of the
ECL gate because of overshoots, they can damage the
ECL inputs, particularly during power-up of separate
supply configurations.
The level translator designs assume one gate load. Multiple gates can have significant IIH loading, and the transmission line routing and termination issues also make this
case difficult.
ECL, and particularly PECL, is valuable technology for high
speed system design, but it must be used with care. With
less than a volt of swing, the noise margins need to be
evaluated carefully. Note that there is some degradation of
noise margin due to the ±5% resistor selections shown.
With 10KH/E, there is no temperature compensation of the
logic levels, whereas the LT1720/LT1721 and the circuits
shown give levels that are stable with temperature. This
will degrade the noise margin over temperature. In some
configurations it is possible to add compensation with
diode or transistor junctions in series with the resistors of
these networks.
For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from Motorola.
LT1720/LT1721
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5V
5V
180Ω
LSTTL
DO NOT USE FOR LT1720/LT1721
LEVEL TRANSLATION. SEE TEXT
270Ω
10KH/E
820Ω
(a) STANDARD TTL TO PECL TRANSLATOR
VCC
R2
R1
1/2 LT1720
10KH/E
100K/E
R3
VCC
R1
R2
R3
5V OR 5.2V 510Ω 180Ω 750Ω
4.5V
620Ω 180Ω 510Ω
(b) LT1720/LT1721 OUTPUT TO PECL TRANSLATOR
VCC
3V
R1
R2
1/2 LT1720
R4
10KH/E
100K/E
R3
VCC
R1
R4
R2
R3
5V OR 5.2V 300Ω 180Ω OMIT 560Ω
4.5V
330Ω 180Ω 1500Ω 1000Ω
(c) 3V LT1720/LT1721 OUTPUT TO PECL TRANSLATOR
VCC
R4
R1
1/2 LT1720
R2
ECL FAMILY
VEE
10KH/E
– 5.2V
100K/E
– 4.5V
R3
VCC
5V
3V
5V
3V
R1
560Ω
270Ω
680Ω
330Ω
R2
270Ω
510Ω
270Ω
390Ω
R3
R4
330Ω 1200Ω
300Ω 330Ω
300Ω 1500Ω
270Ω 430Ω
1720/21 F05
VEE
(d) LT1720/LT1721 OUTPUT TO STANDARD ECL TRANSLATOR
Figure 5
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Circuit Description
The block diagram of one comparator in the LT1720/LT1721
is shown in Figure 6. There are differential inputs
(+ IN/– IN), an output (OUT), a single positive supply (VCC)
and ground (GND). All comparators are completely independent, sharing only the power and ground pins. The
circuit topology consists of a differential input stage, a
gain stage with hysteresis and a complementary
common-emitter output stage. All of the internal signal
paths utilize low voltage swings for high speed at low power.
The input stage topology maximizes the input dynamic
range available without requiring the power, complexity
and die area of two complete input stages such as are
found in rail-to-rail input comparators. With a 2.7V supply,
the LT1720/LT1721 still have a respectable 1.6V of input
common mode range. The differential input voltage range
is rail-to-rail, without the large input currents found in
competing devices. The input stage also features phase
reversal protection to prevent false outputs when the
inputs are driven below the –100mV common mode
voltage limit.
The internal hysteresis is implemented by positive, nonlinear feedback around a second gain stage. Until this point,
the signal path has been entirely differential. The signal
path is then split into two drive signals for the upper and
lower output transistors. The output transistors are connected common emitter for rail-to-rail output operation.
The Schottky clamps limit the output voltages at about
300mV from the rail, not quite the 50mV or 15mV of Linear
Technology’s rail-to-rail amplifiers and other products.
But the output of a comparator is digital, and this output
stage can drive TTL or CMOS directly. It can also drive ECL,
as described earlier, or analog loads as demonstrated in
the applications to follow.
The bias conditions and signal swings in the output stages
are designed to turn their respective output transistors off
faster than on. This nearly eliminates the surge of current
from VCC to ground that occurs at transitions, keeping the
power consumption low even with high output-toggle
frequencies.
The low surge current is what keeps the power consumption low at high output-toggle frequencies. The frequency
dependence of the supply current is shown in the Typical
Performance Characteristics. Just 20pF of capacitive load
on the output more than triples the frequency dependent
rise. The slope of the no-load curve is just 32µA/MHz. With
a 5V supply, this current is the equivalent of charging and
discharging just 6.5pF. The slope of the 20pF load curve is
133µA/MHz, an addition of 101µA/MHz, or 20µA/MHz-V,
units that are equivalent to picoFarads.
The LT1720/LT1721 dynamic current can be estimated by
adding the external capacitive loading to an internal equivalent capacitance of 5pF to 15pF, multiplied by the toggle
frequency and the supply voltage. Because the capacitance of routing traces can easily approach these values,
the dynamic current is dominated by the load in most
circuits.
VCC
NONLINEAR STAGE
+
–
+
+IN
Σ
+
AV1
–IN
–
+
+
AV2
Σ
OUT
–
+
–
GND
1720/21 F06
Figure 6. LT1720/LT1721 Block Diagram
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Speed Limits
The LT1720/LT1721 comparators are intended for high
speed applications, where it is important to understand a
few limitations. These limitations can roughly be divided
into three categories: input speed limits, output speed
limits, and internal speed limits.
There are no significant input speed limits except the
shunt capacitance of the input nodes. If the 2pF typical
input nodes are driven, the LT1720/LT1721 will respond.
The output speed is constrained by two mechanisms, the
first of which is the slew currents available from the output
transistors. To maintain low power quiescent operation,
the LT1720/LT1721 output transistors are sized to deliver
25mA to 45mA typical slew currents. This is sufficient to
drive small capacitive loads and logic gate inputs at
extremely high speeds. But the slew rate will slow dramatically with heavy capacitive loads. Because the propagation
delay (tPD) definition ends at the time the output voltage is
halfway between the supplies, the fixed slew current
actually makes the LT1720/LT1721 faster at 3V than 5V
with 20mV of input overdrive.
Another manifestation of this output speed limit is skew,
the difference between tPD+ and tPD–. The slew currents of
the LT1720/LT1721 vary with the process variations of the
PNP and NPN transistors, for rising edges and falling
edges respectively. The typical 0.5ns skew can have either
polarity, rising edge or falling edge faster. Again, the skew
will increase dramatically with heavy capacitive loads.
The skews of comparators in a single package are correlated, but not identical. Besides some random variability,
there is a small (100ps to 200ps) systematic skew due to
physical parasitics of the packages. For the LT1720 SO-8,
comparator A, whose output is adjacent to the VCC pin, will
have a relatively faster rising edge than comparator B.
Likewise, comparator B, by virtue of an output adjacent to
the ground pin will have a relatively faster falling edge.
Similar dependencies occur in the LT1721 S16, while the
systemic skews in the smaller MSOP and SSOP packages
are half again as small. Of course, if the capacitive loads on
the two comparators of a single package are not identical,
the differential timing will degrade further.
The second output speed limit is the clamp turnaround.
The LT1720/LT1721 output is optimized for fast initial
response, with some loss of turnaround speed, limiting
the toggle frequency. The output transistors are idled in a
low power state once VOH or VOL is reached by detecting
the Schottky clamp action. It is only when the output has
slewed from the old voltage to the new voltage, and the
clamp circuitry has settled, that the idle state is reached
and the output is fully ready to transition again. This clamp
turnaround time is typically 8ns for each direction, resulting in a maximum toggle frequency of 62.5MHz, or a
125MB data rate. With higher frequencies, dropout and
runt pulses can occur. Increases in capacitive load will
increase the time needed for slewing due to the limited
slew currents and the maximum toggle frequency will
decrease further. For higher toggle frequency applications, consider the LT1394, whose linear output stage can
toggle at 100MHz typical.
The internal speed limits manifest themselves as dispersion. All comparators have some degree of dispersion,
defined as a change in propagation delay versus input
overdrive. The propagation delay of the LT1720/LT1721
will vary with overdrive, from a typical of 4.5ns at 20mV
overdrive to 7ns at 5mV overdrive (typical). The LT1720/
LT1721’s primary source of dispersion is the hysteresis
stage. As a change of polarity arrives at the gain stage, the
positive feedback of the hysteresis stage subtracts from
the overdrive available. Only when enough time has
elapsed for a signal to propagate forward through the gain
stage, backwards through the hysteresis stage and forward through the gain stage again, will the output stage
receive the same level of overdrive that it would have
received in the absence of hysteresis.
With 5mV of overdrive, the LT1720/LT1721 are faster with
a 5V supply than with a 3V supply, the opposite of what is
true with 20mV overdrive. This is due to the internal speed
limit, because the gain stage is faster at 5V than 3V due
primarily to the reduced junction capacitances with higher
reverse voltage bias.
In many applications, as shown in the following examples,
there is plenty of input overdrive. Even in applications
providing low levels of overdrive, the LT1720/LT1721 are
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fast enough that the absolute dispersion of 2.5ns
(= 7 – 4.5) is often small enough to ignore.
The gain and hysteresis stage of the LT1720/LT1721 is
simple, short and high speed to help prevent parasitic
oscillations while adding minimum dispersion. This internal “self-latch” can be usefully exploited in many
applications because it occurs early in the signal chain, in
a low power, fully differential stage. It is therefore highly
immune to disturbances from other parts of the circuit,
either in the same comparator, on the supply lines, or
from the other comparator(s) in the same package. Once
a high speed signal trips the hysteresis, the output will
respond, after a fixed propagation delay, without regard
to these external influences that can cause trouble in
nonhysteretic comparators.
±VTRIP Test Circuit
The input trip points are tested using the circuit shown in
the Test Circuits section that precedes this Applications
Information section. The test circuit uses a 1kHz triangle
wave to repeatedly trip the comparator being tested. The
LT1720/LT1721 output is used to trigger switched capacitor sampling of the triangle wave, with a sampler for each
direction. Because the triangle wave is attenuated 1000:1
and fed to the LT1720/LT1721’s differential input, the
sampled voltages are therefore 1000 times the input trip
voltages. The hysteresis and offset are computed from the
trip points as shown.
noninverting input. The circuit will operate with any AT-cut
crystal from 1MHz to 10MHz over a 2.7V to 6V supply
range. As the power is applied, the circuit remains off until
the LT1720/LT1721 bias circuits activate, at a typical VCC
of 2V to 2.2V (25°C), at which point the desired frequency
output is generated.
The output duty cycle for this circuit is roughly 50%, but
it is affected by resistor tolerances and, to a lesser extent,
by comparator offsets and timings. If a 50% duty cycle is
required, the circuit of Figure 7 creates a pair of complementary outputs with a forced 50% duty cycle. Crystals
are narrow-band elements, so the feedback to the noninverting input is a filtered analog version of the square wave
output. Changing the noninverting reference level can therefore vary the duty cycle. C1 operates as in the previous
example, whereas C2 creates a complementary output by
comparing the same two nodes with the opposite input
polarity. A1 compares band-limited versions of the outputs and biases C1’s negative input. C1’s only degree of
freedom to respond is variation of pulse width; hence the
outputs are forced to 50% duty cycle. Again, the circuit
operates from 2.7V to 6V, and the skew between the edges
of the two outputs are shown in Figure 8. There is a slight
duty cycle dependence on comparator loading, so equal
capacitive and resistive loading should be used in critical
VCC
2.7V TO 6V
1MHz TO 10MHz
CRYSTAL (AT-CUT)
2k
220Ω
Crystal Oscillators
A simple crystal oscillator using one comparator of an
LT1720/LT1721 is shown on the first page of this data
sheet. The 2k-620Ω resistor pair set a bias point at the
comparator’s noninverting input. The 2k-1.8k-0.1µF path
sets the inverting input node at an appropriate DC average
level based on the output. The crystal’s path provides
resonant positive feedback and stable oscillation occurs.
Although the LT1720/LT1721 will give the correct logic
output when one input is outside the common mode
range, additional delays may occur when it is so operated,
opening the possibility of spurious operating modes.
Therefore, the DC bias voltages at the inputs are set near
the center of the LT1720/LT1721’s common mode range
and the 220Ω resistor attenuates the feedback to the
14
620Ω
GROUND
CASE
+
C1
1/2 LT1720
OUTPUT
–
100k
2k
0.1µF
+
A1
LT1636
1.8k
0.1µF
–
1k
+
C2
1/2 LT1720
0.1µF
100k
OUTPUT
–
1720 F07
Figure 7. Crystal Oscillator with Complementary
Outputs and 50% Duty Cycle
LT1720/LT1721
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1000
56% low duty cycle, sufficient to allow 2ns between the
high pulses. Figure 10 shows the two outputs.
OUTPUT SKEW (ps)
800
The optional A1 feedback network shown can be used to
force identical output duty cycles. The steady state duty
cycles of both outputs will be 44%. Note, though, that the
addition of this network only adjusts the percentage of
time each output is high to be the same, which can be
important in switching circuits requiring identical settling
times. It cannot adjust the relative phases between the two
outputs to be exactly 180° apart, because the signal at the
input node driven by the crystal is not a pure sinusoid.
600
400
200
0
2.5
3.0
3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
5.5
6.0
1720/21 F08
Q0
2V/DIV
Figure 8. Timing Skew of Figure 7’s Circuit
applications. This circuit works well because of the two
matched delays and rail-to-rail style outputs of the LT1720.
Q1
2V/DIV
The circuit in Figure 9 shows a crystal oscillator circuit that
generates two nonoverlapping clocks by making full use of
the two independent comparators of the LT1720.
C1 oscillates as before, but with a lower reference level,
C2’s output will toggle at different times. The resistors set
the degree of separation between the output’s high pulses.
With the values shown, each output has a 44% high and
20ns/DIV
Figure 10. Nonoverlapping Outputs of Figure 9's Circuit
VCC
2.7V TO 6V
10MHz
CRYSTAL (AT-CUT)
2k
220Ω
620Ω
+
GROUND
CASE
C1
1/2 LT1720
OUTPUT 0
–
2k
1.3k
OPTIONAL—
SEE TEXT
A1
LT1636
0.1µF
2.2k
+
C2
1/2 LT1720
100k
+
0.1µF
–
1k
0.1µF
100k
OUTPUT 1
–
1720/21 F09
Figure 9. Crystal-Based Nonoverlapping 10MHz Clock Generator
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Timing Skews
For a number of reasons, the LT1720/LT1721’s superior
timing specifications make them an excellent choice for
applications requiring accurate differential timing skew.
The comparators in a single package are inherently well
matched, with just 300ps ∆tPD typical. Monolithic construction keeps the delays well matched vs supply voltage
and temperature. Crosstalk between the comparators,
usually a disadvantage in monolithic duals and quads, has
minimal effect on the LT1720/LT1721 timing due to the
internal hysteresis, as described in the Speed Limits
section.
The circuits of Figure 11 show basic building blocks for
differential timing skews. The 2.5k resistance interacts
with the 2pF typical input capacitance to create at least
±4ns delay, controlled by the potentiometer setting.
A differential and a single-ended version are shown. In the
differential configuration, the output edges can be smoothly
scrolled through ∆t = 0 with negligible interaction.
3ns Delay Detector
It is often necessary to measure comparative timing of
pulse edges in order to determine the true synchronicity of
clock and control signals, whether in digital circuitry or in
high speed instrumentation. The circuit in Figure␣ 12 is a
delay detector which will output a pulse when signals X
and Y are out of sync (specifically, when X is high and Y is
low). Note that the addition of an identical circuit to detect
the opposite situation (X low and Y high) allows for full
skew detection.
Comparators U1A and U1B clean up the incoming signals
and render the circuit less sensitive to input levels and
slew rates. The resistive divider network provides level
shifting for the downstream comparator’s common mode
input range, as well as offset to keep the output low except
during a decisive event. When the upstream comparator’s
outputs can overcome the resistively generated offset
(and hysteresis), comparator U1C performs a Boolean
“X*_Y” function and produces an output pulse (see Figure␣ 13). The circuit will give full output response with
input delays down to 3ns and partial output response with
input delays down to 1.8ns. Capacitor C1 helps ensure that
an imbalance of parasitic capacitances in the layout will
not cause common mode excursions to result in differential mode signal and false outputs.1
1 Make
sure the input levels at X and Y are not too close to the 0.5V threshold set by the R8–R9
divider. If you are still getting false outputs, try increasing C1 to 10pF or more. You can also look
for the problem in the impedance balance (R5 || R6 = R7) at the inputs of U1C. Increasing the offset
by lowering R5 will help reject false outputs, but R7 should also be lowered to maintain impedance
balance. For ease of design and parasitic matching, R7 can be replaced by two parallel resistors
equal to R5 and R6.
LT1720
LT1720
CIN
CIN
+
+
INPUT
–
INPUT
–
2.5k
CIN
CIN
0ns TO 4ns
SINGLE-ENDED
DELAY
DIFFERENTIAL ± 4ns
RELATIVE SKEW
2.5k
CIN
CIN
–
+
+
CIN
CIN
VREF
–
VREF
Figure 11. Building Blocks for Timing Skew Generation with the LT1720
16
1720/21 F11
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DELAY DETECTOR
5V
+
X
301Ω*
U1A
1/4 LT1721
51Ω*
R5
1.82k*
OPTIONAL LOGARITHMIC PULSE STRETCHER (SEE TEXT)
R6
301Ω*
5V
–
CAPTURE
0.33µF
–
0.1µF
R9
487Ω*
R8*
4.53k
301Ω*
C1
5.6pF
5V
–
U1C
1/4 LT1721
+
Z
1N5711
VIN
R1
499Ω*
+
VC
U1D
1/4 LT1721
C2
540pF
**
475Ω*
+
+
R7
261Ω*
51Ω*
X
1V
R2
1k*
DELAY
0V
Y
–
5V
301Ω*
U1B
1/4 LT1721
Y
L
R3
1Ω*
VOFF
–
R4
30Ω*
1V
0V
1720/21 F12
Z
* 1% METAL FILM RESISTOR
** 270pF ×2 FOR REDUCED LEAD INDUCTANCE
5V
0V
RESULT OF X AND NOT Y
Figure 12. 3ns Delay Detector with Logarithmic Pulse Stretcher
X
Y
Z
Figure 13. Output Pulse Due to Delay of Y Input Pulse
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Optional Logarithmic Pulse Stretcher
The fourth comparator of the quad LT1721 can be put to
work as a logarithmic pulse stretcher. This simple circuit
can help tremendously if you don’t have a fast enough
oscilloscope (or control circuit) to easily capture 3ns pulse
widths (or faster). When an input pulse occurs, C2 is
charged up with a 180ns capture2 time constant. The
hysteresis and 10mV offset across R3 are overcome
within the first nanosecond3, switching the comparator
output high. When the input pulse subsides, C2 discharges with a 540ns time constant, keeping the comparator on until the decay overrides the 10mV offset across R3
minus hysteresis. Because of this exponential decay, the
output pulse width will be proportional to the logarithm of
the input pulse width. It is important to bypass the circuit’s
VCC well to avoid coupling into the resistive divider. R4
keeps the quiescent input voltage in a range where forward
leakage of the diode due to the 0.4V VOL of the driving
comparator is not a problem.
Neglecting some effects4, the output pulse is related to the
input pulse as:
tOUT = τ2 • ln {VCH • [1 – exp (–tP/τ1)]/(VOFF – VH/2)}
– τ1 • ln [VCH/(VCH – VOFF – VH/2)]
+ tP
(1)
where
tP = input pulse width
tOUT = output pulse width
For simplicity, with tP < τ1, and neglecting the very slight
delay in turn-on due to offset and hysteresis, the equation
can be approximated by:
tOUT = τ2 • ln [(VCH • tP/τ1)/(VOFF – VH/2)]
(2)
For example, an 8ns input pulse gives a 1.67µs output
pulse. Doubling the input pulse to 16ns lengthens the
output pulse by 0.37µs. Doubling the input pulse again to
32ns adds another 0.37µs to the output pulse, and so on.
The rate of 0.37µs per octave falls out of the above
equation as:
∆tOUT/octave = τ2 • ln(2)
(3)
There is ±0.01µs jitter5 in the output pulse which gives an
uncertainty referred to the input pulse of less than 2%
(60ps resolution on a 3ns pulse with a 60MHz oscilloscope—not bad!). The beauty of this circuit is that it gives
resolution precisely where it’s hardest to get. The jitter is
due to a combination of the slow decay of the last few
millivolts on C2 and the 4nV/√Hz noise and 400MHz
bandwidth of the LT1721 input stage. Increasing the offset
across R3 or decreasing τ2 will decrease this jitter at the
expense of dynamic range.
The circuit topology itself is extremely fast, limited theoretically only by the speed of the diode, the capture time
constant τ1 and the pulse source impedance. Figure 14
shows results achieved with the implementation shown,
compared to a plot of equation (1). The low end is limited
by the delivery time of the upstream comparators. As the
input pulse width is increased, the log function is constrained by the asymptotic RC response but, rather than
becoming clamped, becomes time linear. Thus, for very
long input pulses the third term of equation (1) dominates
and the circuit becomes a 3µs pulse stretcher.
τ1 = R1 || R2 • C2
the capture time constant
τ2 = R2 • C2
the decay time constant
VOFF = 10mV
the voltage drop across R1
VH = 3.5mV
LT1721 hysteresis
2 So called because the very fast input pulse is “captured,” for later examination, as a charge on the
VC = VIN – VFDIODE
the input pulse voltage after
the diode drop
3 Assuming the input pulse slew rate at the diode is infinite. This effective delay constant, about 0.4%
VCH = VC • R2/(R1 + R2)
the effective source voltage
for the charge
18
capacitor.
of τ1 or 0.8ns, is the second term of equation 1, below. Driven by the 2.5ns slew-limited LT1721,
this effective delay will be 2ns.
4 V is dependent on the LT1721 output voltage and nonlinear diode characteristics. Also, the
C
Thevenin equivalent charge voltage seen by C2 is boosted slightly by R2 being terminated above
ground.
5 Output jitter increases with inputs pulse widths below ~ 3ns.
LT1720/LT1721
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APPLICATIONS INFORMATION
14
easily measured 1.70µs output pulses. A 12 foot cable
length difference will result in ~18.4ns delay and 2.07µs
output pulses. The difference in the two output pulse
widths is the per-octave response of your circuit (see
equation (3)). Shorter cable length differences can be
used to get a plot of circuit performance down to 1.5ns (if
any), which can then later be used as a lookup reference
when you have moved from quantifying the circuit to using
the circuit. (Note there is a slight aberration in performance below 10ns. See Figure 14.) As a final check, feed
the circuit with identical cable lengths and check that it is
not producing any output pulses.
tOUT STRETCHED (µs)
12
10
8
6
MEASURED
4
EQUATION 1
2
0
1
10
100
tPULSE (ns)
1000
10000
1720/21 F14
Figure 14. Log Pulse Stretcher Output Pulse vs Input Pulse
NANOSECOND
INPUT RANGE
MICROSECOND
OUTPUT RANGE
X
1 FOOT CABLE
L
Y
CIRCUIT OF
FIGURE 12
2V
tOUT
(SEE TEXT)
10ns Triple Overlap Generator
The circuit of Figure 16 utilizes an LT1721 to generate
three overlapping outputs whose pulse edges are separated by 10ns as shown. The time constant is set by the RC
network on the output of comparator A. Comparator B and
D trip at fixed percentages of the exponential voltage decay
across the capacitor. The 4.22kΩ feed-forward to the C
comparator’s inverting input keeps the delay differences
the same in each direction despite the exponential nature
of the RC network’s voltage.
There is a 15ns delay to the first edge in both directions,
due to the 4.5ns delay of two LT1721 comparators, plus
6ns delay in the RC network. This starting delay is shortened somewhat if the pulse was shorter than 40ns because the RC network will not have fully settled; however,
the 10ns edge separations stay constant.
SPLITTER
0V
n FOOT CABLE
1720/21 F15
Figure 15. RG-58 Cable with Velocity of Propogation = 66%;
Delay at Y = (n – 1) • 1.54ns
You don’t need expensive equipment to confirm the actual
overall performance of this circuit. All you need is a
respectable waveform generator (capable of >~100kHz), a
splitter, a variety of cable lengths and a 20MHz or 60MHz
oscilloscope. Split a single pulse source into different
cable lengths and then into the delay detector, feeding the
longer cable into the Y input (see Figure 15). A 6 foot cable
length difference will create a ~9.2ns delay (using 66%
propagation speed RG-58 cable), and should result in
The values shown utilize only the lowest 75% of the supply
voltage span, which allows it to work down to 2.7V supply.
The delay differences grow a couple nanoseconds from 5V
to 2.7V supply due to the fixed VOL/VOH drops which grow
as a percentage at low supply voltage. To keep this effect
to a minimum, the 1kΩ pull-up on comparator A provides
equal loading in either state.
Fast Waveform Sampler
Figure 17 uses a diode-bridge-type switch for clean, fast
waveform sampling. The diode bridge, because of its
inherent symmetry, provides lower AC errors than other
semiconductor-based switching technologies. This circuit features 20dB of gain, 10MHz full power bandwidth
19
LT1720/LT1721
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APPLICATIONS INFORMATION
VCC
VCC
OUTPUTS
+
U1B
1/4 LT1721
1k
VCC
–
VCC
INPUT
U1A
1/4 LT1721
–
VREF
10ns
750Ω
909Ω
+
10ns
1.37k
215Ω
+
681Ω
U1C
1/4 LT1721
100pF
–
10ns
10ns
681Ω
4.22k
+
U1D
1/4 LT1721
–
453Ω
1720/21 F16
Figure 16. 10ns Triple Overlap Generator
5V
2.2k
2.2k
INPUT
±100mV FULL SCALE
+
1k
LT1227
–
909Ω
= 1N5711
AC BALANCE
= CA3039 DIODE ARRAY
(SUBSTRATE TO – 5V)
100Ω
3pF
5V
1.5k
3.6k
1.1k
0.1µF
+
CIN
2k
10pF
1.1k
1.1k
1/2 LT1720
1.1k
–
SAMPLE
COMMAND
MRF501
MRF501
SKEW
COMP
DC BALANCE
2.5k
+
500Ω
11
1/2 LT1720
–
2k
820Ω
8
9
CIN
680Ω
820Ω
6
LM3045
10
13
51Ω
7
51Ω
1720/21 F17
–5V
Figure 17. Fast Waveform Sampler Using the LT1720 for Timing-Skew Compensation
20
OUTPUT
±1V FULL SCALE
LT1720/LT1721
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and 100µV/°C baseline uncertainty. Switching delay is
less than 15ns and the minimum sampling window width
for full power response is 30ns.
The input waveform is presented to the diode bridge
switch, the output of which feeds the LT1227 wideband
amplifier. The LT1720 comparators, triggered by the sample
command, generate phase-opposed outputs. These signals are level shifted by the transistors, providing complementary bipolar drive to switch the bridge. A skew
compensation trim ensures bridge-drive signal simultaneity within 1ns. The AC balance corrects for parasitic
capacitive bridge imbalances. A DC balance adjustment
trims bridge offset.
The trim sequence involves grounding the input via 50Ω
and applying a 100kHz sample command. The DC balance
is adjusted for minimal bridge ON vs OFF variation at the
output. The skew compensation and AC balance adjustments are then optimized for minimum AC disturbance in
the output. Finally, unground the input and the circuit is
ready for use.
Voltage-Controlled Clock Skew Generator
It is sometimes necessary to generate pairs of identical
clock signals that are phase skewed in time. Further, it is
desirable to be able to set the amount of time skew via a
tuning voltage. Figure 18’s circuit does this by utilizing
the LT1720 to digitize phase information from a varactortuned time domain bridge. A 0V to 2V control signal
provides ≈ ±10ns of output skew. This circuit operates
from a 2.7V to 6V supply.
CLOCK
INPUT
VCC
2.7V TO 6V
+
C1
1/2 LT1720
–
Q
FIXED
OUTPUT
Q′
SKEWED
OUTPUT
VCC
2k
2.5k
2.5k*
14k
2k*
2.5k
“FIXED”
+
“SKEWED”
12pF †
–
MV-209
VARACTOR
DIODE
1M
0.1µF
0.005µF
INPUT
0V TO 2V ≈
±10ns
SKEW
= 1N4148
C2
1/2 LT1720
36pF †
1M
L1**
+
VCC
A1
LT1077
–
47µF
+
2.2µF
VIN
6.2M*
= 74HC04
* 1% FILM RESISTOR
** SUMIDA CD43-100
† POLYSTYRENE, 5%
+
10ns
TRIM
SW
LT1317
1.82M*
FB
GND
VC
1.1M
100k
200pF
1720/21 F18
Figure 18. Voltage-Controlled Clock Skew
21
LT1720/LT1721
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Coincidence Detector
High speed comparators are especially suited for interfacing pulse-output transducers, such as particle detectors,
to logic circuitry. The matched delays of a monolithic dual
are well suited for those cases where the coincidence of
two pulses needs to be detected. The circuit of Figure 19
is a coincidence detector that uses an LT1720 and discrete
components as a fast AND gate.
The reference level is set to 1V, an arbitrary threshold. Only
when both input signals exceed this will a coincidence be
detected. The Schottky diodes from the comparator outputs to the base of the MRF-501 form the AND gate, while
the other two Schottkys provide for fast turn-off. A logic
AND gate could instead be used, but would add considerably more delay than the 300ps contributed by this discrete stage.
This circuit can detect coincident pulses as narrow as 3ns.
For narrower pulses, the output will degrade gracefully,
responding, but with narrow pulses that don’t rise all the
way to “high” before starting to fall. The decision delay is
4.5ns with input signals 50mV or more above the reference level. This circuit creates a TTL compatible output but
it can typically drive CMOS as well.
For a more detailed description of the operation of this
circuit, see Application Note 75, pages 10 and 11.
5V
3.9k
MRF501
1/2 LT1720
–
5V
OUTPUT
1k
0.1µF
GROUND
CASE LEAD
300Ω
+
51Ω
5V
–
1/2 LT1720
+
4× 1N5711
51Ω
1720/21 F19
COINCIDENCE COMPARATORS
300ps AND GATE
Figure 19. A 3ns Coincidence Detector
22
300Ω
GND
+IN
–IN
VCC
150Ω
150Ω
1720/21 SS
OUTPUT
LT1720/LT1721
SI PLIFIED SCHE ATIC
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
24
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
SO8 1298
LT1720/LT1721
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7 6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1
0.040 ± 0.006
(1.02 ± 0.15)
0.007
(0.18)
2 3
4
0.034 ± 0.004
(0.86 ± 0.102)
0° – 6° TYP
0.021 ± 0.006
(0.53 ± 0.015)
SEATING
PLANE 0.012
(0.30)
0.0256
REF
(0.65)
BSC
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS8) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
25
LT1720/LT1721
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
3
4
5
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.014 – 0.019
(0.355 – 0.483)
TYP
6
7
8
0.004 – 0.010
(0.101 – 0.254)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
26
2
0.053 – 0.069
(1.346 – 1.752)
0.050
(1.270)
BSC
S16 1098
LT1720/LT1721
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.009
(0.229)
REF
2 3
4
5 6
7
0.053 – 0.068
(1.351 – 1.727)
8
0.004 – 0.0098
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN16 (SSOP) 1098
27
LT1720/LT1721
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TYPICAL APPLICATION
Pulse Stretcher
capacitor C now begins charging through R and, at the
end of 100ns, C2 resets low. The output of C1 also goes
low, latching both outputs low. A new pulse at the input
of C1 can now restart the process. Timing capacitor C can
be increased without limit for longer output pulses.
For detecting short pulses from a single sensor, a pulse
stretcher is often required. The circuit of Figure 20 acts as
a one-shot, stretching the width of an incoming pulse to a
consistent 100ns. Unlike a logic one-shot, this LT1720based circuit requires only 100pV-s of stimulus to trigger.
This circuit has an ultimate sensitivity of better than 14mV
with 5ns to 10ns input pulses. It can even detect an
avalanche generated test pulse of just 1ns duration with
sensitivity better than 100mV.6␣ It can detect short events
better than the coincidence detector of Figure 14 because
the one-shot is configured to catch just 100mV of upward
movement from C1’s VOL, whereas the coincidence
detector’s 3ns specification is based on a full, legitimate
logic high, without the help of a regenerative one-shot.
The circuit works as follows: Comparator C1 functions as
a threshold detector, whereas comparator C2 is configured as a one-shot. The first comparator is prebiased with
a threshold of 8mV to overcome comparator and system
offsets and establish a low output in the absence of an
input signal. An input pulse sends the output of C1 high,
which in turn latches C2’s output high. The output of C2
is fed back to the input of the first comparator, causing
regeneration and latching both outputs high. Timing
6 See Linear Technology Application Note 47, Appendix B. This circuit can detect the output of the
pulse generator described after 40dB attenuation.
5V
0.01µF
15k
–
OUTPUT
C1
1/2 LT1720
PULSE SOURCE
50Ω
+
51Ω
100ns
24Ω
R
1k
6.8k
C
100pF
–
1N5711
C2
1/2 LT1720
+
2k
2k
1720/21 F20
2k
Figure 20. A 1ns Pulse Stretcher
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1016
UltraFast Precision Comparator
Industry Standard 10ns Comparator
LT1116
12ns Single Supply Ground-Sensing Comparator
Single Supply Version of LT1016
LT1394
7ns, UltraFast, Single Supply Comparator
6mA Single Supply Comparator
LT1671
60ns, Low Power, Single Supply Comparator
450µA Single Supply Comparator
LT1719
4.5ns Single Supply 3V/5V Comparator
Single Comparator Similar to the LT1720/LT1721
28
Linear Technology Corporation
17201f LT/TP 1099 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1998