LT1715 4ns, 150MHz Dual Comparator with Independent Input/Output Supplies U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO UltraFast: 4ns at 20mV Overdrive 150MHz Toggle Frequency Separate Input and Output Power Supplies Low Power: 4.6mA per Comparator at 3V Pinout Optimized for High Speed Use Output Optimized for 3V and 5V Supplies TTL/CMOS Compatible Rail-to-Rail Output Input Voltage Range Extends 100mV Below Negative Rail Internal Hysteresis with Specified Limits U APPLICATIO S ■ ■ ■ ■ ■ ■ The LT1715 is available in the 10-pin MSOP package. The pinout of the LT1715 minimizes parasitic effects by placing the most sensitive inputs away from the outputs, shielded by the power rails. High Speed Differential Line Receivers Level Translators Window Comparators Crystal Oscillator Circuits Threshold Detectors/Discriminators High Speed Sampling Circuits Delay Lines For a dual/quad single supply comparator with similar propagation delay, see the LT1720/LT1721. For a single comparator with similar propagation delay, see the LT1719. , LTC and LT are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation. U ■ The LT®1715 is an UltraFastTM dual comparator optimized for low voltage operation. Separate supplies allow independent analog input ranges and output logic levels with no loss of performance. The input voltage range extends from 100mV below VEE to 1.2V below VCC. Internal hysteresis makes the LT1715 easy to use even with slow moving input signals. The rail-to-rail outputs directly interface to TTL and CMOS. The symmetric output drive results in similar rise and fall times that can be harnessed for analog applications or for easy translation to other single supply logic levels. TYPICAL APPLICATIO 100MHz Dual Differential Line Receiver 5V Line Receiver Response to 100MHz Clock, 50MHz Data Both with 25mVP-P Inputs 3V 3V + CLOCK OUT 1V/DIV OUT A IN A – 0V 3V + DATA OUT 1V/DIV OUT B IN B 0V – FET PROBES –5V 5ns/DIV 1715 TA02 1715 TA01 1 LT1715 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage + VS to GND .......................................................... 7V VCC to VEE ........................................................ 13.2V + VS to VEE ....................................................... 13.2V VEE to GND ....................................... – 13.2V to 0.3V Input Current (+ IN, – IN) ................................... ±10mA Output Current (Continuous) ............................ ±20mA Operating Temperature Range ................ – 40°C to 85°C Specified Temperature Range (Note 2) ... – 40°C to 85°C Junction Temperature .......................................... 150°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW +IN A –IN A –IN B +IN B VEE 1 2 3 4 5 A B 10 9 8 7 6 LT1715CMS LT1715IMS VCC +VS OUT A OUT B GND MS10 PACKAGE 10-LEAD PLASTIC MSOP MS10 PART MARKING TJMAX = 150°C, θJA = 120°C/ W (NOTE 3) LTVQ LTVV Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, +VS = 5V, VCM = 1V, COUT = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER VCC – VEE Input Supply Voltage CONDITIONS ● MIN 2.7 TYP 12 V + VS Output Supply Voltage ● 2.7 6 V VCMR Input Voltage Range (Note 4) ● VEE – 0.1 VCC – 1.2 VTRIP+ VTRIP– Input Trip Points (Note 5) ● ● – 1.5 – 5.5 5.5 1.5 mV mV VOS Input Offset Voltage (Note 5) 0.4 2.5 3.5 mV mV 3.5 6 mV ● VHYST Input Hysteresis Voltage (Note 5) ∆VOS/∆T Input Offset Voltage Drift ● IB Input Bias Current ● IOS Input Offset Current ● CMRR Common Mode Rejection Ratio ● 2 –6 –2.5 0 µA 0.2 0.6 µA ● 60 70 dB ● 65 80 dB Power Supply Rejection Ratio (Note 7) Voltage Gain (Note 8) VOH Output High Voltage ISOURCE = 4mA, VIN = VTRIP+ + 20mV ● + VS – 0.4 VOL Output Low Voltage ISINK = 10mA, VIN = VTRIP– ● fMAX Maximum Toggle Frequency (Note 9) tPD20 Propagation Delay VOVERDRIVE = 20mV (Note 10), VCC = 5V, VEE = –5V ∞ – 20mV V 0.4 150 ● 2.8 2.8 VOVERDRIVE = 20mV, VCC = 5V, VEE = 0V 4 ● VOVERDRIVE = 5mV, VEE = 0V (Notes 10, 11) 3 3 2 (Note 12) Between tPD+/tPD–, VEE = 0V 6 7 ● ns ns ns 4.8 6.5 7.5 ns ns 6 9 12 ns ns 0.5 1.5 ns ● Propagation Delay Skew V MHz 4.4 VOVERDRIVE = 20mV, VCC = 3V, VEE = 0V tSKEW V (Note 6) AV Propagation Delay UNITS µV/°C 10 PSRR tPD5 MAX LT1715 ELECTRICAL CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, +VS = 5V, VCM = 1V, COUT = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER CONDITIONS ∆tPD Differential Propagation Delay (Note 13) Between Channels tr Output Rise Time 10% to 90% 2 ns tf Output Fall Time 90% to 10% 2 ns tJITTER Output Timing Jitter VIN = 1.2VP-P (6dBm), ZIN = 50Ω f = 20MHz (Note 14) 15 11 psRMS psRMS ICC Positive Input Stage Supply Current (per Comparator) IEE Negative Input Stage Supply Current (per Comparator) IS Positive Output Stage Supply Current (per Comparator) MIN ● tPD+ tPD– TYP MAX 0.3 1 UNITS ns + VS = VCC = 5V, VEE = – 5V ● 1 2 mA + VS = VCC = 3V, VEE = 0V ● 0.9 1.6 mA + VS = VCC = 5V, VEE = – 5V ● – 4.8 – 2.9 + VS = VCC = 3V, VEE = 0V ● – 3.8 – 2.4 + VS = VCC = 5V, VEE = – 5V ● 4.6 7.5 mA VS = VCC = 3V, VEE = 0V ● 3.7 6 mA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1715C is guaranteed to meet specified performance from 0°C to 70°C. The LT1715C is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1715I is guaranteed to meet specified performance from –40°C to 85°C. Note 3: Thermal resistances vary depending upon the amount of PC board metal attached to Pin 5 of the device. θJA is specified for a 2500mm2 3/32" FR-4 board covered with 2oz copper on both sides and with 100mm2 of copper attached to Pin 5. Thermal performance can be improved beyond the given specification by using a 4-layer board or by attaching more metal area to Pin 5. Note 4: If one input is within these common mode limits, the other input can go outside the common mode limits and the output will be valid. Note 5: The LT1715 comparator includes internal hysteresis. The trip points are the input voltage needed to change the output state in each direction. The offset voltage is defined as the average of VTRIP+ and VTRIP–, while the hysteresis voltage is the difference of these two. Note 6: The common mode rejection ratio is measured with VCC = 5V, VEE = – 5V and is defined as the change in offset voltage measured from VCM = – 5.1V to VCM = 3.8V, divided by 8.9V. Note 7: The power supply rejection ratio is measured with VCM = 1V and is defined as the worst of: the change in offset voltage from VCC = + VS = 2.7V to VCC = + VS = 6V (with VEE = 0V) divided by 3.3V or the change in offset voltage from VEE = 0V to VEE = – 6V (with VCC = +VS = 6V) divided by 6V. mA mA Note 8: Because of internal hysteresis, there is no small-signal region in which to measure gain. Proper operation of internal circuity is ensured by measuring VOH and VOL with only 20mV of overdrive. Note 9: Maximum toggle rate is defined as the highest frequency at which a 100mV sinusoidal input results in an error free output toggling to greater than 4V when high and to less than 1V when low on a 5V output supply. Note 10: Propagation delay measurements made with 100mV steps. Overdrive is measured relative to VTRIP±. Note 11: t PD cannot be measured in automatic handling equipment with low values of overdrive. The LT1715 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that t PD limits can be guaranteed with this test. Note 12: Propagation Delay Skew is defined as: tSKEW = |tPDLH – tPDHL| Note 13: Differential propagation delay is defined as the larger of the two: ∆tPDLH = |tPDLHA – tPDLHB| ∆tPDHL = |tPDHLA – tPDHLB| Note 14: Package inductances combined with asynchronous activity on the other channel can increase the output jitter. See Channel Interactions in Applications Information. Specification above is with one channel active only. 3 LT1715 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Offset and Trip Voltages vs Temperature 3 VTRIP+ VOS AND TRIP POINT VOLTAGE (mV) 2 1 VOS 0 –1 VTRIP– TA = 25°C VCM = 1V VEE = GND –2 –3 2.5 5.5 5.0 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE, VCC = + VS (V) 4.2 +VS = VCC = 5V VCM = 1V VEE = –5V 2 VTRIP+ 1 VOS 0 –1 VTRIP– –2 –3 – 60 – 40 – 20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 6.0 Input Current vs Differential Input Voltage –1 –2 –3 –4 –5 –6 –7 – 5 – 4 – 3 – 2 –1 0 1 2 3 4 DIFFERENTIAL INPUT VOLTAGE (V) 5 8 VCC = +VS = 5V VEE = –5V 6 IS 4 2 ICC 0 –2 IEE –4 –6 – 50 – 25 OUTPUT VOLTAGE RELATIVE TO +VS (V) OUTPUT VOLTAGE (V) –0.1 VCC = +VS = 5V, UNLESS 125°C OTHERWISE NOTED +VS = 2.7V VIN = –10mV 0.3 25°C 0.2 0.1 4 12 16 8 OUTPUT SINK CURRENT (mA) 20 1715 G07 4 50 25 75 0 TEMPERATURE (°C) TA = 25°C VEE = GND 5 100 100 3 IS, OUTPUT HIGH IS, OUTPUT LOW 2 ICC 1 0 –1 IEE, OUTPUT LOW –2 –3 125 – 55°C –0.3 25°C –0.4 125°C –0.5 125°C +VS = 2.7V 0 125 4 IEE, OUTPUT HIGH –4 75 50 25 TEMPERATURE (°C) 0 VCC = +VS = 5V, UNLESS OTHERWISE NOTED VIN = 10mV –0.2 –0.6 0 6 0 4 3 2 5 6 1 SUPPLY VOLTAGE, VCC = + VS (V) 4 12 16 8 OUTPUT SOURCE CURRENT (mA) 20 1715 G08 7 1715 G06 Output High Voltage vs Load Current 125°C 0 – 5.2 1715 G05 Output Low Voltage vs Load Current – 55°C – 5.0 Quiescent Supply Current vs Supply Voltage 1715 G04 0.4 – 4.8 1715 G03 SUPPLY CURRENT PER COMPARATOR (mA) INPUT BIAS (µA) SUPPLY CURRENT PER COMPARATOR (mA) TA = 25°C VCC = +VS = 5V VEE = –5V 0.5 3.6 Quiescent Supply Current vs Temperature 2 0 3.8 1715 G02 1715 G01 1 +VS = VCC = 5V VEE = – 5V 4.0 – 5.4 – 50 – 25 TOTAL SUPPLY CURRENT PER COMPARATOR (mA) VOS AND TRIP POINT VOLTAGE (mV) 3 Input Common Mode Limits vs Temperature COMMON MODE INPUT VOLTAGE (V) Input Offset and Trip Voltages vs Supply Voltage Supply Current vs Toggle Frequency 30 VALID TOGGLING INCOMPLETE OUTPUT TOGGLING 25 CLOAD = 20pF 20 CLOAD = 10pF 15 CLOAD = 0pF 10 TA = 25°C VIN = ±50mV SINUSOID +VS = VCC = 5V VEE = GND 5 0 0 25 50 75 100 125 150 175 200 225 TOGGLE FREQUENCY (MHz) 1715 G09 LT1715 U W TYPICAL PERFOR A CE CHARACTERISTICS Propagation Delay vs Overdrive 8.0 7 7.5 VCC = +VS = 3V VEE = 0V 6 5 tPDLH tPDHL 4 tPDLH VCC = +VS = 5V VEE = –5V 3 10 0 20 30 OVERDRIVE (mV) 40 7.0 6.5 6.0 OVERDRIVE = 5mV VCC = +VS = 3V VEE = 0V 5.5 5.0 4.5 4.0 3.0 – 50 – 25 50 5.5 tPDLH CLOAD = 10pF VSTEP = 100mV 3.5 OVERDRIVE = 20mV tPDHL Propagation Delay vs Supply Voltage 75 50 25 TEMPERATURE (°C) 0 100 100 80 60 40 20 150 130 110 90 50 25 0 75 TEMPERATURE (°C) 100 100 8 PROPAGATION DELAY (ns) 125 50 1715 G16 175 150 TOGGLING FROM 20% TO 80% OF +VS 125 100 TA = 25°C VIN = ±50mV SINUSOID 75 VEE = GND CLOAD = 10pF 50 4 2 3 7 1715 G15 20mV/DIV 5V 6 OUT A RISING EDGE (tPDLH) 5 6 5 +VS = VCC SUPPLY VOLTAGE (V) NA 25mVP-P TA = 25°C VSTEP = 100mV OVERDRIVE = 20mV +VS = VCC = 5V VEE = –5V FALLING EDGE (tPDHL) 1V/DIV 0V 4 3 10 15 20 25 30 35 40 45 50 OUTPUT CAPACITANCE (pF) 200 Response to 150MHz 25mVP-P Sine Wave Driving 10pF 75 5 125 Propagation Delay vs Load Capacitance 150 TOGGLING FROM 1V TO +VS – 1V 225 1715 G14 Maximum Toggle Rate vs Load Capacitance 175 5.5 6.0 5.0 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE, +VS = VCC OR V + (V) 250 TA = 25°C 230 VIN = ±50mV SINUSOID +VS = VCC = 5V 210 VEE = –5V 190 CLOAD = 10pF RLOAD = 500Ω 170 50 –50 –25 100 TA = 25°C VIN = ±50mV SINUSOID +VS = VCC = 5V VEE = GND VEE = –5V Maximum Toggle Rate vs Supply Voltage 1715 G13 0 4.0 1715 G12 70 0 200 tPDHL tPDLH 3.5 2.5 125 TOGGLE FREQUENCY (MHz) TOGGLE FREQUENCY (MHz) TOGGLE FREQUENCY (MHz) 120 10 INPUT SINUSOID AMPLITUDE (mV) VEE = GND 4.5 tPDHL 250 TA = 25°C 160 +VS = VCC = 5V VEE = GND 140 CLOAD = 10pF 225 tPDLH Maximum Toggle Rate vs Temperature 180 250 5.0 1715 G11 Maximum Toggle Rate vs Input Amplitude 1 TA = 25°C VSTEP = 100mV OVERDRIVE = 20mV CLOAD = 10pF VCC = +VS = 5V VEE = –5V 1715 G10 TOGGLE FREQUENCY (MHz) PROPAGATION DELAY (ns) TA = 25°C VSTEP = 100mV CLOAD = 10pF PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 8 Propagation Delay vs Temperature 0 10 20 40 30 OUTPUT LOAD CAPACITANCE (pF) 50 FET PROBES VCC = 5V VEE = –5V +VS = 5V VCM = 0V 2.5ns/DIV 1715 G18 1715 G17 5 LT1715 U U U PI FU CTIO S +IN A (Pin 1): Noninverting Input of Comparator A. GND (Pin 6): Ground for Output Stage. – IN A (Pin 2): Inverting Input of Comparator A. OUT B (Pin 7): Output of Comparator B. – IN B (Pin 3): Inverting Input of Comparator B. OUT A (Pin 8): Output of Comparator A. +IN B (Pin 4): Noninverting Input of Comparator B. + VS (Pin 9): Positive Supply Voltage for Output Stage. VEE (Pin 5): Negative Supply Voltage for Input Stage and Substrate. VCC (Pin 10): Positive Supply Voltage for Input Stage. TEST CIRCUITS ±VTRIP Test Circuit LTC203 BANDWIDTH-LIMITED TRIANGLE WAVE ~ 1kHz, VCM ±7.5V 14 VCC 15 2 1000 × VTRIP+ 50k 1µF 10nF + 50Ω 3 0.1µF 50Ω DUT 1/2 LT1715 – 16 1 9 8 10k 1/2 LT1112 200k – 1000 × VHYST + VCM 11 10 6 7 1000 × VOS 10k LTC203 3 1/2 LT1638 + 100k 15 + 1µF 10nF 1 16 8 9 2.4k – 100k 14 1000 × VTRIP– 100k – 100k 2 1/2 LT1638 1/2 LT1112 – 0.15µF 6 NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ±15V. 200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN DUT IS NOT POWERED 6 7 11 10 1715 TC01 + LT1715 TEST CIRCUITS Response Time Test Circuit +Vs – VCM 0V VCC – VCM 0.01µF –100mV 25Ω 25Ω 0.1µF 0V PULSE IN + DUT 1/2 LT1715 50k 10× SCOPE PROBE (CIN ≈ 10pF) – 130Ω 0.01µF 2N3866 V1* 50Ω VEE – VCM 1N5711 –3V 50Ω 400Ω –VCM 750Ω *V1 = –1000 • (OVERDRIVE + VTRIP+) NOTE: RISING EDGE TEST SHOWN. FOR FALLING EDGE, REVERSE LT1719 INPUTS –5V 1715 TC02 U W U U APPLICATIO S I FOR ATIO Power Supply Configurations The LT1715 has separate supply pins for the input and output stages that allow flexible operation, accommodating separate voltage ranges for the analog input and the output logic. Of course, a single 3V/5V supply may be used by tying + VS and VCC together as well as GND and VEE. The minimum voltage requirement can be simply stated as both the output and the input stages need at least 2.7V and the VEE pin must be equal to or less than ground. The following rules must be adhered to in any configuration: 2.7V ≤ (VCC – VEE) ≤ 12V 2.7V ≤ (+ VS – GND) ≤ 6V (+ VS – VEE) ≤ 12V VEE ≤ Ground Although the ground pin need not be tied to system ground, most applications will use it that way. Figure 1 shows three common configurations. The final one is uncommon, but it will work and may be useful as a level translator; the input stage is run from – 5.2V and ground while the output stage is run from 3V and ground. In this case the common mode input voltage range does not include ground, so it may be helpful to tie VCC to 3V. Conversely, VCC may also be tied below ground, as long as the above rules are not violated. 2.7V TO 6V 5V VCC + VCC + + VS GND – + VS GND – VEE 3V VEE – 5V Single Supply ± 5V Input, 3V Output Supplies 12V VCC + + VS GND – VCC 5V VEE + + VS GND – VEE – 5.2V 12V Input, 5V Output Supplies 3V 1715 F01 Front End Entirely Negative Figure 1. Variety of Power Supply Configurations Input Voltage Considerations The LT1715 is specified for a common mode range of –100mV to 3.8V when used with a single 5V supply. A more general consideration is that the common mode range is 100mV below VEE to 1.2V below VCC. The criterion for this common mode limit is that the output still 7 LT1715 U W U U APPLICATIO S I FOR ATIO responds correctly to a small differential input signal. If one input is within the common mode limit, the other input signal can go outside the common mode limits, up to the absolute maximum limits, and the output will retain the correct polarity. When either input signal falls below the negative common mode limit, the internal PN diode formed with the substrate can turn on, resulting in significant current flow through the die. An external Schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate diode from turning on. When both input signals are below the negative common mode limit, phase reversal protection circuitry prevents false output inversion to at least – 400mV common mode. However, the offset and hysteresis in this mode will increase dramatically, to as much as 15mV each. The input bias currents will also increase. When one input signal goes above the common mode range without exceeding a diode drop above the input supply rail, the input stage will remain biased and the comparator will maintain correct output polarity. Above this voltage, the input stage current source will saturate completely and the ESD protection diode will forward conduct. Once the aberrant input falls back into the common mode range, the comparator will respond correctly to valid input signals within less than 10ns. When both input signals are above the positive common mode limit, the input stage will get debiased and the output polarity will be random. However, the internal hysteresis will hold the output to a valid logic level. When at least one of the inputs returns to within the common mode limits, recovery from this state will take as long as 1µs. The propagation delay does not increase significantly when driven with large differential voltages, but with low levels of overdrive, an apparent increase may be seen with large source resistances due to an RC delay caused by the 2pF typical input capacitance. Input Protection The input stage is protected against damage from large differential signals, up to and beyond a differential voltage 8 equal to the supply voltage, limited only by the absolute maximum currents noted. External input protection circuitry is only needed if currents would otherwise exceed these absolute maximums. The internal catch diodes can conduct current up to these rated maximums without latchup, even when the supply voltages are at the absolute maximum ratings. The LT1715 input stage has general purpose internal ESD protection for the human body model. For use as a line receiver, additional external protection may be required. As with most integrated circuits, the level of immunity to ESD is much greater when residing on a printed circuit board where the power supply decoupling capacitance will limit the voltage rise caused by an ESD pulse. Input Bias Current Input bias current is measured with both inputs held at 1V. As with any PNP differential input stage, the LT1715 bias current flows out of the device. It will go to zero on the higher of the two inputs and double on the lower of the two inputs. With more than two diode drops of differential input voltage, the LT1715’s input protection circuitry activates, and current out of the lower input will increase an additional 30% and there will be a small bias current into the higher of the two input pins, of 4µA or less. See the Typical Performance curve “Input Current vs Differential Input Voltage.” High Speed Design Considerations Application of high speed comparators is often plagued by oscillations. The LT1715 has 4mV of internal hysteresis, which will prevent oscillations as long as parasitic output to input feedback is kept below 4mV. However, with the 2V/ns slew rate of the LT1715 outputs, a 4mV step can be created at a 100Ω input source with only 0.02pF of output to input coupling. The LT1715’s pinout has been arranged to minimize problems by placing the sensitive inputs away from the outputs, shielded by the power rails. The input and output traces of the circuit board should also be separated, and the requisite level of isolation is readily achieved if a topside ground plane runs between the output and the inputs. For multilayer boards where the ground plane is internal, a topside ground or supply trace should be run between the inputs and the output. LT1715 U W U U APPLICATIONS INFORMATION The ground pin of the LT1715 can disturb the ground plane potential while toggling due to the extremely fast on and off times of the output stage. Therefore, using a ground for input termination or filtering that is separate from the LT1715 Pin 6 ground can be highly beneficial. For example, a ground plane tied to Pin 6 and directly adjacent to a 1" long input trace can capacitively couple 4mV of disturbance into the input. In this scenario, cutting the ground plane between the GND pin and the inputs will cut the capacitance and the disturbance down substantially. Figure 2 shows a typical topside layout of the LT1715 on such a multilayer board. Shown is the topside metal etch including traces, pin escape vias, and the land pads for an MS10 LT1715 and its adjacent X7R 10nF bypass capacitors in the 0805 case. The ground trace from Pin 6 runs under the device up to the bypass capacitor, shielding the inputs from the outputs. Note the use of a common via for the LT1715 and the bypass capacitors, which minimizes interference from high frequency energy running around the ground plane or power distribution traces. The supply bypass should include an adjacent 10nF ceramic capacitor and a 2.2µF tantalum capacitor no farther than 5cm away; use more capacitance on + VS if driving more than 4mA loads. To prevent oscillations, it is helpful to balance the impedance at the inverting and noninverting inputs; source impedances should be kept low, preferably 1kΩ or less. maintain signal integrity. The LT1715 can drive DC terminations of 200Ω or more, but lower characteristic impedance traces can be used with series termination or AC termination topologies. Channel Interactions The LT1715’s two channels are designed to be entirely independent. However, at frequencies approaching and exceeding 100MHz, bond wire inductance begins to interfere with overlapping switching edges on the two channels. Figure 3 shows one channel of the comparator toggling at 100MHz with the other channel driven low with the scope set to display infinite persistence. Jitter is almost nonexistent. Figure 4 displays the same channel at 100MHz with infinite persistence, but the other channel of the comparator is toggling as well at frequencies swept from 60MHz to 160MHz. Jitter will occur as rising and falling edges align for any non harmonic or non fundamental frequency of the high frequency signal. – 5V OUT A 1V/DIV 0V The outputs of the LT1715 are capable of very high slew rates. To prevent overshoot, ringing and other problems with transmission line effects, keep the output traces shorter than 10cm, or be sure to terminate the lines to 5ns/DIV 1715 F03 Figure 3. Clean 100MHz Toggling – 5V OUT A 1V/DIV 0V 1715 F02 5ns/DIV Figure 2. Typical Topside Metal for Multilayer PCB Layouts 1715 F04 Figure 4. 100MHz Jitter with Both Channels Driven 9 LT1715 U W U U APPLICATIO S I FOR ATIO VOUT At frequencies well beyond 100MHz, the toggling of one channel may be impaired by toggling on the other. This is a rather complex interaction of supply bypassing and bond inductance, and it cannot be entirely prevented. However, good bypassing and board layout techniques will effectively minimize it. VOH VHYST (= VTRIP+ – VTRIP–) VHYST/2 Power Supply Sequencing The LT1715 is designed to tolerate any power supply sequencing at system turn-on and power down. In any of the previously shown power supply configurations, the various supplies can activate in any order without excessive current drain by the LT1715. As always, the Absolute Maximum Ratings must not be exceeded, either on the power supply terminals or the input terminals. Power supply sequencing problems can occur when input signals are powered from supplies that are independent of the LT1715’s supplies. No problems should occur if the input signals are powered from the same VCC and VEE supplies as the LT1715. Unused Comparators If a comparator is unused, its output should be left floating to minimize load current. The unused inputs can be tied off to the rails and power consumption can be further minimized if the inputs are connected to the power rails to induce an output low. Connecting the inverting input to VCC and the noninverting input to VEE will likely be the easiest method. Hysteresis The LT1715 includes internal hysteresis, which makes it easier to use than many other similar speed comparators. The input-output transfer characteristic is illustrated in Figure 5 showing the definitions of VOS and VHYST based upon the two measurable trip points. The hysteresis band makes the LT1715 well behaved, even with slowly moving inputs. The exact amount of hysteresis will vary from part to part as indicated in the specifications table. The hysteresis level will also vary slightly with changes in supply voltage and common mode voltage. A key advantage of the 10 VOL ∆VIN = VIN+ – VIN– 0 VTRIP– VTRIP+ ++V V VOS = TRIP 2 – TRIP 1715 F05 Figure 5. Hysteresis I/O Characteristics LT1715 is the significant reduction in these effects, which is important whenever an LT1715 is used to detect a threshold crossing in one direction only. In such a case, the relevant trip point will be all that matters, and a stable offset voltage with an unpredictable level of hysteresis, as seen in competing comparators, is useless. The LT1715 is many times better than prior generation comparators in these regards. In fact, the CMRR and PSRR tests are performed by checking for changes in either trip point to the limits indicated in the specifications table. Because the offset voltage is the average of the trip points, the CMRR and PSRR of the offset voltage is therefore guaranteed to be at least as good as those limits. This more stringent test also puts a limit on the common mode and power supply dependence of the hysteresis voltage. Additional hysteresis may be added externally. The rail-torail outputs of the LT1715 make this more predictable than with TTL output comparators due to the LT1715’s small variability of VOH (output high voltage). To add additional hysteresis, set up positive feedback by adding additional external resistor R3 as shown in Figure␣ 6. Resistor R3 adds a portion of the output to the threshold set by the resistor string. The LT1715 pulls the outputs to + VS and ground to within 200mV of the rails with light loads, and to within 400mV with heavy loads. For the load of most circuits, a good model for the voltage on the right side of R3 is 300mV or +VS – 300mV, for a total voltage swing of (+VS – 300mV) – (300mV) = +VS – 600mV. LT1715 U U W U APPLICATIONS INFORMATION VREF R1 may also be required. Note that the currents through the R1/R2 bias string should be many times the input currents of the LT1715. For 5% accuracy, the current must be at least 20 times the input current, more for higher accuracy. R3 R2 + 1/2 LT1715 R1 – Interfacing the LT1715 to ECL INPUT 1715 F06 Figure 6. Additional External Hysteresis With this in mind, calculation of the resistor values needed is a two-step process. First, calculate the value of R3 based on the additional hysteresis desired, the output voltage swing and the impedance of the primary bias string: R3 = (R1R2)(+VS – 0.6V)/(additional hysteresis) Additional hysteresis is the desired overall hysteresis less the internal 4mV hysteresis. The second step is to recalculate R2 to set the same average threshold as before. The average threshold before was set at VTH = (VREF)(R1)/(R1 + R2). The new R2 is calculated based on the average output voltage (+VS/2) and the simplified circuit model in Figure 7. To assure that the comparator’s noninverting input is, on average, the same VTH as before: R2′ = (VREF – VTH)/(VTH/R1 + (VTH – VS/2)/R3) For additional hysteresis of 10mV or less, it is not uncommon for R2′ to be the same as R2 within 1% resistor tolerances. This method will work for additional hysteresis of up to a few hundred millivolts. Beyond that, the impedance of R3 is low enough to effect the bias string, and adjustment of VREF R2′ VTH R3 VAVERAGE = +VS 2 R1 + 1/2 LT1715 – 1715 F07 Figure 7. Model for Additional Hysteresis Calculations The LT1715’s comparators can be used in high speed applications where Emitter-Coupled Logic (ECL) is deployed. To interface the output of the LT1715 to ECL logic inputs, standard TTL/CMOS to ECL level translators such as the 10H124, 10H424 and 100124 can be used. These components come at a cost of a few nanoseconds additional delay as well as supply currents of 50mA or more, and are only available in quads. A faster, simpler and lower power translator can be constructed with resistors as shown in Figure 8. Figure 8a shows the standard TTL to Positive ECL (PECL) resistive level translator. This translator cannot be used for the LT1715, or with CMOS logic, because it depends on the 820Ω resistor to limit the output swing (VOH) of the all-NPN TTL gate with its so-called totem-pole output. The LT1715 is fabricated in a complementary bipolar process and the output stage has a PNP driver that pulls the output nearly all the way to the supply rail, even when sourcing 10mA. Figure 8b shows a three resistor level translator for interfacing the LT1715 to ECL running off the same supply rail. No pull-down on the output of the LT1715 is needed, but pull-down R3 limits the VIH seen by the PECL gate. This is needed because ECL inputs have both a minimum and maximum VIH specification for proper operation. Resistor values are given for both ECL interface types; in both cases it is assumed that the LT1715 operates from the same supply rail. Figure 8c shows the case of translating to PECL from an LT1715 powered by a 3V supply rail. Again, resistor values are given for both ECL interface types. This time four resistors are needed, although with 10KH/E, R3 is not needed. In that case, the circuit resembles the standard TTL translator of Figure 8a, but the function of the new resistor, R4, is much different. R4 loads the LT1715 output when high so that the current flowing through R1 doesn’t forward bias the LT1715’s internal ESD clamp diode. Although this diode can handle 20mA without damage, normal 11 LT1715 U U W U APPLICATIONS INFORMATION 5V 5V 180Ω LSTTL DO NOT USE FOR LT1715 LEVEL TRANSLATION. SEE TEXT 270Ω 10KH/E 820Ω (a) STANDARD TTL TO PECL TRANSLATOR +VS VCC R2 R1 1/2 LT1715 10KH/E 100K/E R3 R1 + VS R2 R3 5V OR 5.2V 510Ω 180Ω 750Ω 4.5V 620Ω 180Ω 510Ω VEE (b) LT1715 OUTPUT TO PECL TRANSLATOR VECL VCC 3V R1 R2 1/2 LT1715 R4 10KH/E 100K/E R3 R4 R1 VECL R2 R3 5V OR 5.2V 300Ω 180Ω OMIT 560Ω 4.5V 330Ω 180Ω 1500Ω 1000Ω VEE (c) 3V LT1715 OUTPUT TO PECL TRANSLATOR VCC +VS R4 R1 1/2 LT1715 R2 VEE ECL FAMILY VECL 10KH/E – 5.2V 100K/E – 4.5V R3 + VS 5V 3V 5V 3V R1 560Ω 270Ω 680Ω 330Ω R2 270Ω 510Ω 270Ω 390Ω R4 R3 330Ω 1200Ω 300Ω 330Ω 300Ω 1500Ω 270Ω 430Ω 1715 F08 VECL (d) LT1715 OUTPUT TO STANDARD ECL TRANSLATOR Figure 8 operation and performance of the output stage can be impaired above 100µA of forward current. R4 prevents this with the minimum additional power dissipation. Finally, Figure 8d shows the case of driving standard, negative-rail, ECL with the LT1715. Resistor values are given for both ECL interface types and for both a 5V and 3V LT1715 supply rail. Again, a fourth resistor, R4 is needed to prevent the low state current from flowing out of the LT1715, turning on the internal ESD/substrate diodes. Resistor R4 again prevents this with the minimum additional power dissipation. 12 Of course, if the VEE of the LT1715 is the same as the ECL negative supply, the GND pin can be tied to it as well and + VS grounded. Then the output stage has the same power rails as the ECL and the circuits of Figure 8b can be used. For all the dividers shown, the output impedance is about 110Ω. This makes these fast, less than a nanosecond, with most layouts. Avoid the temptation to use speedup capacitors. Not only can they foul up the operation of the ECL gate because of overshoots, they can damage the ECL inputs, particularly during power-up of separate supply configurations. LT1715 U W U U APPLICATIO S I FOR ATIO The level translator designs assume one gate load. Multiple gates can have significant IIH loading, and the transmission line routing and termination issues also make this case difficult. ECL, and particularly PECL, is valuable technology for high speed system design, but it must be used with care. With less than a volt of swing, the noise margins need to be evaluated carefully. Note that there is some degradation of noise margin due to the ±5% resistor selections shown. With 10KH/E, there is no temperature compensation of the logic levels, whereas the LT1715 and the circuits shown give levels that are stable with temperature. This will lower the noise margin over temperature. In some configurations it is possible to add compensation with diode or transistor junctions in series with the resistors of these networks. For more information on ECL design, refer to the ECLiPS data book (DL140), the 10KH system design handbook (HB205) and PECL design (AN1406), all from Motorola, now ON Semiconductor. Circuit Description The block diagram of the LT1715 is shown in Figure 9. The circuit topology consists of a differential input stage, a gain stage with hysteresis and a complementary common-emitter output stage. All of the internal signal paths utilize low voltage swings for high speed at low power. The input stage topology maximizes the input dynamic range available without requiring the power, complexity and die area of two complete input stages such as are found in rail-to-rail input comparators. With a single 2.7V supply, the LT1715 still has a respectable 1.6V of input common mode range. The differential input voltage range is rail-to-rail, without the large input currents found in competing devices. The input stage also features phase reversal protection to prevent false outputs when the inputs are driven below the –100mV common mode voltage limit. The internal hysteresis is implemented by positive, nonlinear feedback around a second gain stage. Until this point, the signal path has been entirely differential. The signal path is then split into two drive signals for the upper and lower output transistors. The output transistors are connected common emitter for rail-to-rail output operation. The Schottky clamps limit the output voltages at about 300mV from the rail, not quite the 50mV or 15mV of Linear Technology’s rail-to-rail amplifiers and other products. But the output of a comparator is digital, and this output stage can drive TTL or CMOS directly. It can also drive ECL, as described earlier, or analog loads. The bias conditions and signal swings in the output stage are designed to turn their respective output transistors off faster than on. This helps minimize the surge of current from + VS to ground that occurs at transitions, to minimize +VS NONLINEAR STAGE + – VCC + +IN Σ + AV1 –IN + + AV2 Σ – OUT – + VEE – GND 1715 F09 Figure 9. LT1715 Block Diagram 13 LT1715 U W U U APPLICATIO S I FOR ATIO the frequency-dependent increase in power consumption. The frequency dependence of the supply current is shown in the Typical Performance Characteristics. Speed Limits The LT1715 comparator is intended for high speed applications, where it is important to understand a few limitations. These limitations can roughly be divided into three categories: input speed limits, output speed limits, and internal speed limits. There are no significant input speed limits except the shunt capacitance of the input nodes. If the 2pF typical input nodes are driven, the LT1715 will respond. The output speed is constrained by three mechanisms, the first of which is the slew currents available from the output transistors. To maintain low power quiescent operation, the LT1715 output transistors are sized to deliver 35mA to 60mA typical slew currents. This is sufficient to drive small capacitive loads and logic gate inputs at extremely high speeds. But the slew rate will slow dramatically with heavy capacitive loads. Because the propagation delay (tPD) definition ends at the time the output voltage is halfway between the supplies, the fixed slew current makes the LT1715 faster at 3V than 5V with large capacitive loads and sufficient input overdrive. Another manifestation of this output speed limit is skew, the difference between tPD+ and tPD–. The slew currents of the LT1715 vary with the process variations of the PNP and NPN transistors, for rising edges and falling edges respectively. The typical 0.5ns skew can have either polarity, rising edge or falling edge faster. Again, the skew will increase dramatically with heavy capacitive loads. A final limit to output speed is the turn-on and turn-off time of the output devices. Each device has substantial base charge that requires one nanosecond or more of active charging or discharging by the bias current of the Darlington driver stage. When toggle rates are high enough that insufficient time is allowed for this turn-on or turn-off, glitches may occur leading to dropout or runt pulses. Furthermore, power consumption may increase nonlinearly if devices are not turned off before the opposing cycle. However, once the toggle frequency increases or decreases, the part 14 will easily leave this undesired operating mode no worse for the wear provided there is adequate heat sinking to prevent thermal overload. At frequencies well beyond the maximum toggle rate, the part will toggle with limited output swing and well controlled power consumption. The internal speed limits manifest themselves as dispersion. All comparators have some degree of dispersion, defined as a change in propagation delay versus input overdrive. The propagation delay of the LT1715 will vary with overdrive, from a typical of 4ns at 20mV overdrive to 6ns at 5mV overdrive (typical). The LT1715’s primary source of dispersion is the hysteresis stage. As a change of polarity arrives at the gain stage, the positive feedback of the hysteresis stage subtracts from the overdrive available. Only when enough time has elapsed for a signal to propagate forward through the gain stage, backwards through the hysteresis path and forward through the gain stage again, will the output stage receive the same level of overdrive that it would have received in the absence of hysteresis. The LT1715 is several hundred picoseconds faster when VEE = – 5V, relative to single supply operation. This is due to the internal speed limit; the gain stage operates between VEE and + VS, and it is faster with higher reverse voltage bias due to reduced silicon junction capacitances. In many applications, as shown in the following examples, there is plenty of input overdrive. Even in applications providing low levels of overdrive, the LT1715 is fast enough that the absolute dispersion of 2ns (= 6 – 4) is often small enough to ignore. The gain and hysteresis stage of the LT1715 is simple, short and high speed to help prevent parasitic oscillations while adding minimum dispersion. This internal “self-latch” can be usefully exploited in many applications because it occurs early in the signal chain, in a low power, fully differential stage. It is therefore highly immune to disturbances from other parts of the circuit, such as the output, or on the supply lines. Once a high speed signal trips the hysteresis, the output will respond, after some propagation delay, without regard to these external influences that can cause trouble in nonhysteretic comparators. LT1715 U W U U APPLICATIO S I FOR ATIO ±VTRIP Test Circuit The input trip points test circuit uses a 1kHz triangle wave to repeatedly trip the comparator being tested. The LT1715 output is used to trigger switched capacitor sampling of the triangle wave, with a sampler for each direction. Because the triangle wave is attenuated 1000:1 and fed to the LT1715’s differential input, the sampled voltages are therefore 1000 times the input trip voltages. The hysteresis and offset are computed from the trip points as shown. W W SI PLIFIED SCHE ATIC VCC +VS 150Ω –IN OUTPUT 150Ω +IN GND VEE 1715 SS U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. MS10 Package 10-Lead Plastic MSOP (LTC DWG # 05-08-1661) 0.034 (0.86) REF 0.043 (1.10) MAX 0.007 (0.18) 0.118 ± 0.004* (3.00 ± 0.102) 10 9 8 7 6 0° – 6° TYP 0.021 ± 0.006 (0.53 ± 0.015) SEATING PLANE 0.007 – 0.011 (0.17 – 0.27) 0.0197 (0.50) BSC 0.005 ± 0.002 (0.13 ± 0.05) 0.118 ± 0.004** (3.00 ± 0.102) 0.193 ± 0.006 (4.90 ± 0.15) * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. MSOP (MS10) 1100 1 2 3 4 5 15 LT1715 U TYPICAL APPLICATIO Propagation delay of comparators is typically specified for a 100mV step with some fraction of that for overdrive. But in many signal processing applications, such as in communications, the goal is to convert a sine wave, such as a carrier, to a square wave for use as a timing clock. The desired behavior is for the output timing to be dependent on the input timing only. No phase shift should occur as a function of the input amplitude, which would result in AM to FM conversion. The circuit of Figure 12a is a simple LT1715-based sine wave to square wave converter. The ±5V supplies on the input allow very large swing inputs, while the 3V logic supply keeps the output swing small to minimize cross talk. Figure 12b shows the time delay vs input amplitude with a 10MHz sine wave. The LT1715 delay changes just 0.65ns over the 26dB amplitude range; 2.33° at 10MHz. The delay is particularly flat yielding excellent AM rejection from 0dBm to 15dBm. If a 2:1 transformer is used to drive the input differentially, this exceptionally flat zone spans – 5dBm to 10dBm, a common range for RF signal levels. 5V SINE WAVE INPUT With small input signals, the hysteresis and dispersion make the LT1715 act like a comparator with a 12mV hysteresis span. In other words, a 12mVP-P sine wave at 10MHz will barely toggle the LT1715, with 90° of phase lag or 25ns additional delay. Above 5VP-P at 10MHz, the LT1715 delay starts to decrease due to internal capacitive feed-forward in the input stage. Unlike some comparators, the LT1715 will not falsely anticipate a change in input polarity, but the feedforward is enough to make a transition propagate through the LT1715 faster once the input polarity does change. 5 4 3V + 50Ω Similar delay performance is achieved with input frequencies as high as 50MHz. There is, however, some additional encroachment into the central flat zone by both the small amplitude and large amplitude variations. TIME DELAY (ns) High Performance Sine Wave to Square Wave Converter SQUARE WAVE OUTPUT 25°C VCC = 5V VEE = – 5V +VS = 3V 10MHz 3 2 1 632mVP-P 1/2 LT1715 – –5V 0 –5 0 2VP-P 6.32VP-P 20 5 10 15 INPUT AMPLITUDE (dBm) 1715 F12a Figure 12a. LT1715-Based Sine Wave to Square Wave Converter 25 1715 F12b Figure 12b. Time Delay vs Sine Wave Input Amplitude RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1016 UltraFast Precision Comparator Industry Standard 10ns Comparator LT1116 12ns Single Supply Ground-Sensing Comparator Single Supply Version of LT1016 LT1394 7ns, UltraFast, Single Supply Comparator 6mA Single Supply Comparator LT1711/LT1712 4.5ns, 3V/5V/±5V Single/Dual Rail-to-Rail Comparators UltraFast Rail-to-Rail Input and Output Comparator LT1713/LT1714 7ns, Low Power, 3V/5V/±5V Single/Dual Rail-to-Rail Comparators Rail-to-Rail Input and Output Comparator LT1719 4.5ns Single Supply 3V/5V Comparator Single Comparator Similar to the LT1715 LT1720/LT1721 Dual/Quad 4.5ns, Single Supply 3V/5V Comparator Dual/Quad Comparator Similar to the LT1715 16 Linear Technology Corporation 1715f LT/TP 0401 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2001