5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator ADP5052 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT APPLICATIONS ADP5052 VDD C1 INT VREG OSCILLATOR 100mA RT C0 FB1 PVIN1 4.5V TO 15V BST1 C2 COMP1 CHANNEL 1 BUCK REGULATOR (1.2A/2.5A/4A) SW1 VOUT1 C4 PGND DL2 RILIM1 RILIM2 Q2 PVIN2 COMP2 L1 Q1 DL1 SS12 C5 C3 VREG EN1 CHANNEL 2 BUCK REGULATOR (1.2A/2.5A/4A) VREG VOUT2 SW2 BST2 EN2 C6 L2 C7 FB2 PWRGD PVIN3 C8 COMP3 EN3 BST3 CHANNEL 3 BUCK REGULATOR (1.2A) SW3 C9 L3 VOUT3 C10 FB3 PGND3 SS34 BST4 PVIN4 C11 COMP4 CHANNEL 4 BUCK REGULATOR (1.2A) EN4 1.7V TO 5.5V C14 Small cell base stations FPGA and processor applications Security and surveillance Medical applications SYNC/MODE VREG PVIN5 EN5 SW4 FB4 C12 L4 VOUT4 C13 PGND4 CHANNEL 5 200mA LDO REGULATOR VOUT5 FB5 VOUT5 C15 EXPOSED PAD Figure 1. GENERAL DESCRIPTION The ADP5052 combines four high performance buck regulators and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages up to 15 V with no preregulators. Channel 1 and Channel 2 integrate high-side power MOSFETs and low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and deliver a programmable output current of 1.2 A, 2.5 A, or 4 A. Combining Channel 1 and Channel 2 in a parallel configuration can provide a single output with up to 8 A of current. Rev. 0 Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver output current of 1.2 A. The switching frequency of the ADP5052 can be programmed or synchronized to an external clock. The ADP5052 contains a precision enable pin on each channel for easy power-up sequencing or adjustable UVLO threshold. The ADP5052 integrates a general-purpose LDO regulator with low quiescent current and low dropout voltage that provides up to 200 mA of output current. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 10900-001 Wide input voltage range: 4.5 V to 15 V ±1.5% output accuracy over full temperature range 250 kHz to 1.4 MHz adjustable switching frequency Adjustable/fixed output options via factory fuse Power regulation Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A sync buck regulators with low-side FET driver Channel 3 and Channel 4: 1.2 A sync buck regulators Channel 5: 200 mA low dropout (LDO) regulator Always alive 5.1 V LDO supply for tiny load demand Single 8 A output (Channel 1 and Channel 2 operated in parallel) Precision enable with 0.8 V accurate threshold Active output discharge switch FPWM or automatic PWM/PSM mode selection Frequency synchronization input or output Optional latch-off protection on OVP/OCP failure Power-good flag on selected channels UVLO, OCP, and TSD protection 48-lead, 7 mm × 7 mm LFCSP package −40°C to +125°C junction temperature ADP5052 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Shutdown .................................................................... 22 Applications ....................................................................................... 1 LDO Regulator ........................................................................... 22 Typical Application Circuit ............................................................. 1 Applications Information .............................................................. 23 General Description ......................................................................... 1 ADIsimPower Design Tool ....................................................... 23 Revision History ............................................................................... 2 Programming the Adjustable Output Voltage ........................ 23 Detailed Functional Block Diagram .............................................. 3 Voltage Conversion Limitations ............................................... 23 Specifications..................................................................................... 4 Current-Limit Setting ................................................................ 23 Buck Regulator Specifications .................................................... 5 Soft Start Setting ......................................................................... 24 LDO Regulator Specifications .................................................... 7 Inductor Selection ...................................................................... 24 Absolute Maximum Ratings ............................................................ 8 Output Capacitor Selection....................................................... 24 Thermal Resistance ...................................................................... 8 Input Capacitor Selection .......................................................... 25 ESD Caution .................................................................................. 8 Low-Side Power Device Selection ............................................ 25 Pin Configuration and Function Descriptions ............................. 9 Programming the UVLO Input ................................................ 25 Typical Performance Characteristics ........................................... 11 Compensation Components Design ....................................... 26 Theory of Operation ...................................................................... 17 Power Dissipation....................................................................... 26 Buck Regulator Operational Modes......................................... 17 Junction Temperature ................................................................ 27 Adjustable and Fixed Output Voltages .................................... 17 Design Example .............................................................................. 28 Internal Regulators (VREG and VDD) ................................... 17 Setting the Switching Frequency .............................................. 28 Separate Supply Applications .................................................... 18 Setting the Output Voltage ........................................................ 28 Low-Side Device Selection ........................................................ 18 Setting the Current Limit .......................................................... 28 Bootstrap Circuitry .................................................................... 18 Selecting the Inductor ................................................................ 28 Active Output Discharge Switch .............................................. 18 Selecting the Output Capacitor ................................................ 29 Precision Enabling ...................................................................... 18 Selecting the Low-Side MOSFET ............................................. 29 Oscillator ..................................................................................... 18 Designing the Compensation Network ................................... 29 Synchronization Input/Output ................................................. 19 Selecting the Soft Start Time..................................................... 29 Soft Start ...................................................................................... 19 Selecting the Input Capacitor ................................................... 29 Parallel Operation....................................................................... 20 Recommended External Components .................................... 30 Startup with Precharged Output .............................................. 20 Circuit Board Layout Recommendations ................................... 31 Current-Limit Protection .......................................................... 20 Typical Application Circuits ......................................................... 32 Frequency Foldback ................................................................... 21 Factory Programmable Options ................................................... 35 Hiccup Protection ...................................................................... 21 Factory Default Options ............................................................ 37 Latch-Off Protection .................................................................. 21 Outline Dimensions ....................................................................... 38 Undervoltage Lockout (UVLO) ............................................... 22 Ordering Guide .......................................................................... 38 Power-Good Function ............................................................... 22 REVISION HISTORY 5/13—Revision 0: Initial Version Rev. 0 | Page 2 of 40 Data Sheet ADP5052 DETAILED FUNCTIONAL BLOCK DIAGRAM CHANNEL 1 BUCK REGULATOR UVLO1 PVIN1 – 0.8V + + EN1 ACS1 – 1MΩ VREG HICCUP AND LATCH-OFF + OCP CLK1 – BST1 Q1 DRIVER + CMP1 – COMP1 0.8V FB1 + EA1 – CLK1 FREQUENCY FOLDBACK OVP LATCH-OFF + VID1 0.72V + 0.99V – PWRGD1 QDG1 CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION VREG SW1 DISCHARGE SWITCH SLOPE COMP DL1 DRIVER PGND ZERO CROSS – CURRENT-LIMIT SELECTION CURRENT BALANCE EN2 PVIN2 CHANNEL 2 BUCK REGULATOR BST2 COMP2 DUPLICATE CHANNEL 1 DL2 SW2 FB2 RT OSCILLATOR VREG SYNC/MODE SS12 SS34 PVIN1 PWRGD VREG INTERNAL REGULATOR HOUSEKEEPING LOGIC SOFT START DECODER VDD QPWRGD CHANNEL 3 BUCK REGULATOR UVLO3 PVIN3 – 0.8V + + EN3 ACS3 – 1MΩ VREG HICCUP AND LATCH-OFF + OCP CLK3 – BST3 Q3 DRIVER + CMP3 – COMP3 0.8V FB3 + EA3 – CLK3 FREQUENCY FOLDBACK OVP LATCH-OFF + VID3 0.72V EN4 + 0.99V – PWRGD3 SW3 CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION VREG Q4 DRIVER PGND3 ZERO CROSS – QDG3 DISCHARGE SWITCH SLOPE COMP PVIN4 CHANNEL 4 BUCK REGULATOR BST4 DUPLICATE CHANNEL 3 COMP4 SW4 FB4 PGND4 CHANNEL 5 LDO REGULATOR VOUT5 PVIN5 0.8V + Q7 LDO CONTROL 1MΩ – EA5 + 0.5V FB5 10900-202 EN5 – Figure 2. Rev. 0 | Page 3 of 40 ADP5052 Data Sheet SPECIFICATIONS VIN = 12 V, VVREG = 5.1 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter INPUT SUPPLY VOLTAGE RANGE QUIESCENT CURRENT Operating Quiescent Current UNDERVOLTAGE LOCKOUT Rising Threshold Falling Threshold Hysteresis OSCILLATOR CIRCUIT Switching Frequency Switching Frequency Range SYNC Input Input Clock Range Input Clock Pulse Width Minimum On Time Minimum Off Time Input Clock High Voltage Input Clock Low Voltage SYNC Output Clock Frequency Positive Pulse Duty Cycle Rise or Fall Time High Level Voltage PRECISION ENABLING High Level Threshold Low Level Threshold Pull-Down Resistor POWER GOOD Internal Power-Good Rising Threshold Internal Power-Good Hysteresis Internal Power-Good Falling Delay Rising Delay for PWRGD Pin Leakage Current for PWRGD Pin Output Low Voltage for PWRGD Pin INTERNAL REGULATORS VDD Output Voltage VDD Current Limit VREG Output Voltage VREG Dropout Voltage VREG Current Limit THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Symbol VIN IQ(4-BUCKS) ISHDN(4BUCKS+LDO) UVLO VUVLO-RISING VUVLO-FALLING VHYS Min 4.5 3.6 fSW 700 250 fSYNC 250 tSYNC_MIN_ON tSYNC_MIN_OFF VH(SYNC) VL(SYNC) 100 100 1.3 Typ Max 15.0 Unit V 4.8 25 6.25 65 mA µA 4.2 3.78 0.42 4.36 V V V 740 780 1400 kHz kHz 1400 kHz 0.4 ns ns V V fCLK tCLK_PULSE_DUTY tCLK_RISE_FALL VH(SYNC_OUT) fSW 50 10 VVREG VTH_H(EN) VTH_L(EN) RPULL-DOWN(EN) 0.806 0.725 1.0 0.832 V V MΩ 90.5 3.3 50 1 0.1 50 95 % % µs ms µA mV Test Conditions/Comments PVIN1, PVIN2, PVIN3, PVIN4 pins PVIN1, PVIN2, PVIN3, PVIN4 pins No switching, all ENx pins high All ENx pins low PVIN1, PVIN2, PVIN3, PVIN4 pins RT = 25.5 kΩ kHz % ns V EN1, EN2, EN3, EN4, EN5 pins 0.688 VPWRGD(RISE) VPWRGD(HYS) tPWRGD_FALL tPWRGD_PIN_RISE IPWRGD_LEAKAGE VPWRGD_LOW 86.3 VVDD ILIM_VDD VVREG VDROPOUT ILIM_VREG 3.2 20 4.9 TSHDN THYS 50 3.305 51 5.1 225 95 150 15 Rev. 0 | Page 4 of 40 1 100 3.4 80 5.3 140 V mA V mV mA °C °C IPWRGD = 1 mA IVDD = 10 mA IVREG = 50 mA Data Sheet ADP5052 BUCK REGULATOR SPECIFICATIONS VIN = 12 V, VVREG = 5.1 V, fSW = 600 kHz for all channels, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter CHANNEL 1 SYNC BUCK REGULATOR FB1 Pin Fixed Output Options Adjustable Feedback Voltage Feedback Voltage Accuracy Feedback Bias Current SW1 Pin High-Side Power FET On Resistance Current-Limit Threshold Minimum On Time Minimum Off Time Low-Side Driver, DL1 Pin Rising Time Falling Time Sourcing Resistor Sinking Resistor Error Amplifier (EA), COMP1 Pin EA Transconductance Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance CHANNEL 2 SYNC BUCK REGULATOR FB2 Pin Fixed Output Options Adjustable Feedback Voltage Feedback Voltage Accuracy Symbol Min VOUT1 VFB1 VFB1(DEFAULT) 0.85 Typ −0.55 −1.25 −1.5 RDSON(1H) tRISING1 tFALLING1 tSOURCING1 tSINKING1 20 3.4 10 0.95 3.50 1.91 4.95 310 470 tSS1 V V % % % µA Fuse trim TJ = 25°C 0°C ≤ TJ ≤ 85°C −40°C ≤ TJ ≤ +125°C Adjustable voltage mΩ Pin-to-pin measurement A A A ns ns RILIM1 = floating RILIM1 = 47 kΩ RILIM1 = 22 kΩ fSW = 250 kHz to 1.4 MHz fSW = 250 kHz to 1.4 MHz ns ns Ω Ω CISS = 1.2 nF CISS = 1.2 nF 5.28 3.08 7.48 155 620 2.0 2.0 8.0 tHICCUP1 RDIS1 7 × tSS1 250 3.3 5.0 0.800 −0.55 −1.25 −1.5 +0.55 +1.0 +1.5 0.1 Feedback Bias Current SW2 Pin High-Side Power FET On Resistance Current-Limit Threshold IFB2 Minimum On Time Minimum Off Time Low-Side Driver, DL2 Pin Rising Time Falling Time Sourcing Resistor Sinking Resistor tMIN_ON2 tMIN_OFF2 4.4 2.63 6.44 117 1/9 × tSW tRISING2 tFALLING2 tSOURCING2 tSINKING2 20 3.4 10 0.95 RDSON(2H) ITH(ILIM2) 1.60 100 tMIN_ON1 tMIN_OFF1 VOUT2 VFB2 VFB2(DEFAULT) Test Conditions/Comments +0.55 +1.0 +1.5 0.1 4.4 2.63 6.44 117 1/9 × tSW gm1 Unit 0.800 IFB1 ITH(ILIM1) Max 110 3.50 1.91 4.95 Rev. 0 | Page 5 of 40 5.28 3.08 7.48 155 µS ms ms ms Ω SS12 connected to VREG V V % % % µA Fuse trim mΩ Pin-to-pin measurement A A A ns ns RILIM2 = floating RILIM2 = 47 kΩ RILIM2 = 22 kΩ fSW = 250 kHz to 1.4 MHz fSW = 250 kHz to 1.4 MHz ns ns Ω Ω CISS = 1.2 nF CISS = 1.2 nF TJ = 25°C 0°C ≤ TJ ≤ 85°C −40°C ≤ TJ ≤ +125°C Adjustable voltage ADP5052 Parameter Error Amplifier (EA), COMP2 Pin EA Transconductance Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance CHANNEL 3 SYNC BUCK REGULATOR FB3 Pin Fixed Output Options Adjustable Feedback Voltage Feedback Voltage Accuracy Feedback Bias Current SW3 Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance Current-Limit Threshold Minimum On Time Minimum Off Time Error Amplifier (EA), COMP3 Pin EA Transconductance Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance CHANNEL 4 SYNC BUCK REGULATOR FB4 Pin Fixed Output Options Adjustable Feedback Voltage Feedback Voltage Accuracy Feedback Bias Current SW4 Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance Current-Limit Threshold Minimum On Time Minimum Off Time Error Amplifier (EA), COMP4 Pin EA Transconductance Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance Data Sheet Symbol Min Typ Max Unit gm2 310 470 620 µS tSS2 2.0 2.0 8.0 tHICCUP2 RDIS2 VOUT3 VFB3 VFB3(DEFAULT) 7 × tSS2 250 1.20 1.80 0.800 −0.55 −1.25 −1.5 +0.55 +1.0 +1.5 0.1 IFB3 Test Conditions/Comments ms ms ms Ω SS12 connected to VREG V V % % % µA Fuse trim TJ = 25°C 0°C ≤ TJ ≤ 85°C −40°C ≤ TJ ≤ +125°C Adjustable voltage RDSON(3H) 225 mΩ Pin-to-pin measurement RDSON(3L) 150 mΩ Pin-to-pin measurement fSW = 250 kHz to 1.4 MHz fSW = 250 kHz to 1.4 MHz ITH(ILIM3) tMIN_ON3 tMIN_OFF3 1.7 gm3 310 tSS3 2.2 90 1/9 × tSW 2.55 120 A ns ns 470 620 µS 2.0 2.0 8.0 tHICCUP3 RDIS3 VOUT4 VFB4 VFB4(DEFAULT) 7 × tSS3 250 2.5 5.5 0.800 −0.55 −1.25 −1.5 +0.55 +1.0 +1.5 0.1 IFB4 ms ms ms Ω SS34 connected to VREG V V % % % µA Fuse trim TJ = 25°C 0°C ≤ TJ ≤ 85°C −40°C ≤ TJ ≤ +125°C RDSON(4H) 225 mΩ Pin-to-pin measurement RDSON(4L) 150 mΩ Pin-to-pin measurement fSW = 250 kHz to 1.4 MHz fSW = 250 kHz to 1.4 MHz ITH(ILIM4) tMIN_ON4 tMIN_OFF4 1.7 gm4 310 tSS4 2.2 90 1/9 × tSW 2.55 120 A ns ns 470 620 µS 2.0 2.0 tHICCUP4 RDIS4 8.0 7 × tSS4 250 Rev. 0 | Page 6 of 40 ms ms ms Ω SS34 connected to VREG Data Sheet ADP5052 LDO REGULATOR SPECIFICATIONS VIN5 = (VOUT5 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = COUT = 1 µF; TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 3. Parameter INPUT SUPPLY VOLTAGE RANGE OPERATIONAL SUPPLY CURRENT Bias Current for LDO Regulator VOLTAGE FEEDBACK (FB5 PIN) Adjustable Feedback Voltage Feedback Voltage Accuracy Min 1.7 Typ Max 5.5 Unit V Test Conditions/Comments PVIN5 pin 30 60 145 130 170 320 µA µA µA IOUT5 = 200 µA IOUT5 = 10 mA IOUT5 = 200 mA +1.0 +1.6 +2.0 V % % % 0.500 −1.0 −1.6 −2.0 DROPOUT VOLTAGE CURRENT-LIMIT THRESHOLD OUTPUT NOISE POWER SUPPLY REJECTION RATIO 250 80 100 180 510 mV mV mV mA 92 µV rms 77 66 dB dB Rev. 0 | Page 7 of 40 TJ = 25°C 0°C ≤ TJ ≤ 85°C −40°C ≤ TJ ≤ +125°C IOUT5 = 200 mA VOUT5 = 3.3 V VOUT5 = 2.5 V VOUT5 = 1.5 V Specified from the output voltage drop to 90% of the specified typical value 10 Hz to 100 kHz, VPVIN5 = 5 V, VOUT5 = 1.8 V VPVIN5 = 5 V, VOUT5 = 1.8 V, IOUT5 = 1 mA 10 kHz 100 kHz ADP5052 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Parameter PVIN1 to PGND PVIN2 to PGND PVIN3 to PGND3 PVIN4 to PGND4 PVIN5 to GND SW1 to PGND SW2 to PGND SW3 to PGND3 SW4 to PGND4 PGND to GND PGND3 to GND PGND4 to GND BST1 to SW1 BST2 to SW2 BST3 to SW3 BST4 to SW4 DL1 to PGND DL2 to PGND SS12, SS34 to GND EN1, EN2, EN3, EN4, EN5 to GND VREG to GND SYNC/MODE to GND VOUT5, FB5 to GND RT to GND PWRGD to GND FB1, FB2, FB3, FB4 to GND1 FB2 to GND2 FB4 to GND2 COMP1, COMP2, COMP3, COMP4 to GND VDD to GND Storage Temperate Range Operational Junction Temperature Range 1 2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +6.5 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +3.6 V −0.3 V to +6.5 V −0.3 V to +3.6 V −0.3 V to +6.5 V −0.3 V to +7 V −0.3 V to +3.6 V THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 48-Lead LFCSP ESD CAUTION −0.3 V to +3.6 V −65°C to +150°C −40°C to +125°C This rating applies to the adjustable output voltage models of the ADP5052. This rating applies to the fixed output voltage models of the ADP5052. Rev. 0 | Page 8 of 40 θJA 27.87 θJC 2.99 Unit °C/W Data Sheet ADP5052 48 47 46 45 44 43 42 41 40 39 38 37 EN3 SS34 COMP3 FB3 VREG SYNC/MODE VDD RT FB1 COMP1 SS12 EN1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP5052 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 PVIN1 PVIN1 SW1 SW1 BST1 DL1 PGND DL2 BST2 SW2 SW2 PVIN2 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED AND SOLDERED TO AN EXTERNAL GROUND PLANE. 10900-002 GND EN4 COMP4 FB4 GND GND GND PWRGD FB2 COMP2 EN2 PVIN2 13 14 15 16 17 18 19 20 21 22 23 24 BST3 1 PGND3 2 SW3 3 PVIN3 4 EN5 5 FB5 6 VOUT5 7 PVIN5 8 PVIN4 9 SW4 10 PGND4 11 BST4 12 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17, 18, 19 20 21 22 23 24, 25 26, 27 28 29 Mnemonic BST3 PGND3 SW3 PVIN3 EN5 FB5 VOUT5 PVIN5 PVIN4 SW4 PGND4 BST4 GND EN4 COMP4 FB4 GND PWRGD FB2 COMP2 EN2 PVIN2 SW2 BST2 DL2 30 31 PGND DL1 32 BST1 Description High-Side FET Driver Power Supply for Channel 3. Power Ground for Channel 3. Switching Node Output for Channel 3. Power Input for Channel 3. Connect a bypass capacitor between this pin and ground. Enable Input for Channel 5. An external resistor divider can be used to set the turn-on threshold. Feedback Sensing Input for Channel 5. Power Output for Channel 5. Power Input for Channel 5. Connect a bypass capacitor between this pin and ground. Power Input for Channel 4. Connect a bypass capacitor between this pin and ground. Switching Node Output for Channel 4. Power Ground for Channel 4. High-Side FET Driver Power Supply for Channel 4. This pin is for internal test purposes. Connect this pin to ground. Enable Input for Channel 4. An external resistor divider can be used to set the turn-on threshold. Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground. Feedback Sensing Input for Channel 4. These pins are for internal test purposes. Connect these pins to ground. Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels. Feedback Sensing Input for Channel 2. Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground. Enable Input for Channel 2. An external resistor divider can be used to set the turn-on threshold. Power Input for Channel 2. Connect a bypass capacitor between this pin and ground. Switching Node Output for Channel 2. High-Side FET Driver Power Supply for Channel 2. Low-Side FET Gate Driver for Channel 2. Connect a resistor from this pin to ground to program the current-limit threshold for Channel 2. Power Ground for Channel 1 and Channel 2. Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current-limit threshold for Channel 1. High-Side FET Driver Power Supply for Channel 1. Rev. 0 | Page 9 of 40 ADP5052 Pin No. 33, 34 35, 36 Mnemonic SW1 PVIN1 37 38 EN1 SS12 39 40 41 COMP1 FB1 RT 42 43 VDD SYNC/MODE 44 45 46 47 VREG FB3 COMP3 SS34 48 EN3 EPAD Data Sheet Description Switching Node Output for Channel 1. Power Input for the Internal 5.1 V VREG Linear Regulator and the Channel 1 Buck Regulator. Connect a bypass capacitor between this pin and ground. Enable Input for Channel 1. An external resistor divider can be used to set the turn-on threshold. Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 1 and Channel 2 (see the Soft Start section). This pin is also used to configure parallel operation of Channel 1 and Channel 2 (see the Parallel Operation section). Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground. Feedback Sensing Input for Channel 1. Connect a resistor from RT to ground to program the switching frequency from 250 kHz to 1.4 MHz. For more information, see the Oscillator section. Output of the Internal 3.3 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground. Synchronization Input/Output (SYNC). To synchronize the switching frequency of the part to an external clock, connect this pin to an external clock with a frequency from 250 kHz to 1.4 MHz. This pin can also be configured as a synchronization output by factory fuse. Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, the part operates in forced PWM (FPWM) mode. When this pin is logic low, the part operates in automatic PWM/PSM mode. Output of the Internal 5.1 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground. Feedback Sensing Input for Channel 3. Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground. Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 3 and Channel 4 (see the Soft Start section). Enable Input for Channel 3. An external resistor divider can be used to set the turn-on threshold. Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane. Rev. 0 | Page 10 of 40 Data Sheet ADP5052 100 100 90 90 80 80 70 70 60 50 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VOUT = 5.0V 40 30 20 40 VOUT = 1.2V, FPWM VOUT = 1.2V, AUTO PWM/PSM VOUT = 1.8V, FPWM VOUT = 1.8V, AUTO PWM/PSM VOUT = 3.3V, FPWM VOUT = 3.3V, AUTO PWM/PSM 20 10 0 1 2 IOUT (A) 3 4 0 10900-003 0 Figure 4. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, fSW = 600 kHz, FPWM Mode 0 100 90 90 80 80 70 70 50 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 40 30 20 1 10 Figure 7. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, fSW = 600 kHz, FPWM and Automatic PWM/PSM Modes 100 60 0.1 IOUT (A) EFFICIENCY (%) 60 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VOUT = 5.0V 50 40 30 20 0 1 2 IOUT (A) 3 4 0 10900-004 0 Figure 5. Channel 1/Channel 2 Efficiency Curve, VIN = 5.0 V, fSW = 600 kHz, FPWM Mode 0 100 90 80 80 70 EFFICIENCY (%) 50 40 1.2 40 30 20 10 10 4 0 10900-005 0 Figure 6. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, VOUT = 1.8 V, FPWM Mode VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 50 20 3 1.0 60 30 2 IOUT (A) 0.8 70 fSW = 300kHz fSW = 600kHz fSW = 1.0MHz 1 0.6 Figure 8. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, fSW = 600 kHz, FPWM Mode 90 0 0.4 IOUT (A) 100 60 0.2 10900-007 10 10 0 0.2 0.4 0.6 IOUT (A) 0.8 1.0 1.2 10900-008 EFFICIENCY (%) 50 30 10 EFFICIENCY (%) 60 10900-006 EFFICIENCY (%) EFFICIENCY (%) TYPICAL PERFORMANCE CHARACTERISTICS Figure 9. Channel 3/Channel 4 Efficiency Curve, VIN = 5.0 V, fSW = 600 kHz, FPWM Mode Rev. 0 | Page 11 of 40 ADP5052 Data Sheet 100 0.4 90 0.3 LINE REGULATION (%) 80 60 50 40 30 fSW = 300kHz fSW = 600kHz fSW = 1.0MHz 20 0.2 0.4 0 –0.1 –0.3 0.6 0.8 1.0 1.2 IOUT (A) –0.4 10900-009 0 0.1 –0.2 10 0 0.2 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 INPUT VOLTAGE (V) 10900-012 EFFICIENCY (%) 70 Figure 13. Channel 1 Line Regulation, VOUT = 3.3 V, IOUT = 4 A, fSW = 600 kHz, FPWM Mode Figure 10. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, VOUT = 1.8 V, FPWM Mode 0.4 100 90 0.3 LOAD REGULATION (%) 80 60 50 VOUT = 1.2V, FPWM VOUT = 1.2V, AUTO PWM/PSM VOUT = 1.8V, FPWM VOUT = 1.8V, AUTO PWM/PSM VOUT = 3.3V, FPWM VOUT = 3.3V, AUTO PWM/PSM 20 10 0.1 IOUT (A) 1 –0.1 –0.3 2 Figure 11. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, fSW = 600 kHz, FPWM and Automatic PWM/PSM Modes –0.4 0 0.3 0.3 0.2 0.2 LINE REGULATION (%) 0.4 0 –0.1 –0.3 2 IOUT (A) 3 4 1.0 1.2 –0.1 –0.3 1 0.8 0 –0.2 0 0.6 0.1 –0.2 –0.4 0.4 Figure 14. Channel 3 Load Regulation, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz, FPWM Mode 0.4 0.1 0.2 IOUT (A) 10900-011 LOAD REGULATION (%) 0 –0.2 0 0 0.1 10900-013 30 0.2 Figure 12. Channel 1 Load Regulation, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz, FPWM Mode Rev. 0 | Page 12 of 40 –0.4 4.5 6.0 7.5 9.0 10.5 12.0 INPUT VOLTAGE (V) 13.5 15.0 Figure 15. Channel 3 Line Regulation, VOUT = 3.3 V, IOUT = 1 A, fSW = 600 kHz, FPWM Mode 10900-014 40 10900-010 EFFICIENCY (%) 70 Data Sheet ADP5052 75 0.4 65 0.3 SHUTDOWN CURRENT (µA) FEEDBACK VOLTAGE ACCURACY (%) 0.5 0.2 0.1 0 –0.1 –0.2 –0.3 55 45 VIN = 4.5V VIN = 7.0V VIN = 12V VIN = 15V 35 25 –20 10 40 70 100 130 TEMPERATURE (°C) 15 –50 10900-015 –0.5 –50 Figure 16. 0.8 V Feedback Voltage Accuracy vs. Temperature for Channel 1, Adjustable Output Model –25 0 25 50 75 TEMPERATURE (°C) 100 125 150 10900-019 –0.4 Figure 19. Shutdown Current vs. Temperature (EN1, EN2, EN3, EN4, and EN5 Low) 850 5.0 4.8 4.6 UVLO THRESHOLD (V) FREQUENCY (kHz) 800 750 700 650 4.4 RISING 4.2 4.0 FALLING 3.8 3.6 3.4 600 10 40 70 100 130 TEMPERATURE (°C) 3.0 –50 10900-017 –20 –20 10 40 70 100 130 TEMPERATURE (°C) 10900-020 3.2 550 –50 Figure 20. UVLO Threshold vs. Temperature Figure 17. Frequency vs. Temperature, VIN = 12 V 6.0 7 RILIM = 22kΩ 6 CURRENT LIMIT (A) 5.0 4.5 4.0 5 RILIM = OPEN 4 3 RILIM = 47kΩ 2 3.5 –25 0 25 50 75 TEMPERATURE (°C) 100 125 150 10900-018 3.0 –50 1 Figure 18. Quescient Current vs. Temperature (Includes PVIN1, PVIN2, PVIN3, and PVIN4) Rev. 0 | Page 13 of 40 0 4 6 8 10 12 14 16 INPUT VOLTAGE (V) Figure 21. Channel 1/Channel 2 Current Limit vs. Input Voltage 10900-021 QUIESCENT CURRENT (mA) 5.5 ADP5052 Data Sheet 200 180 180 160 140 140 100 CH1/CH2 CH3/CH4 80 60 VOUT = 1.8V 80 60 VOUT = 1.2V 20 20 10 40 70 TEMPERATURE (°C) 100 130 0 10900-022 –20 1 100 IOUT (mA) 0 2.5 –20 2.4 –40 PSRR (dB) 2.6 2.3 IOUT = 1mA IOUT = 10mA IOUT = 50mA IOUT = 100mA IOUT = 150mA IOUT = 200mA 2.2 10 Figure 25. Channel 5 (LDO Regulator) Output Noise vs. Output Load, VIN = 5 V, COUT = 1 µF Figure 22. Minimum On Time vs. Temperature IOUT = 1mA IOUT = 10mA IOUT = 50mA IOUT = 100mA IOUT = 150mA IOUT = 200mA –60 –80 –100 2.1 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE (V) –120 10 10900-023 2.0 2.0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 10900-026 OUTPUT VOLTAGE (V) 100 40 40 0 –50 VOUT = 2.5V 120 10900-025 120 RMS NOISE (µV) MINIMUM ON TIME (ns) 160 VOUT = 3.3V Figure 26. Channel 5 (LDO Regulator) PSRR over Output Load, VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF Figure 23. Channel 5 (LDO Regulator) Line Regulation over Output Load 100 0 PVIN5 = PVIN5 = PVIN5 = PVIN5 = PVIN5 = PVIN5 = –10 –20 10 4.0V; IOUT = 1mA 3.6V, IOUT = 1mA 4.0V, IOUT = 100mA 3.6V, IOUT = 100mA 4.0V, IOUT = 200mA 3.6V, IOUT = 200mA PSRR (dB) 1 VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V –40 –50 –60 –70 0.1 –80 0.01 10 100 1k 10k 100k FREQUENCY (Hz) –100 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 27. Channel 5 (LDO Regulator) PSRR over Various Loads and Dropout Voltages, VOUT = 3.3 V, COUT = 1 µF Figure 24. Channel 5 (LDO Regulator) Output Noise Spectrum, VIN = 5 V, COUT = 1 µF, IOUT = 10 mA Rev. 0 | Page 14 of 40 10900-027 –90 10900-024 NOISE (µV/√Hz) –30 Data Sheet ADP5052 VOUT 2 VOUT 2 SW IOUT2 IOUT1 1 M1.00µs A CH1 7.40V CH2 100mV BW M100µs A CH2 CH3 2.00A Ω BW CH4 2.00A Ω BW Figure 28. Steady State Waveform at Heavy Load, VIN = 12 V, VOUT = 3.3 V, IOUT = 3 A, fSW = 600 kHz, L = 4.7 µH, COUT = 47 µF × 2, FPWM Mode –56.0mV 10900-031 CH1 5.00V CH2 10.0mV BW 10900-028 4 Figure 31. Load Transient, Channel 1/Channel 2 Parallel Output, 0 A to 6 A, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz, L = 4.7 µH, COUT = 47 µF × 4 VOUT 1 VOUT 2 IOUT 4 SW EN 2 1 A CH1 11.0mV CH1 500mV BW CH3 5.00V BW Figure 29. Steady State Waveform at Light Load, VIN = 12 V, VOUT = 3.3 V, IOUT = 30 mA, fSW = 600 kHz, L = 4.7 µH, COUT = 47 µF × 2, Automatic PWM/PSM Mode M1.00ms CH2 5.00V CH4 2.00A Ω A CH1 650mV 10900-032 CH1 5.00V CH2 50.0mV BW M100µs 10900-029 PWRGD 3 Figure 32. Channel 1/Channel 2 Soft Start with 4 A Resistance Load, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2 VIN 1 1 VOUT VOUT EN 3 IOUT 2 IOUT 4 M100µs CH4 2.00A Ω A CH1 –22.0mV CH1 10.0V BW CH3 1.00V BW Figure 30. Channel 1/Channel 2 Load Transient, 1 A to 4 A, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz, L = 2.2 µH, COUT = 47 µF × 2 Rev. 0 | Page 15 of 40 M400µs CH2 5.00V BW CH4 1.00A Ω BW A CH2 2.80V 10900-033 CH1 50.0mV BW 10900-030 4 Figure 33. Startup with Precharged Output, VIN = 12 V, VOUT = 3.3 V ADP5052 Data Sheet VOUT VOUT 1 1 IOUT 4 SW 2 EN 2 IOUT 4 PWRGD M10.0ms A CH1 CH2 5.00V BW CH4 5.00A Ω BW 650mV CH1 500mV BW Figure 34. Channel 1/Channel 2 Shutdown with Active Output Discharge, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2 1 VOUT SW 2 IOUT CH1 500mV BW CH2 10.00V BW CH4 5.00A Ω M10.0ms A CH1 970mV 10900-135 4 Figure 35. Short-Circuit Protection Entry, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2 Rev. 0 | Page 16 of 40 M10.0ms A CH1 CH2 10.0V BW CH4 5.00A Ω BW 970mV 10900-136 CH1 500mV BW CH3 5.00V BW 10900-034 3 Figure 36. Short-Circuit Protection Recovery, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2 Data Sheet ADP5052 THEORY OF OPERATION The ADP5052 is a micropower management unit that combines four high performance buck regulators with a 200 mA low dropout (LDO) regulator in a 48-lead LFCSP package to meet demanding performance and board space requirements. The device enables direct connection to high input voltages up to 15 V with no preregulators to make applications simpler and more efficient. BUCK REGULATOR OPERATIONAL MODES PWM Mode In pulse-width modulation (PWM) mode, the buck regulators in the ADP5052 operate at a fixed frequency; this frequency is set by an internal oscillator that is programmed by the RT pin. At the start of each oscillator cycle, the high-side MOSFET turns on and sends a positive voltage across the inductor. The inductor current increases until the current-sense signal exceeds the peak inductor current threshold that turns off the high-side MOSFET; this threshold is set by the error amplifier output. During the high-side MOSFET off time, the inductor current decreases through the low-side MOSFET until the next oscillator clock pulse starts a new cycle. The buck regulators in the ADP5052 regulate the output voltage by adjusting the peak inductor current threshold. PSM Mode To achieve higher efficiency, the buck regulators in the ADP5052 smoothly transition to variable frequency power save mode (PSM) operation when the output load falls below the PSM current threshold. When the output voltage falls below regulation, the buck regulator enters PWM mode for a few oscillator cycles until the voltage increases to within regulation. During the idle time between bursts, the MOSFET turns off, and the output capacitor supplies all the output current. The PSM comparator monitors the internal compensation node, which represents the peak inductor current information. The average PSM current threshold depends on the input voltage (VIN), the output voltage (VOUT), the inductor, and the output capacitor. Because the output voltage occasionally falls below regulation and then recovers, the output voltage ripple in PSM operation is larger than the ripple in the forced PWM mode of operation under light load conditions. Forced PWM and Automatic PWM/PSM Modes The buck regulators can be configured to always operate in PWM mode using the SYNC/MODE pin. In forced PWM (FPWM) mode, the regulator continues to operate at a fixed frequency even when the output current is below the PWM/PSM threshold. In PWM mode, efficiency is lower compared to PSM mode under light load conditions. The low-side MOSFET remains on when the inductor current falls to less than 0 A, causing the ADP5052 to enter continuous conduction mode (CCM). The buck regulators can be configured to operate in automatic PWM/PSM mode using the SYNC/MODE pin. In automatic PWM/PSM mode, the buck regulators operate in either PWM mode or PSM mode, depending on the output current. When the average output current falls below the PWM/PSM threshold, the buck regulator enters PSM mode operation; in PSM mode, the regulator operates with a reduced switching frequency to maintain high efficiency. The low-side MOSFET turns off when the output current reaches 0 A, causing the regulator to operate in discontinuous mode (DCM). When the SYNC/MODE pin is connected to VREG, the part operates in forced PWM (FPWM) mode. When the SYNC/ MODE pin is connected to ground, the part operates in automatic PWM/PSM mode. ADJUSTABLE AND FIXED OUTPUT VOLTAGES The ADP5052 provides adjustable and fixed output voltage settings via factory fuse. For the adjustable output settings, use an external resistor divider to set the desired output voltage via the feedback reference voltage (0.8 V for Channel 1 to Channel 4, and 0.5 V for Channel 5). For the fixed output settings, the feedback resistor divider is built into the ADP5052, and the feedback pin (FBx) must be tied directly to the output. Table 7 lists the available fixed output voltage ranges for each buck regulator channel. Table 7. Fixed Output Voltage Ranges Channel Channel 1 Channel 2 Channel 3 Channel 4 Fixed Output Voltage Range 0.85 V to 1.6 V in 25 mV steps 3.3 V to 5.0 V in 300 mV or 200 mV steps 1.2 V to 1.8 V in 100 mV steps 2.5 V to 5.5 V in 100 mV steps The output range can also be programmed by factory fuse. If a different output voltage range is required, contact your local Analog Devices, Inc., sales or distribution representative. INTERNAL REGULATORS (VREG AND VDD) The internal VREG regulator in the ADP5052 provides a stable 5.1 V power supply for the bias voltage of the MOSFET drivers. The internal VDD regulator in the ADP5052 provides a stable 3.3 V power supply for internal control circuits. Connect a 1.0 µF ceramic capacitor between VREG and ground; connect another 1.0 µF ceramic capacitor between VDD and ground. The internal VREG and VDD regulators are active as long as PVIN1 is available. The internal VREG regulator can provide a total load of 95 mA including the MOSFET driving current, and it can be used as an always alive 5.1 V power supply for a small system current demand. The current-limit circuit is included in the VREG regulator to protect the circuit when the part is heavily loaded. The VDD regulator is for internal circuit use and is not recommended for other purposes. Rev. 0 | Page 17 of 40 ADP5052 Data Sheet SEPARATE SUPPLY APPLICATIONS PRECISION ENABLING The ADP5052 supports separate input voltages for the four buck regulators. This means that the input voltages for the four buck regulators can be connected to different supply voltages. The ADP5052 has an enable control pin for each regulator, including the LDO regulator. The enable control pin (ENx) features a precision enable circuit with a 0.8 V reference voltage. When the voltage at the ENx pin is greater than 0.8 V, the regulator is enabled. When the voltage at the ENx pin falls below 0.725 V, the regulator is disabled. An internal 1 MΩ pull-down resistor prevents errors if the ENx pin is left floating. Precision enabling can be used to monitor the PVIN1 voltage and to delay the startup of the outputs to ensure that PVIN1 is high enough to support the outputs in regulation. For more information, see the Precision Enabling section. The ADP5052 supports cascading supply operation for the four buck regulators. As shown in Figure 37, PVIN2, PVIN3, and PVIN4 are powered from the Channel 1 output. In this configuration, the Channel 1 output voltage must be higher than the UVLO threshold for PVIN2, PVIN3, and PVIN4. The precision enable threshold voltage allows easy sequencing of channels within the part, as well as sequencing between the ADP5052 and other input/output supplies. The ENx pin can also be used as a programmable UVLO input using a resistor divider (see Figure 38). For more information, see the Programming the UVLO Input section. ADP5052 INPUT/OUTPUT VOLTAGE INTERNAL ENABLE DEGLITCH TIMER 0.8V R1 ENx 1MΩ PVIN1 VOUT1 Figure 38. Precision Enable Diagram for One Channel OSCILLATOR VOUT2 TO VOUT4 The switching frequency (fSW) of the ADP5052 can be set to a value from 250 kHz to 1.4 MHz by connecting a resistor from the RT pin to ground. The value of the RT resistor can be calculated as follows: BUCK 2 10900-036 PVIN2 TO PVIN4 BUCK 1 Figure 37. Cascading Supply Application LOW-SIDE DEVICE SELECTION RRT (kΩ) = [14,822/fSW (kHz)]1.081 BOOTSTRAP CIRCUITRY Each buck regulator in the ADP5052 has an integrated bootstrap regulator. The bootstrap regulator requires a 0.1 µF ceramic capacitor (X5R or X7R) between the BSTx and SWx pins to provide the gate drive voltage for the high-side MOSFET. Figure 39 shows the typical relationship between the switching frequency (fSW) and the RT resistor. The adjustable frequency allows users to make decisions based on the trade-off between efficiency and solution size. 1.6M 1.4M 1.2M FREQUENCY (Hz) The buck regulators in Channel 1 and Channel 2 integrate 4 A high-side power MOSFETs and low-side MOSFET drivers. The N-channel MOSFETs selected for use with the ADP5052 must be able to work with the synchronized buck regulators. In general, a low RDSON N-channel MOSFET can be used to achieve higher efficiency; dual MOSFETs in one package (for both Channel 1 and Channel 2) are recommended to save space on the PCB. For more information, see the Low-Side Power Device Selection section. 1.0M 800k 600k 400k ACTIVE OUTPUT DISCHARGE SWITCH 200k Each buck regulator in the ADP5052 integrates a discharge switch from the switching node to ground. This switch is turned on when its associated regulator is disabled, which helps to discharge the output capacitor quickly. The typical value of the discharge switch is 250 Ω for Channel 1 to Channel 4. The discharge switch function can be enabled or disabled for all four buck regulators by factory fuse. 0 0 20 40 RT RESISTOR (kΩ) 60 80 10900-044 VIN R2 10900-037 The PVIN1 voltage provides the power supply for the internal regulators and the control circuitry. Therefore, if the user plans to use separate supply voltages for the buck regulators, the PVIN1 voltage must be above the UVLO threshold before the other channels begin to operate. Figure 39. Switching Frequency vs. RT Resistor For Channel 1 and Channel 3, the frequency can be set to half the master switching frequency set by the RT pin. This setting can be selected by factory fuse. If the master switching frequency is less than 250 kHz, this halving of the frequency for Channel 1 or Channel 3 is not recommended. Rev. 0 | Page 18 of 40 Data Sheet ADP5052 Phase Shift The phase shift between Channel 1 and Channel 2 and between Channel 3 and Channel 4 is 180°. Therefore, Channel 3 is in phase with Channel 1, and Channel 4 is in phase with Channel 2 (see Figure 40). This phase shift maximizes the benefits of out-of-phase operation by reducing the input ripple current and lowering the ground noise. In the configuration shown in Figure 41, the phase shift between Channel 1 of the first ADP5052 device and Channel 1 of the second ADP5052 device is 0˚ (see Figure 42). SYNC-OUT AT FIRST ADP5052 1 0° REFERENCE CH1 (½ fSW OPTIONAL) 180° PHASE SHIFT SW1 AT FIRST ADP5052 SW 2 SW1 AT SECOND ADP5052 CH2 0° PHASE SHIFT CH1 2.00V BW CH3 5.00V BW CH4 Figure 42. Waveforms of Two ADP5052 Devices Operating in Synchronization Mode 10900-040 SYNCHRONIZATION INPUT/OUTPUT The switching frequency of the ADP5052 can be synchronized to an external clock with a frequency range from 250 kHz to 1.4 MHz. The ADP5052 automatically detects the presence of an external clock applied to the SYNC/MODE pin, and the switching frequency transitions smoothly to the frequency of the external clock. When the external clock signal stops, the device automatically switches back to the internal clock and continues to operate. Note that the internal switching frequency set by the RT pin must be programmed to a value that is close to the external clock value for successful synchronization; the suggested frequency difference is less than ±15% in typical applications. The SYNC/MODE pin can be configured as a synchronization clock output by factory fuse. A positive clock pulse with a 50% duty cycle is generated at the SYNC/MODE pin with a frequency equal to the internal switching frequency set by the RT pin. There is a short delay time (approximately 15% of tSW) from the generated synchronization clock to the Channel 1 switching node. 560mV To set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect a resistor divider from the SS12 or SS34 pin to the VREG pin and ground (see Figure 43). This configuration may be required to accommodate a specific start-up sequence or an application with a large output capacitor. ADP5052 VREG TOP RESISTOR SS12 OR SS34 LEVEL DETECTOR AND DECODER BOTTOM RESISTOR VREG 100kΩ 10900-039 SYNC/MODE ADP5052 A CH1 The buck regulators in the ADP5052 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. The soft start time is typically fixed at 2 ms for each buck regulator when the SS12 and SS34 pins are tied to VREG. Figure 41 shows two ADP5052 devices configured for frequency synchronization mode: one ADP5052 device is configured as the clock output to synchronize another ADP5052 device. It is recommended that a 100 kΩ pull-up resistor be used to prevent logic errors when the SYNC/MODE pin is left floating. ADP5052 M400ns SOFT START Figure 40. Phase Shift Diagram, Four Buck Regulators SYNC/MODE CH2 5.00V BW Figure 41. Two ADP5052 Devices Configured for Synchronization Mode Rev. 0 | Page 19 of 40 10900-041 180° PHASE SHIFT 10900-148 3 CH3 (½ fSW OPTIONAL) Figure 43. Level Detector Circuit for Soft Start ADP5052 Data Sheet The SS12 pin can be used to program the soft start time and parallel operation for Channel 1 and Channel 2. The SS34 pin can be used to program the soft start time for Channel 3 and Channel 4. Table 8 provides the values of the resistors needed to set the soft start time. Current balance in parallel configuration is well regulated by the internal control loop. Figure 45 shows the typical current balance matching in the parallel output configuration. 6 5 RBOT (kΩ) N/A 600 500 400 300 200 100 0 Soft Start Time Channel 1 Channel 2 2 ms 2 ms 2 ms Parallel 2 ms 8 ms 4 ms 2 ms 4 ms 4 ms 8 ms 2 ms 8 ms Parallel 8 ms 8 ms Soft Start Time Channel 3 Channel 4 2 ms 2 ms 2 ms 4 ms 2 ms 8 ms 4 ms 2 ms 4 ms 4 ms 4 ms 8 ms 8 ms 2 ms 8 ms 8 ms Use the SS12 pin to select parallel operation as specified in Table 8. Leave the COMP2 pin open. Use the FB1 pin to set the output voltage. Connect the FB2 pin to ground (FB2 is ignored). Connect the EN2 pin to ground (EN2 is ignored). VIN VREG SS12 SW1 CHANNEL 1 BUCK REGULATOR (4A) 0 0 EN1 CHANNEL 2 BUCK REGULATOR (4A) L1 FB1 SW2 L2 FB2 10900-042 EN2 Figure 44. Parallel Operation for Channel 1 and Channel 2 When Channel 1 and Channel 2 are operated in the parallel configuration, configure the channels as follows: • • 2 4 6 8 10 Set the input voltages and current-limit settings for Channel 1 and Channel 2 to the same values. Operate both channels in forced PWM mode. Figure 45. Current Balance in Parallel Output Configuration, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode STARTUP WITH PRECHARGED OUTPUT The buck regulators in the ADP5052 include a precharged start-up feature to protect the low-side FETs from damage during startup. If the output voltage is precharged before the regulator is turned on, the regulator prevents reverse inductor current—which discharges the output capacitor—until the internal soft start reference voltage exceeds the precharged voltage on the feedback (FBx) pin. The buck regulators in the ADP5052 include peak current-limit protection circuitry to limit the amount of positive current flowing through the high-side MOSFET. The peak current limit on the power switch limits the amount of current that can flow from the input to the output. The programmable current-limit threshold feature allows for the use of small size inductors for low current applications. VOUT (UP TO 8A) COMP1 COMP2 CH1 CH2 IDEAL CURRENT-LIMIT PROTECTION PVIN1 PVIN2 2 TOTAL OUTPUT LOAD (A) The ADP5052 supports two-phase parallel operation of Channel 1 and Channel 2 to provide a single output with up to 8 A of current. To configure Channel 1 and Channel 2 as a two-phase single output in parallel operation, do the following (see Figure 44): • • • • 3 1 PARALLEL OPERATION • 4 10900-151 RTOP (kΩ) 0 100 200 300 400 500 600 N/A CHANNEL CURRENT (A) Table 8. Soft Start Time Set by the SS12 and SS34 Pins To configure the current-limit threshold for Channel 1, connect a resistor from the DL1 pin to ground; to configure the currentlimit threshold for Channel 2, connect another resistor from the DL2 pin to ground. Table 9 lists the peak current-limit threshold settings for Channel 1 and Channel 2. Table 9. Peak Current-Limit Threshold Settings for Channel 1 and Channel 2 RILIM1 or RILIM2 Floating 47 kΩ 22 kΩ Typical Peak Current-Limit Threshold 4.4 A 2.63 A 6.44 A The buck regulators in the ADP5052 include negative currentlimit protection circuitry to limit certain amounts of negative current flowing through the low-side MOSFET. Rev. 0 | Page 20 of 40 Data Sheet ADP5052 FREQUENCY FOLDBACK LATCH-OFF PROTECTION The buck regulators in the ADP5052 include frequency foldback to prevent output current runaway when a hard short occurs on the output. Frequency foldback is implemented as follows: The buck regulators in the ADP5052 have an optional latch-off mode to protect the device from serious problems such as shortcircuit and overvoltage conditions. Latch-off mode can be enabled by factory fuse. • Short-Circuit Latch-Off Mode The reduced switching frequency allows more time for the inductor current to decrease but also increases the ripple current during peak current regulation. This results in a reduction in average current and prevents output current runaway. Pulse Skip Mode Under Maximum Duty Cycle Under maximum duty cycle conditions, frequency foldback maintains the output in regulation. If the maximum duty cycle is reached—for example, when the input voltage decreases—the PWM modulator skips every other PWM pulse, resulting in a switching frequency foldback of one-half. If the duty cycle increases further, the PWM modulator skips two of every three PWM pulses, resulting in a switching frequency foldback to one-third of the switching frequency. Frequency foldback increases the effective maximum duty cycle, thereby decreasing the dropout voltage between the input and output voltages. Short-circuit latch-off mode is enabled by factory fuse (on or off for all four buck regulators). When short-circuit latch-off mode is enabled and the protection circuit detects an overcurrent status after a soft start, the buck regulator enters hiccup mode and attempts to restart. If seven continuous restart attempts are made and the regulator remains in the fault condition, the regulator is shut down. This shutdown (latch-off) condition is cleared only by reenabling the channel or by resetting the channel power supply. Note that short-circuit latch-off mode does not work if hiccup protection is disabled. Figure 46 shows the short-circuit latch-off detection function. OUTPUT VOLTAGE SHORT CIRCUIT DETECTED BY COUNTER OVERFLOW ATTEMPT TO RESTART SCP LATCH-OFF FUNCTION ENABLED AFTER 7 RESTART ATTEMPTS TIME 7 × tSS HICCUP PROTECTION The buck regulators in the ADP5052 include a hiccup mode for overcurrent protection (OCP). When the peak inductor current reaches the current-limit threshold, the high-side MOSFET turns off and the low-side MOSFET turns on until the next cycle. When hiccup mode is active, the overcurrent fault counter is incremented. If the overcurrent fault counter reaches 15 and overflows (indicating a short-circuit condition), both the highside and low-side MOSFETs are turned off. The buck regulator remains in hiccup mode for a period equal to seven soft start cycles and then attempts to restart from soft start. If the shortcircuit fault has cleared, the regulator resumes normal operation; otherwise, it reenters hiccup mode after the soft start. Hiccup protection is masked during the initial soft start cycle to enable startup of the buck regulator under heavy load conditions. Note that careful design and proper component selection are required to ensure that the buck regulator recovers from hiccup mode under heavy loads. Hiccup protection can be enabled or disabled for all four buck regulators by factory fuse. When hiccup protection is disabled, the frequency foldback feature is still available for overcurrent protection. LATCH OFF THIS REGULATOR LATCH-OFF 10900-045 PWRGD Figure 46. Short-Circuit Latch-Off Detection Overvoltage Latch-Off Mode Overvoltage latch-off mode is enabled by factory fuse (on or off for all four buck regulators). The overvoltage latch-off threshold is 124% of the nominal output voltage level. When the output voltage exceeds this threshold, the protection circuit detects the overvoltage status and the regulator shuts down. This shutdown (latch-off) condition is cleared only by reenabling the channel or by resetting the channel power supply. Figure 47 shows the overvoltage latch-off detection function. OUTPUT VOLTAGE 124% NOMINAL OUTPUT 100% NOMINAL OUTPUT TIME LATCH-OFF CHx ON LATCH OFF THIS REGULATOR Figure 47. Overvoltage Latch-Off Detection Rev. 0 | Page 21 of 40 10900-046 • If the voltage at the FBx pin falls below half the target output voltage, the switching frequency is reduced by half. If the voltage at the FBx pin falls again to below one-fourth the target output voltage, the switching frequency is reduced to half its current value, that is, to one-fourth of fSW. ADP5052 Data Sheet UNDERVOLTAGE LOCKOUT (UVLO) THERMAL SHUTDOWN Undervoltage lockout circuitry monitors the input voltage level of each buck regulator in the ADP5052. If any input voltage (PVINx pin) falls below 3.78 V (typical), the corresponding channel is turned off. After the input voltage rises above 4.2 V (typical), the soft start period is initiated, and the corresponding channel is enabled when the ENx pin is high. If the ADP5052 junction temperature exceeds 150°C, the thermal shutdown circuit turns off the IC except for the internal linear regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 15°C hysteresis is included so that the ADP5052 does not return to operation after thermal shutdown until the on-chip temperature falls below 135°C. When the part exits thermal shutdown, a soft start is initiated for each enabled channel. POWER-GOOD FUNCTION The ADP5052 includes an open-drain power-good output (PWRGD pin) that becomes active high when the selected buck regulators are operating normally. By default, the PWRGD pin monitors the output voltage on Channel 1. Other channels can be configured to control the PWRGD pin when the ADP5052 is ordered (see Table 19). LDO REGULATOR The ADP5052 integrates a general-purpose LDO regulator with low quiescent current and low dropout voltage. The LDO regulator provides up to 200 mA of output current. The LDO regulator operates with an input voltage of 1.7 V to 5.5 V. The wide supply range makes the regulator suitable for cascading configurations where the LDO supply voltage is provided from one of the buck regulators. The LDO output voltage is set using an external resistor divider (see Figure 48). A logic high on the PWRGD pin indicates that the regulated output voltage of the buck regulator is above 90.5% (typical) of its nominal output. When the regulated output voltage of the buck regulator falls below 87.2% (typical) of its nominal output for a delay time greater than approximately 50 µs, the PWRGD pin goes low. The output of the PWRGD pin is the logical AND of the internal PWRGx signals. An internal PWRGx signal must be high for a validation time of 1 ms before the PWRGD pin goes high; if one PWRGx signal fails, the PWRGD pin goes low with no delay. The channels that control the PWRGD pin (Channel 1 to Channel 4) can be specified by factory fuse. The default PWRGD setting is to monitor the output of Channel 1. 1.7V TO 5.5V PVIN5 C1 1µF VOUT5 RA LDO C2 1µF FB5 RB EN5 10900-049 Note that a UVLO condition on Channel 1 (PVIN1 pin) has a higher priority than a UVLO condition on other channels, which means that the PVIN1 supply must be available before other channels can be operated. Figure 48. 200 mA LDO Regulator The LDO regulator provides a high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response using small 1 µF ceramic input and output capacitors. Rev. 0 | Page 22 of 40 Data Sheet ADP5052 APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL The ADP5052 is supported by the ADIsimPower™ design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic and bill of materials and to calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and part count while taking into consideration the operating conditions and limitations of the IC and all real external components. The ADIsimPower tool can be found at www.analog.com/ADIsimPower; the user can request an unpopulated board through the tool. PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE The output voltage of the ADP5052 is externally set by a resistive voltage divider from the output voltage to the FBx pin. To limit the degradation of the output voltage accuracy due to feedback bias current, ensure that the bottom resistor in the divider is not too large—a value of less than 50 kΩ is recommended. The equation for the output voltage setting is VOUT = VREF × (1 + (RTOP/RBOT)) The minimum output voltage in continuous conduction mode (CCM) for a given input voltage and switching frequency can be calculated using the following equation: VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) × IOUT_MIN × tMIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN (1) where: VOUT_MIN is the minimum output voltage. tMIN_ON is the minimum on time. fSW is the switching frequency. RDSON1 is the on resistance of the high-side MOSFET. RDSON2 is the on resistance of the low-side MOSFET. IOUT_MIN is the minimum output current. RL is the resistance of the output inductor. The maximum output voltage for a given input voltage and switching frequency is limited by the minimum off time and the maximum duty cycle. Note that the frequency foldback feature helps to increase the effective maximum duty cycle by lowering the switching frequency, thereby decreasing the dropout voltage between the input and output voltages (see the Frequency Foldback section). The maximum output voltage for a given input voltage and switching frequency can be calculated using the following equation: where: VOUT is the output voltage. VREF is the feedback reference voltage: 0.8 V for Channel 1 to Channel 4 and 0.5 V for Channel 5. RTOP is the feedback resistor from VOUT to FB. RBOT is the feedback resistor from FB to ground. VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON1 − RDSON2) × IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON2 + RL) × IOUT_MAX (2) No resistor divider is required in the fixed output options. If a different fixed output voltage is required, contact your local Analog Devices sales or distribution representative. VOLTAGE CONVERSION LIMITATIONS For a given input voltage, upper and lower limitations on the output voltage exist due to the minimum on time and the minimum off time. The minimum output voltage for a given input voltage and switching frequency is limited by the minimum on time. The minimum on time for Channel 1 and Channel 2 is 117 ns (typical); the minimum on time for Channel 3 and Channel 4 is 90 ns (typical). The minimum on time increases at higher junction temperatures. Note that in forced PWM mode, Channel 1 and Channel 2 can potentially exceed the nominal output voltage when the minimum on time limit is exceeded. Careful switching frequency selection is required to avoid this problem. where: VOUT_MAX is the maximum output voltage. tMIN_OFF is the minimum off time. fSW is the switching frequency. RDSON1 is the on resistance of the high-side MOSFET. RDSON2 is the on resistance of the low-side MOSFET. IOUT_MAX is the maximum output current. RL is the resistance of the output inductor. As shown in Equation 1 and Equation 2, reducing the switching frequency eases the minimum on time and off time limitations. CURRENT-LIMIT SETTING The ADP5052 has three selectable current-limit thresholds for Channel 1 and Channel 2. Make sure that the selected currentlimit value is larger than the peak current of the inductor, IPEAK. See Table 9 for the current-limit configuration for Channel 1 and Channel 2. Rev. 0 | Page 23 of 40 ADP5052 Data Sheet SOFT START SETTING Table 10. Recommended Inductors The buck regulators in the ADP5052 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. To set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect a resistor divider from the SS12 or SS34 pin to the VREG pin and ground (see the Soft Start section). Vendor Coilcraft INDUCTOR SELECTION The inductor value is determined by the switching frequency, input voltage, output voltage, and inductor ripple current. Using a small inductor value yields faster transient response but degrades efficiency due to the larger inductor ripple current. Using a large inductor value yields a smaller ripple current and better efficiency but results in slower transient response. Thus, a trade-off must be made between transient response and efficiency. As a guideline, the inductor ripple current, ΔIL, is typically set to a value from 30% to 40% of the maximum load current. The inductor value can be calculated using the following equation: where: VIN is the input voltage. VOUT is the output voltage. D is the duty cycle (D = VOUT/VIN). ΔIL is the inductor ripple current. fSW is the switching frequency. The ADP5052 has internal slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is greater than 50%. The peak inductor current is calculated using the following equation: IPEAK = IOUT + (ΔIL/2) The saturation current of the inductor must be larger than the peak inductor current. For ferrite core inductors with a fast saturation characteristic, make sure that the saturation current rating of the inductor is higher than the current-limit threshold of the buck regulator to prevent the inductor from becoming saturated. ISAT (A) 5.4 3.7 2.9 2.7 3.6 2.8 23 15.9 12.2 10.5 9.2 11.2 7.1 5.5 4.6 IRMS (A) 11 8.0 5.2 5.0 3.9 2.8 18 10 8.0 11 9.0 9.1 7.0 5.3 4.2 DCR (mΩ) 10.8 21.35 34.8 52.2 67.4 84 5.62 12.7 19.92 14.4 18.9 9.4 17.3 29.6 46.6 Size (mm) 4×4 4×4 4×4 4×4 4×4 4×4 6×6 6×6 6×6 6×6 6×6 6.2 × 5.8 6.2 × 5.8 6.2 × 5.8 6.2 × 5.8 OUTPUT CAPACITOR SELECTION The output capacitance required to meet the undershoot (voltage droop) requirement can be calculated using the following equation: COUT _ UV = K UV × ∆I STEP 2 × L 2 × (VIN − VOUT ) × ∆VOUT _ UV where: KUV is a factor (typically set to 2). ΔISTEP is the load step. ΔVOUT_UV is the allowable undershoot on the output voltage. Another example of the effect of the output capacitor on the loop dynamics of the regulator is when the load is suddenly removed from the output and the energy stored in the inductor rushes into the output capacitor, causing an overshoot of the output voltage. The output capacitance required to meet the overshoot requirement can be calculated using the following equation: The rms current of the inductor can be calculated using the following equation: I RMS = I OUT + Value (µH) 1.0 2.2 3.3 4.7 6.8 10 1.0 2.2 3.3 4.7 6.8 1.0 2.2 3.3 4.7 The selected output capacitor affects both the output voltage ripple and the loop dynamics of the regulator. For example, during load step transients on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop can ramp up the inductor current, causing an undershoot of the output voltage. L = [(VIN − VOUT) × D]/(ΔIL × fSW) 2 TOKO Part No. XFL4020-102 XFL4020-222 XFL4020-332 XFL4020-472 XAL4030-682 XAL4040-103 XAL6030-102 XAL6030-222 XAL6030-332 XAL6060-472 XAL6060-682 FDV0530-1R0 FDV0530-2R2 FDV0530-3R3 FDV0530-4R7 ∆I L 2 COUT _ OV = 12 (V OUT Shielded ferrite core materials are recommended for low core loss and low EMI. Table 10 lists recommended inductors. K OV × ∆I STEP 2 × L + ∆VOUT_OV )2 − VOUT 2 where: KOV is a factor (typically set to 2). ΔISTEP is the load step. ΔVOUT_OV is the allowable overshoot on the output voltage. Rev. 0 | Page 24 of 40 Data Sheet ADP5052 The output voltage ripple is determined by the ESR of the output capacitor and its capacitance value. Use the following equations to select a capacitor that can meet the output ripple requirements: COUT _ RIPPLE = RESR = ∆I L 8 × f SW × ∆VOUT _ RIPPLE When the high-side MOSFET is turned off, the low-side MOSFET supplies the inductor current. For low duty cycle applications, the low-side MOSFET supplies the current for most of the period. To achieve higher efficiency, it is important to select a MOSFET with low on resistance. The power conduction loss for the lowside MOSFET can be calculated using the following equation: ∆VOUT _ RIPPLE PFET_LOW = IOUT2 × RDSON × (1 − D) ∆I L where: ΔIL is the inductor ripple current. fSW is the switching frequency. ΔVOUT_RIPPLE is the allowable output voltage ripple. RESR is the equivalent series resistance of the output capacitor. Select the largest output capacitance given by COUT_UV, COUT_OV, and COUT_RIPPLE to meet both load transient and output ripple requirements. The voltage rating of the selected output capacitor must be greater than the output voltage. The minimum rms current rating of the output capacitor is determined by the following equation: I COUT _ rms = ∆I L 12 where: RDSON is the on resistance of the low-side MOSFET. D is the duty cycle (D = VOUT/VIN). Table 11 lists recommended dual MOSFETs for various currentlimit settings. Ensure that the MOSFET can handle thermal dissipation due to power loss. Table 11. Recommended Dual MOSFETs Vendor IR Fairchild Vishay INPUT CAPACITOR SELECTION The input decoupling capacitor attenuates high frequency noise on the input and acts as an energy reservoir. Use a ceramic capacitor and place it close to the PVINx pin. The loop composed of the input capacitor, the high-side NFET, and the low-side NFET must be kept as small as possible. The voltage rating of the input capacitor must be greater than the maximum input voltage. Make sure that the rms current rating of the input capacitor is larger than the following equation: I CIN _ rms = I OUT × D × (1 − D ) where D is the duty cycle (D = VOUT/VIN). LOW-SIDE POWER DEVICE SELECTION Channel 1 and Channel 2 include integrated low-side MOSFET drivers, which can drive low-side N-channel MOSFETs (NFETs). The selection of the low-side N-channel MOSFET affects the performance of the buck regulator. The selected MOSFET must meet the following requirements: • • • • Drain-to-source voltage (VDS) must be higher than 1.2 × VIN. Drain current (ID) must be greater than 1.2 × ILIMIT_MAX, where ILIMIT_MAX is the selected maximum current-limit threshold. The selected MOSFET can be fully turned on at VGS = 4.5 V. Total gate charge (Qg at VGS = 4.5 V) must be less than 20 nC. Lower Qg characteristics provide higher efficiency. AOS Part No. IRFHM8363 IRLHS6276 FDMA1024 FDMB3900 FDMB3800 FDC6401 Si7228DN Si7232DN Si7904BDN Si5906DU Si5908DC SiA906EDJ AON7804 AON7826 AO6800 AON2800 VDS (V) 30 20 20 25 30 20 30 20 20 30 20 20 30 20 30 20 ID (A) 10 3.4 5.0 7.0 4.8 3.0 23 25 6 6 5.9 4.5 22 22 3.4 4.5 RDSON (mΩ) 20.4 45 54 33 51 70 25 16.4 30 40 40 46 26 26 70 47 Qg (nC) 6.7 3.1 5.2 11 4 3.3 4.1 12 9 8 5 3.5 7.5 6 4.7 4.1 Size (mm) 3×3 2×2 2×2 3×2 3×2 3×3 3×3 3×3 3×3 3×2 3×2 2×2 3×3 3×3 3×3 2×2 PROGRAMMING THE UVLO INPUT The precision enable input can be used to program the UVLO threshold of the input voltage, as shown in Figure 38. To limit the degradation of the input voltage accuracy due to the internal 1 MΩ pull-down resistor tolerance, ensure that the bottom resistor in the divider is not too large—a value of less than 50 kΩ is recommended. The precision turn-on threshold is 0.8 V. The resistive voltage divider for the programmable VIN start-up voltage is calculated as follows: VIN_STARTUP = (0.8 nA + (0.8 V/RBOT_EN)) × (RTOP_EN + RBOT_EN) where: RTOP_EN is the resistor from VIN to EN. RBOT_EN is the resistor from EN to ground. Rev. 0 | Page 25 of 40 ADP5052 Data Sheet COMPENSATION COMPONENTS DESIGN For the peak current-mode control architecture, the power stage can be simplified as a voltage controlled current source that supplies current to the output capacitor and load resistor. The simplified loop is composed of one domain pole and a zero contributed by the output capacitor ESR. The control-to-output transfer function is shown in the following equations: s 1 + 2 × π × f VOUT (s) z Gvd (s) = = AVI × R × VCOMP (s) s 1 + 2 × π × f p fz = fp = 2. RC = 1 2 × π × RESR × COUT 4. 1 2 × π × (R + R ESR ) × COUT VOUT + AVI CCP – 10900-054 CC + CCP × R ×C ×C s × 1 + C C CP × s CC + CCP RC PLOSS = PCOND + PSW + PTRAN RESR The closed-loop transfer equation is as follows: × RESR × COUT Use the following equation to estimate the power dissipation of the buck regulator: The compensation components, RC and CC, contribute a zero; RC and the optional CCP contribute an optional pole. RBOT + RTOP CCP is optional. It can be used to cancel the zero caused by the ESR of the output capacitor. Calculate CCP using the following equation: The power dissipation (PLOSS) for each buck regulator includes power switch conduction losses (PCOND), switching losses (PSW), and transition losses (PTRAN). Other sources of power dissipation exist, but these sources are generally less significant at the high output currents of the application thermal limit. COUT 1 + RC × CC × s RC Buck Regulator Power Dissipation Figure 49. Simplified Peak Current-Mode Control Small Signal Circuit −gm (R + RESR ) × COUT PD = PBUCK1 + PBUCK2 + PBUCK3 + PBUCK4 + PLDO CC RBOT Place the compensation zero at the domain pole (fP). Calculate CC using the following equation: The total power dissipation in the ADP5052 simplifies to R RC 0.8 V × g m × AVI POWER DISSIPATION RTOP VCOMP 2 × π ×VOUT × COUT × f C CCP = VOUT – gm + Determine the cross frequency (fC). Generally, fC is between fSW/12 and fSW/6. Calculate RC using the following equation: CC = The ADP5052 uses a transconductance amplifier as the error amplifier to compensate the system. Figure 49 shows the simplified peak current-mode control small signal circuit. TV (s) = 1. 3. where: AVI = 10 A/V for Channel 1 or Channel 2, and 3.33 A/V for Channel 3 or Channel 4. R is the load resistance. RESR is the equivalent series resistance of the output capacitor. COUT is the output capacitance. RBOT The following guidelines show how to select the compensation components—RC, CC, and CCP—for ceramic output capacitor applications. × Gvd(s) Power Switch Conduction Loss (PCOND) Power switch conduction losses are caused by the flow of output current through both the high-side and low-side power switches, each of which has its own internal on resistance (RDSON). Use the following equation to estimate the power switch conduction loss: PCOND = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2 where: RDSON_HS is the on resistance of the high-side MOSFET. RDSON_LS is the on resistance of the low-side MOSFET. D is the duty cycle (D = VOUT/VIN). Rev. 0 | Page 26 of 40 Data Sheet ADP5052 Switching Loss (PSW) LDO Regulator Power Dissipation Switching losses are associated with the current drawn by the driver to turn the power devices on and off at the switching frequency. Each time a power device gate is turned on or off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. Use the following equation to estimate the switching loss: The power dissipation of the LDO regulator is given by the following equation: PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW where: CGATE_HS is the gate capacitance of the high-side MOSFET. CGATE_LS is the gate capacitance of the low-side MOSFET. fSW is the switching frequency. PLDO = [(VIN − VOUT) × IOUT] + (VIN × IGND) where: VIN and VOUT are the input and output voltages of the LDO regulator. IOUT is the load current of the LDO regulator. IGND is the ground current of the LDO regulator. Power dissipation due to the ground current is small in the ADP5052 and can be ignored. JUNCTION TEMPERATURE Transition Loss (PTRAN) Transition losses occur because the high-side MOSFET cannot turn on or off instantaneously. During a switch node transition, the MOSFET provides all the inductor current. The source-todrain voltage of the MOSFET is half the input voltage, resulting in power loss. Transition losses increase with both load and input voltage and occur twice for each switching cycle. Use the following equation to estimate the transition loss: PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW where: tR is the rise time of the switch node. tF is the fall time of the switch node. Thermal Shutdown Channel 1 and Channel 2 store the value of the inductor current only during the on time of the internal high-side MOSFET. Therefore, a small amount of power (as well as a small amount of input rms current) is dissipated inside the ADP5052, which reduces thermal constraints. However, when Channel 1 and Channel 2 are operating under maximum load with high ambient temperature and high duty cycle, the input rms current can become very large and cause the junction temperature to exceed the maximum junction temperature of 125°C. If the junction temperature exceeds 150°C, the regulator enters thermal shutdown and recovers when the junction temperature falls below 135°C. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the following equation: TJ = TA + TR where: TJ is the junction temperature. TA is the ambient temperature. TR is the rise in temperature of the package due to power dissipation. The rise in temperature of the package is directly proportional to the power dissipation in the package. The proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: TR = θJA × PD where: TR is the rise in temperature of the package. θJA is the thermal resistance from the junction of the die to the ambient temperature of the package (see Table 5). PD is the power dissipation in the package. An important factor to consider is that the thermal resistance value is based on a 4-layer, 4 inch × 3 inch PCB with 2.5 oz. of copper, as specified in the JEDEC standard, whereas real-world applications may use PCBs with different dimensions and a different number of layers. It is important to maximize the amount of copper used to remove heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. Connect the exposed pad to the ground plane with several vias. Rev. 0 | Page 27 of 40 ADP5052 Data Sheet DESIGN EXAMPLE This section provides an example of the step-by-step design procedures and the external components required for Channel 1. Table 12 lists the design requirements for this example. Table 12. Example Design Requirements for Channel 1 Parameter Input Voltage Output Voltage Output Current Output Ripple Load Transient Specification VPVIN1 = 12 V ± 5% VOUT1 = 1.2 V IOUT1 = 4 A ΔVOUT1_RIPPLE = 12 mV in CCM mode ±5% at 20% to 80% load transient, 1 A/µs Although this example shows step-by-step design procedures for Channel 1, the procedures apply to all other buck regulator channels (Channel 2 to Channel 4). SETTING THE SWITCHING FREQUENCY The first step is to determine the switching frequency for the ADP5052 design. In general, higher switching frequencies produce a smaller solution size due to the lower component values required, whereas lower switching frequencies result in higher conversion efficiency due to lower switching losses. The switching frequency of the ADP5052 can be set to a value from 250 kHz to 1.4 MHz by connecting a resistor from the RT pin to ground. The selected resistor allows the user to make decisions based on the trade-off between efficiency and solution size. (For more information, see the Oscillator section.) However, the highest supported switching frequency must be assessed by checking the voltage conversion limitations enforced by the minimum on time and the minimum off time (see the Voltage Conversion Limitations section). In this design example, a switching frequency of 600 kHz is used to achieve a good combination of small solution size and high conversion efficiency. To set the switching frequency to 600 kHz, use the following equation to calculate the resistor value, RRT: RRT (kΩ) = [14,822/fSW (kHz)]1.081 Therefore, select standard resistor RRT = 31.6 kΩ. SETTING THE OUTPUT VOLTAGE Select a 10 kΩ bottom resistor (RBOT) and then calculate the top feedback resistor using the following equation: SETTING THE CURRENT LIMIT For 4 A output current operation, the typical peak current limit is 6.44 A. For this example, choose RILIM1 = 22 kΩ (see Table 9). For more information, see the Current-Limit Protection section. SELECTING THE INDUCTOR The peak-to-peak inductor ripple current, ΔIL, is set to 35% of the maximum output current. Use the following equation to estimate the value of the inductor: L = [(VIN − VOUT) × D]/(ΔIL × fSW) where: VIN = 12 V. VOUT = 1.2 V. D is the duty cycle (D = VOUT/VIN = 0.1). ΔIL = 35% × 4 A = 1.4 A. fSW = 600 kHz. The resulting value for L is 1.28 µH. The closest standard inductor value is 1.5 µH; therefore, the inductor ripple current, ΔIL, is 1.2 A. The peak inductor current is calculated using the following equation: IPEAK = IOUT + (ΔIL/2) The calculated peak current for the inductor is 4.6 A. The rms current of the inductor can be calculated using the following equation: I RMS = I OUT 2 + ∆I L 2 12 The rms current of the inductor is approximately 4.02 A. Therefore, an inductor with a minimum rms current rating of 4.02 A and a minimum saturation current rating of 4.6 A is required. However, to prevent the inductor from reaching its saturation point in current-limit conditions, it is recommended that the inductor saturation current be higher than the maximum peak current limit, typically 7.48 A, for reliable operation. Based on these requirements and recommendations, the TOKO FDV0530-1R5, with a DCR of 13.5 mΩ, is selected for this design. RBOT = RTOP × (VREF/(VOUT − VREF)) where: VREF is 0.8 V for Channel 1. VOUT is the output voltage. To set the output voltage to 1.2 V, choose the following resistor values: RTOP = 4.99 kΩ, RBOT = 10 kΩ. Rev. 0 | Page 28 of 40 Data Sheet ADP5052 COUT _ RIPPLE = ∆I L 100 120 8 × f SW × ∆VOUT _ RIPPLE 80 90 60 60 40 30 20 0 ∆VOUT _ RIPPLE ∆I L MAGNITUDE (dB) R ESR = Figure 50 shows the Bode plot for the 1.2 V output rail. The cross frequency is 62 kHz, and the phase margin is 58°. Figure 51 shows the load transient waveform. The calculated capacitance, COUT_RIPPLE, is 20.8 µF, and the calculated RESR is 10 mΩ. To meet the ±5% overshoot and undershoot requirements, use the following equations to calculate the capacitance: COUT _ UV = COUT _ OV = K UV × ∆I STEP × L 2 –30 –60 –40 –90 –60 –120 –80 2 × (VIN − VOUT ) × ∆VOUT _ UV (V 0 –20 K OV × ∆I STEP 2 × L OUT –150 CROSS FREQUENCY: 62kHz PHASE MARGIN: 58° –100 1k 10k –180 100k 1M FREQUENCY (Hz) + ∆VOUT_OV ) − VOUT 2 PHASE (Degrees) The output capacitor must meet the output voltage ripple and load transient requirements. To meet the output voltage ripple requirement, use the following equations to calculate the ESR and capacitance: Choose standard components: RC = 15 kΩ and CC = 2.7 nF. CCP is optional. 10900-161 SELECTING THE OUTPUT CAPACITOR Figure 50. Bode Plot for 1.2 V Output 2 For estimation purposes, use KOV = KUV = 2; therefore, COUT_OV = 117 µF and COUT_UV = 13.3 µF. The ESR of the output capacitor must be less than 13.3 mΩ, and the output capacitance must be greater than 117 µF. It is recommended that three ceramic capacitors be used (47 µF, X5R, 6.3 V), such as the GRM21BR60J476ME15 from Murata with an ESR of 2 mΩ. VOUT 1 IOUT SELECTING THE LOW-SIDE MOSFET A low RDSON N-channel MOSFET must be selected for high efficiency solutions. The MOSFET breakdown voltage (VDS) must be greater than 1.2 × VIN, and the drain current must be greater than 1.2 × ILIMIT_MAX. CH1 50.0mV BW It is recommended that a 20 V, dual N-channel MOSFET—such as the Si7232DN from Vishay—be used for both Channel 1 and Channel 2. The RDSON of the Si7232DN at 4.5 V driver voltage is 16.4 mΩ, and the total gate charge is 12 nC. DESIGNING THE COMPENSATION NETWORK For better load transient and stability performance, set the cross frequency, fC, to fSW/10. In this example, fSW is set to 600 kHz; therefore, fC is set to 60 kHz. For the 1.2 V output rail, the 47 µF ceramic output capacitor has a derated value of 40 µF. RC = 2 × π × 1.2 V × 3 × 40 µ F × 60 kHz CC = CCP = 0.8 V × 470 µS × 10 A/V (0.3 Ω + 0.001 Ω) × 3 × 40 µ F 14.4 k Ω 0.001 Ω × 3 × 40 µ F 14.4 k Ω = 14.4 k Ω = 2.51 nF M200µs CH4 2.00A Ω BW A CH4 2.32A 10900-162 4 Figure 51. 0.8 A to 3.2 A Load Transient for 1.2 V Output SELECTING THE SOFT START TIME The soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during soft start and limiting the inrush current. The SS12 pin can be used to program a soft start time of 2 ms, 4 ms, or 8 ms and can also be used to configure parallel operation of Channel 1 and Channel 2. For more information, see the Soft Start section and Table 8. SELECTING THE INPUT CAPACITOR For the input capacitor, select a ceramic capacitor with a minimum value of 10 µF; place the input capacitor close to the PVIN1 pin. In this example, one 10 µF, X5R, 25 V ceramic capacitor is recommended. = 8.3 pF Rev. 0 | Page 29 of 40 ADP5052 Data Sheet RECOMMENDED EXTERNAL COMPONENTS Table 13 lists the recommended external components for 4 A applications used with Channel 1 and Channel 2 of the ADP5052. Table 14 lists the recommended external components for 1.2 A applications used with Channel 3 and Channel 4. Table 13. Recommended External Components for Typical 4 A Applications, Channel 1 and Channel 2 (±1% Output Ripple, ±7.5% Tolerance at ~60% Step Transient) fSW (kHz) 300 IOUT (A) 4 600 4 1000 4 1 2 3 VIN (V) 12 (or 5) 12 (or 5) 12 (or 5) 12 (or 5) 12 (or 5) 12 12 (or 5) 12 (or 5) 12 (or 5) 12 (or 5) 12 (or 5) 12 5 5 12 (or 5) 12 (or 5) 12 (or 5) 12 VOUT (V) 1.2 1.5 1.8 2.5 3.3 5.0 1.2 1.5 1.8 2.5 3.3 5.0 1.2 1.5 1.8 2.5 3.3 5.0 L (µH) 3.3 3.3 3.3 4.7 6.8 6.8 1.5 1.5 2.2 2.2 3.3 3.3 1.0 1.0 1.0 1.5 1.5 2.2 COUT (µF) 2 × 1001 2 × 1001 3 × 472 3 × 472 3 × 472 473 2 × 472 2 × 472 2 × 472 2 × 472 2 × 472 473 2 × 472 2 × 472 472 472 472 473 RTOP (kΩ) 4.99 8.87 12.7 21.5 31.6 52.3 4.99 8.87 12.7 21.5 31.6 52.3 4.99 8.87 12.7 21.5 31.6 52.3 RBOT (kΩ) 10 10.2 10.2 10.2 10.2 10 10 10.2 10.2 10.2 10.2 10 10 10.2 10.2 10.2 10.2 10 RC (kΩ) 10 10 6.81 10 10 4.7 10 10 10 10 15 10 15 15 10 10 10 15 CC (pF) 4700 4700 4700 4700 4700 4700 2700 2700 2700 2700 2700 2700 1500 1500 1500 1500 1500 1500 Dual FET Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN Si7232DN 100 µF capacitor: Murata GRM31CR60J107ME39 (6.3 V, X5R, 1206). 47 µF capacitor: Murata GRM21BR60J476ME15 (6.3 V, X5R, 0805). 47 µF capacitor: Murata GRM31CR61A476ME15 (10 V, X5R, 1206). Table 14. Recommended External Components for Typical 1.2 A Applications, Channel 3 and Channel 4 (±1% Output Ripple, ±7.5% Tolerance at ~60% Step Transient) fSW (kHz) 300 IOUT (A) 1.2 600 1.2 1000 1.2 1 2 VIN (V) 12 (or 5) 12 (or 5) 12 (or 5) 12 (or 5) 12 (or 5) 12 12 (or 5) 12 (or 5) 12 (or 5) 12 (or 5) 12 (or 5) 12 5 12 (or 5) 12 (or 5) 12 (or 5) 12 (or 5) 12 VOUT (V) 1.2 1.5 1.8 2.5 3.3 5.0 1.2 1.5 1.8 2.5 3.3 5.0 1.2 1.5 1.8 2.5 3.3 5.0 L (µH) 10 10 15 15 22 22 4.7 6.8 6.8 10 10 10 2.2 3.3 4.7 4.7 6.8 6.8 COUT (µF) 2 × 221 2 × 221 2 × 221 2 × 221 2 × 221 222 221 221 221 221 221 222 221 221 221 221 221 222 22 µF capacitor: Murata GRM188R60J226MEA0 (6.3 V, X5R, 0603). 22 µF capacitor: Murata GRM219R61A226MEA0 (10 V, X5R, 0805). Rev. 0 | Page 30 of 40 RTOP (kΩ) 4.99 8.87 12.7 21.5 31.6 52.3 4.99 8.87 12.7 21.5 31.6 52.3 4.99 8.87 12.7 21.5 31.6 52.3 RBOT (kΩ) 10 10.2 10.2 10.2 10.2 10 10 10.2 10.2 10.2 10.2 10 10 10.2 10.2 10.2 10.2 10 RC (kΩ) 6.81 6.81 6.81 6.81 6.81 6.81 6.81 6.81 6.81 6.81 6.81 6.81 10 10 10 10 10 15 CC (pF) 4700 4700 4700 4700 4700 4700 2700 2700 2700 2700 2700 2700 1800 1800 1800 1800 1800 1800 Data Sheet ADP5052 CIRCUIT BOARD LAYOUT RECOMMENDATIONS • • • • • Place the input capacitor, inductor, MOSFET, output capacitor, and bootstrap capacitor close to the IC. Use short, thick traces to connect the input capacitors to the PVINx pins, and use dedicated power ground to connect the input and output capacitor grounds to minimize the connection length. Use several high current vias, if required, to connect PVINx, PGNDx, and SWx to other power planes. Use short, thick traces to connect the inductors to the SWx pins and the output capacitors. Ensure that the high current loop traces are as short and wide as possible. Figure 52 shows the high current path. Maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component side to improve thermal dissipation. • • • • Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Place the decoupling capacitors close to the VREG and VDD pins. Place the frequency setting resistor close to the RT pin. Place the feedback resistor divider close to the FBx pin. In addition, keep the FBx traces away from the high current traces and the switch node to avoid noise pickup. Use Size 0402 or 0603 resistors and capacitors to achieve the smallest possible footprint solution on boards where space is limited. VIN PVINx BSTx VOUT SWx ADP5052 DLx FBx ENx GND Figure 52. Typical Circuit with High Current Traces Shown in Blue 10900-163 • • 10900-055 Good circuit board layout is essential to obtain the best performance from the ADP5052 (see Figure 53). Poor layout can affect the regulation and stability of the part, as well as the electromagnetic interference (EMI) and electromagnetic compatibility (EMC) performance. Refer to the following guidelines for a good PCB layout. Figure 53. Typical PCB Layout for the ADP5052 Rev. 0 | Page 31 of 40 ADP5052 Data Sheet TYPICAL APPLICATION CIRCUITS ADP5052 VREG SYNC/MODE VREG VDD C0 1.0µF C1 1.0µF INT VREG OSCILLATOR 100mA RT 31.6kΩ FB1 PVIN1 12V BST1 C2 10µF COMP1 6.81kΩ EN1 2.7nF VREG CHANNEL 1 BUCK REGULATOR (1.2A/2.5A/4A) SW1 5V REG DL1 SS12 L1 VOUT1 2.2µH C4 47µF Q1 1.2V/2A SiA906EDJ (46mΩ) VCORE PROCESSOR PGND VDDIO PVIN2 DL2 Q2 C5 10µF COMP2 2.7nF C3 0.1µF 6.81kΩ EN2 CHANNEL 2 BUCK REGULATOR (1.2A/2.5A/4A) 5V REG L2 VOUT2 4.7µH C7 47µF SW2 BST2 C6 0.1µF 3.3V/2.5A I/O FB2 PWRGD PVIN3 C8 10µF 2.7nF VREG COMP3 6.81kΩ EN3 BST3 CHANNEL 3 BUCK REGULATOR (1.2A) SW3 C9 0.1µF L3 VOUT3 4.7µH 1.5V/1.2A C10 22µF FB3 DDR TERM. LDO DDR MEMORY PGND3 SS34 BST4 PVIN4 C11 10µF COMP4 2.7nF 6.81kΩ EN4 CHANNEL 4 BUCK REGULATOR (1.2A) SW4 C12 0.1µF L4 VOUT4 10µH 4.5V/1.2A C13 22µF FB4 RFPA PGND4 PVIN5 C14 1µF VOUT5 FB5 47kΩ 10kΩ VOUT5 2.85V/100mA RF TRANSCEIVER C15 1µF EXPOSED PAD 10900-056 EN5 CHANNEL 5 200mA LDO REGULATOR Figure 54. Typical Femtocell Application, 600 kHz Switching Frequency, Fixed Output Model Rev. 0 | Page 32 of 40 Data Sheet ADP5052 ADP5052 VREG SYNC/MODE VREG VDD C0 1.0µF C1 1.0µF INT VREG OSCILLATOR 100mA RT 31.6kΩ FB1 10kΩ PVIN1 12V 4.99kΩ BST1 C2 10µF COMP1 2.7nF 10kΩ EN1 VREG SW1 CHANNEL 1 BUCK REGULATOR (1.2A/2.5A/4A) 5V REG PGND PVIN2 DL2 VREG 6.81kΩ EN3 C4 47µF 1.2V/4A VCORE C16 47µF Si7232DN (16.4mΩ) FPGA 22kΩ AUXILIARY VOLTAGE Q2 CHANNEL 2 BUCK REGULATOR (1.2A/2.5A/4A) 5V REG L2 VOUT2 2.2µH C7 47µF SW2 BST2 C6 0.1µF FB2 2.5V/4A C17 47µF 21.5kΩ I/O BANK 0 I/O BANK 1 I/O BANK 2 10.2kΩ PVIN3 2.7nF VOUT1 22kΩ PWRGD C8 10µF COMP3 L1 1.5µH Q1 DL1 SS12 C5 10µF COMP2 2.7nF 10kΩ EN2 C3 0.1µF BST3 CHANNEL 3 BUCK REGULATOR (1.2A) SW3 C9 0.1µF L3 VOUT3 6.8µH 8.87kΩ FB3 1.5V/1.2A 10.2kΩ PGND3 I/O BANK 3 MGTs C10 22µF DDR TERM. LDO DDR MEMORY 3.3V/1.2A FLASH MEMORY SS34 BST4 PVIN4 C11 10µF COMP4 6.81kΩ EN4 SW4 FB4 PGND4 C12 0.1µF L4 VOUT4 10µH 31.6kΩ C13 22µF 10.2kΩ PVIN5 EN5 CHANNEL 5 200mA LDO REGULATOR C14 1µF VOUT5 FB5 14kΩ 10kΩ VOUT5 1.2V/100mA C15 1µF EXPOSED PAD 10900-057 2.7nF CHANNEL 4 BUCK REGULATOR (1.2A) Figure 55. Typical FPGA Application, 600 kHz Switching Frequency, Adjustable Output Model Rev. 0 | Page 33 of 40 ADP5052 Data Sheet ADP5052 VREG SYNC/MODE VREG VDD C1 1.0µF C0 1.0µF PVIN1 INT VREG OSCILLATOR 100mA RT 31.6kΩ 10kΩ FB1 12V 4.99kΩ BST1 C2 10µF COMP1 2.7nF CHANNEL 1 BUCK REGULATOR (1.2A/2.5A/4A) 10kΩ EN1 VREG 100kΩ DL1 SS12 Si7232DN (16.4mΩ) Q1 VOUT1 C4 100µF 1.2V/8A C16 100µF 22kΩ PGND 22kΩ DL2 Q2 PVIN2 COMP2 L1 1.5µH 5V REG 600kΩ C5 10µF C3 0.1µF SW1 CHANNEL 2 BUCK REGULATOR (1.2A/2.5A/4A) 5V REG L2 SW2 BST2 EN2 1.5µH C6 0.1µF FB2 PWRGD PVIN3 C8 10µF 2.7nF VREG COMP3 6.81kΩ EN3 BST3 CHANNEL 3 BUCK REGULATOR (1.2A) C9 0.1µF SW3 L3 6.8µH FB3 PGND3 10.2kΩ VOUT3 1.5V/1.2A C10 22µF 8.87kΩ SS34 BST4 C12 0.1µF PVIN4 C11 10µF 2.7nF COMP4 CHANNEL 4 BUCK REGULATOR (1.2A) 6.81kΩ EN4 SW4 L4 10µH FB4 PGND4 10.2kΩ VOUT4 C13 22µF 31.6kΩ C14 1µF PVIN5 EN5 CHANNEL 5 200mA LDO REGULATOR 3.3V/1.2A VOUT5 40.2kΩ FB5 10kΩ C15 1µF VOUT5 2.5V/200mA 10900-165 EXPOSED PAD Figure 56. Typical Channel 1/Channel 2 Parallel Output Application, 600 kHz Switching Frequency, Adjustable Output Model Rev. 0 | Page 34 of 40 Data Sheet ADP5052 FACTORY PROGRAMMABLE OPTIONS Table 15 through Table 26 list the options that can be programmed into the ADP5052 when it is ordered from Analog Devices. For a list of the default options, see Table 27. To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 15. Output Voltage Options for Channel 1 (Fixed Output Options: 0.85 V to 1.6 V in 25 mV Increments) Option Option 0 Option 1 Option 2 … Option 30 Option 31 Description 0.8 V adjustable output (default) 0.85 V fixed output 0.875 V fixed output … 1.575 V fixed output 1.6 V fixed output Table 16. Output Voltage Options for Channel 2 (Fixed Output Options: 3.3 V to 5.0 V in 300 mV/200 mV Increments) Option Option 0 Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Description 0.8 V adjustable output (default) 3.3 V fixed output 3.6 V fixed output 3.9 V fixed output 4.2 V fixed output 4.5 V fixed output 4.8 V fixed output 5.0 V fixed output Table 17. Output Voltage Options for Channel 3 (Fixed Output Options: 1.2 V to 1.8 V in 100 mV Increments) Option Option 0 Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Description 0.8 V adjustable output (default) 1.2 V fixed output 1.3 V fixed output 1.4 V fixed output 1.5 V fixed output 1.6 V fixed output 1.7 V fixed output 1.8 V fixed output Table 18. Output Voltage Options for Channel 4 (Fixed Output Options: 2.5 V to 5.5 V in 100 mV Increments) Option Option 0 Option 1 Option 2 … Option 30 Option 31 Description 0.8 V adjustable output (default) 2.5 V fixed output 2.6 V fixed output … 5.4 V fixed output 5.5 V fixed output Rev. 0 | Page 35 of 40 ADP5052 Data Sheet Table 19. PWRGD Output Options Option Option 0 Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 Option 10 Option 11 Option 12 Option 13 Option 14 Option 15 Description No monitoring of any channel Monitor Channel 1 output (default) Monitor Channel 2 output Monitor Channel 1 and Channel 2 outputs Monitor Channel 3 output Monitor Channel 1 and Channel 3 outputs Monitor Channel 2 and Channel 3 outputs Monitor Channel 1, Channel 2, and Channel 3 outputs Monitor Channel 4 output Monitor Channel 1 and Channel 4 outputs Monitor Channel 2 and Channel 4 outputs Monitor Channel 1, Channel 2, and Channel 4 outputs Monitor Channel 3 and Channel 4 outputs Monitor Channel 1, Channel 3, and Channel 4 outputs Monitor Channel 2, Channel 3, and Channel 4 outputs Monitor Channel 1, Channel 2, Channel 3, and Channel 4 outputs Table 20. Output Discharge Functionality Options Option Option 0 Option 1 Description Output discharge function disabled for all four buck regulators Output discharge function enabled for all four buck regulators (default) Table 21. Switching Frequency Options for Channel 1 Option Option 0 Option 1 Description 1 × switching frequency set by the RT pin (default) ½ × switching frequency set by the RT pin Table 22. Switching Frequency Options for Channel 3 Option Option 0 Option 1 Description 1 × switching frequency set by the RT pin (default) ½ × switching frequency set by the RT pin Table 23. Pin 43—SYNC/MODE Pin Options Option Option 0 Option 1 Description Forced PWM/automatic PWM/PSM mode setting with the ability to synchronize to an external clock Generate a clock signal equal to the master frequency set by the RT pin Table 24. Hiccup Protection Options for the Four Buck Regulators Option Option 0 Option 1 Description Hiccup protection enabled for overcurrent events (default) Hiccup protection disabled; frequency foldback protection only for overcurrent events Table 25. Short-Circuit Latch-Off Options for the Four Buck Regulators Option Option 0 Option 1 Description Latch-off function disabled for output short-circuit events (default) Latch-off function enabled for output short-circuit events Table 26. Overvoltage Latch-Off Options for the Four Buck Regulators Option Option 0 Option 1 Description Latch-off function disabled for output overvoltage events (default) Latch-off function enabled for output overvoltage events Rev. 0 | Page 36 of 40 Data Sheet ADP5052 FACTORY DEFAULT OPTIONS Table 27 lists the factory default options programmed into the ADP5052 when the device is ordered (see the Ordering Guide). To order the device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 15 through Table 26 list all available options for the device. Table 27. Factory Default Options Option Channel 1 output voltage Channel 2 output voltage Channel 3 output voltage Channel 4 output voltage PWRGD pin (Pin 20) output Output discharge function Switching frequency on Channel 1 Switching frequency on Channel 3 SYNC/MODE pin (Pin 43) function Hiccup protection Short-circuit latch-off function Overvoltage latch-off function Default Value 0.8 V adjustable output 0.8 V adjustable output 0.8 V adjustable output 0.8 V adjustable output Monitor Channel 1 output Enabled for all four buck regulators 1 × switching frequency set by the RT pin 1 × switching frequency set by the RT pin Forced PWM/automatic PWM/PSM mode setting with the ability to synchronize to an external clock Enabled for overcurrent events Disabled for output short-circuit events Disabled for output overvoltage events Rev. 0 | Page 37 of 40 ADP5052 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.20 PIN 1 INDICATOR 37 36 48 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 5.60 SQ 5.55 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE *5.65 EXPOSED PAD 24 PIN 1 INDICATOR 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-2 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION. 04-26-2013-C 7.10 7.00 SQ 6.90 Figure 57. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 7 mm × 7 mm Body, Very Very Thin Quad (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP5052ACPZ-R7 ADP5052-EVALZ 1 2 Temperature Range −40°C to +125°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Package Option 2 CP-48-13 Z = RoHS Compliant Part. Table 27 lists the factory default options for the device. For a list of factory programmable options, see the Factory Programmable Options section. To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Rev. 0 | Page 38 of 40 Data Sheet ADP5052 NOTES Rev. 0 | Page 39 of 40 ADP5052 Data Sheet NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10900-0-5/13(0) Rev. 0 | Page 40 of 40