MOTOROLA Order this document by MCM69P817/D SEMICONDUCTOR TECHNICAL DATA MCM69P817 Product Preview 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P817 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 18 bits each. This device integrates input registers, an output register, a 2–bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and linear burst order (LBO) are clock (K) controlled through positive– edge–triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69P817 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and SBb controls DQb. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge–triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM69P817 operates from a 3.3 V core power supply and all outputs operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible. ZP PACKAGE PBGA CASE 999–01 • MCM69P817 Speed Options 200 MHz 5 ns Pipelined tKHQV 2.5 ns 0.5 ns 1 ns IDD 475 mA 180 MHz 5.5 ns 3.0 ns 0.5 ns 1 ns 450 mA PBGA 166 MHz 6 ns 3.5 ns 0.5 ns 1 ns 425 mA PBGA Speed tKHKH Setup Hold Pkg PBGA • 3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply • ADSP, ADSC, and ADV Burst Control Pins • Selectable Burst Sequencing Order (Linear/Interleaved) • Single–Cycle Deselect Timing • Internally Self–Timed Write Cycle • Byte Write and Global Write Control • PB1 Version 2.0 Compatible • JEDEC Standard 119–Pin PBGA Package BurstRAM is a trademark of Motorola, Inc. The PowerPC name is a trademark of IBM Corp., used under license therefrom. This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. 6/10/97 Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM69P817 1 FUNCTIONAL BLOCK DIAGRAM LBO ADV K ADSC BURST COUNTER K2 2 18 256K x 18 ARRAY CLR ADSP 2 SA SA1 SA0 ADDRESS REGISTER 18 16 SGW SW SBa 18 18 WRITE REGISTER b 2 SBb K2 SE1 SE2 SE3 G MCM69P817 2 DATA–IN REGISTER WRITE REGISTER c ENABLE REGISTER DATA–OUT REGISTER K K ENABLE REGISTER DQa – DQb MOTOROLA FAST SRAM PIN ASSIGNMENT A B C D 1 2 3 4 5 6 7 VDDQ SA SA ADSP SA SA VDDQ NC SE2 SA ADSC SA SE3 NC NC SA SA VDD SA SA NC DQb NC VSS NC VSS DQa NC NC DQb VSS SE1 VSS NC DQa VDDQ NC VSS G VSS DQa VDDQ NC DQb SBb ADV VSS NC DQa DQb NC VSS SGW VSS DQa NC VDDQ VDD NC VDD NC VDD VDDQ E F G H J K L NC DQb VSS K VSS NC DQa DQb NC VSS NC SBa DQa NC VDDQ DQb VSS SW VSS NC VDDQ M N P R DQb NC VSS SA1 VSS DQa NC NC DQb VSS SA0 VSS NC DQa NC SA LBO VDD NC SA NC NC SA SA NC SA SA NC VDDQ NC NC NC NC NC VDDQ T U TOP VIEW 119 BUMP PBGA Not to Scale MOTOROLA FAST SRAM MCM69P817 3 PBGA PIN DESCRIPTIONS Pin Locations Symbol Type 4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address used to initiate a new READ or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 4G ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P DQx I/O 4F G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 4K K Input Clock: This signal registers the address, data in, and all control signals except G and LBO. 3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter (68K/PowerPC). High — interleaved burst counter (486/i960/Pentium). 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 5L, 3G (a) (b) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b). SGW overrides SBx. 4E SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 6B SE3 Input Synchronous Chip Enable: Active low for depth expansion. 4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 4M SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 4C, 2J, 4J, 6J, 4R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply I/O Power Supply. 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P VSS Supply Ground. 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U NC — MCM69P817 4 Description Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b). No Connection: There is no connection to the chip. MOTOROLA FAST SRAM TRUTH TABLE (See Notes 1 Through 5) Address Used SE1 SE2 SE3 ADSP Deselect None 1 X X Deselect None 0 X 1 Deselect None 0 0 Deselect None X X Next Cycle Deselect ADSC ADV G3 DQx Write 2, 4 X 0 X X High–Z X 0 X X X High–Z X X 0 X X X High–Z X 1 1 0 X X High–Z X None X 0 X 1 0 X X High–Z X Begin Read External 0 1 0 0 X X X High–Z X5 Begin Read External 0 1 0 1 0 X X High–Z READ5 Continue Read Next X X X 1 1 0 1 High–Z READ Continue Read Next X X X 1 1 0 0 DQ READ Continue Read Next 1 X X X 1 0 1 High–Z READ Continue Read Next 1 X X X 1 0 0 DQ READ Suspend Read Current X X X 1 1 1 1 High–Z READ Suspend Read Current X X X 1 1 1 0 DQ READ Suspend Read Current 1 X X X 1 1 1 High–Z READ Suspend Read Current 1 X X X 1 1 0 DQ READ Begin Write External 0 1 0 1 0 X X High–Z WRITE Next X X X 1 1 0 X High–Z WRITE Continue Write Continue Write Next 1 X X X 1 0 X High–Z WRITE Suspend Write Current X X X 1 1 1 X High–Z WRITE Suspend Write Current 1 X X X 1 1 X High–Z WRITE NOTES: 1. X = don’t care. 1 = logic high. 0 = logic low. 2. Write is defined as either (a) any SBx and SW low or (b) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. 5. This read assumes the RAM was previously deselected. LINEAR BURST ADDRESS TABLE (LBO = VSS) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10 INTERLEAVED BURST ADDRESS TABLE (LBO = VDD) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00 WRITE TRUTH TABLE SGW SW SBa SBb Read Cycle Type H H X X Read H L H H Write Byte a H L L H Write Byte b H L H L Write All Bytes H L L L Write All Bytes L X X X MOTOROLA FAST SRAM MCM69P817 5 ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Symbol Value Unit VDD VSS – 0.5 to + 4.6 V VDDQ VSS – 0.5 to VDD V Vin, Vout VSS – 0.5 to VDD + 0.5 V Input Voltage (Three–State I/O) (See Note 2) VIT VSS – 0.5 to VDDQ + 0.5 V Output Current (per I/O) Iout ± 20 mA Package Power Dissipation (See Note 3) PD 1.6 W Tbias – 10 to 85 °C Tstg – 55 to 125 °C Power Supply Voltage I/O Supply Voltage (See Note 2) Input Voltage Relative to VSS for Any Pin Except VDD (See Note 2) Temperature Under Bias Storage Temperature This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady–state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing can not be controlled and is not allowed. 3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics. PACKAGE THERMAL CHARACTERISTICS — PBGA Rating Symbol Max Unit Notes RθJA 41 19 °C/W 1, 2 Junction to Board (Bottom) RθJB 11 °C/W 3 Junction to Case (Top) RθJC 9 °C/W 4 Junction to Ambient (@ 200 lfm) Single Layer Board Four Layer Board NOTES: 1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38–87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MCM69P817 6 MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (3.6 V ≥ VDD ≥ 3.135 V, 70°C ≥ TA ≥ 0°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) Parameter Symbol Min Typ Max Unit VDD 3.135 3.3 3.6 V VDDQ 2.375 3.3 VDD V Ambient Temperature TA 0 — 70 °C Input Low Voltage VIL – 0.3 — 0.8 V Input High Voltage VIH 2.0 — VDD + 0.3 V Supply Voltage I/O Supply Voltage VIH VSS VSS – 1.0 V 20% tKHKH (MIN) Figure 1. Undershoot Voltage DC CHARACTERISTICS AND SUPPLY CURRENTS Symbol Min Typ Max Unit Notes Input Leakage Current (0 V ≤ Vin ≤ VDD) Parameter Ilkg(I) — — ±1 µA 1 Output Leakage Current (0 V ≤ Vin ≤ VDDQ) Ilkg(O) — — ±1 µA IDDA — — 475 450 425 mA 2, 3, 4 CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) ISB2 — — 40 mA 5 TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at Vin ≤ VIL or ≥ VIH) ISB3 — — 45 mA 5 Clock Running (Device Deselected, MCM69P817–2.5 Freq = Max, VDD = Max, All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) ISB4 — — 190 mA 5 Static Clock Running (Device Deselected, MCM69P817–2.5 Freq = Max, VDD = Max, All Inputs Static at Vin ≤ VIL or ≥ VIH) ISB5 — — 85 mA 5 Output Low Voltage (IOL = 2 mA) VDDQ = 2.5 V VOL1 — — 0.7 V Output High Voltage (IOH = – 2 mA) VDDQ = 2.5 V VOH1 1.7 — — V Output Low Voltage (IOL = 8 mA) VDDQ = 3.3 V VOL2 — — 0.4 V AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes VDD and VDDQ MCM69P817–2.5 MCM69P817–3 MCM69P817–3.5 Output High Voltage (IOH = – 4 mA) VDDQ = 3.3 V VOH2 2.4 — — NOTES: 1. LBO pin has an internal pullup and will exhibit leakage currents of ± 5 µA. 2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr / tf, pulse level 0 to 3.0 V). 3. All addresses transition simultaneously low (LSB) and then high (MSB). 4. Data states are all zero. 5. Device in Deselected mode as defined by the Truth Table. V CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 70°C ≥ TA ≥ 0°C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Min Typ Max Unit Input Capacitance Cin — 4 5 pF Input/Output Capacitance CI/O — 7 8 pF MOTOROLA FAST SRAM MCM69P817 7 AC OPERATING CONDITIONS AND CHARACTERISTICS (3.6 V ≥ VDD ≥ 3.135 V, 70°C ≥ TA ≥ 0°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Slew Rate (See Figure 3) . . . . . . . . . . . . . . . . . . . . . . . . 1.0 V/ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted Output Rise/Fall Times (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 ns READ/WRITE CYCLE TIMING (See Notes 1 and 2) MCM69P817–2.5 200 MHz MCM69P817–3 180 MHz MCM69P817–3.5 166 MHz Symbol S b l Min Max Min Max Min Max Unit U i Cycle Time tKHKH 5 — 5.5 — 6 — ns Clock High Pulse Width tKHKL 2.2 — 2.5 — 2.7 — ns 3, 4 Clock Low Pulse Width tKLKH 2.2 — 2.5 — 2.7 — ns 3, 4 Clock Access Time tKHQV — 2.5 — 3 — 3.5 ns 3 Parameter P Output Enable to Output Valid Notes N tGLQV — 3.5 — 3.5 — 3.8 ns 3 Clock High to Output Active tKHQX1 0 — 0 — 0 — ns 3, 5, 6 Clock High to Output Change tKHQX2 1.5 — 1.5 — 1.5 — ns 3, 6 Output Enable to Output Active tGLQX 0 — 0 — 0 — ns 3, 5, 6 Output Disable to Q High–Z tGHQZ — 3.5 — 3.5 — 3.8 ns 3, 5, 6 Clock High to Q High–Z tKHQZ 1.5 5 1.5 5.5 1.5 6 ns 3, 5, 6 Setup Times: Address Data In Write Chip Enable ADSP, ADSC, ADV tADKH tDVKH tWVKH tEVKH tADSKH 0.5 0.5 0.5 0.5 1.5 — 0.5 0.5 0.5 0.5 1.5 — 0.5 0.5 0.5 0.5 1.5 — ns 3 Hold Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHEX 1.0 — 1.0 — 1.0 — ns 3 NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. Tested per AC Test Load, Figure 2. 4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 5. Measured at ± 200 mV from steady state. 6. This parameter is sampled and not 100% tested. MCM69P817 8 MOTOROLA FAST SRAM OUTPUT Z0 = 50 Ω RL = 50 Ω 1.5 V Figure 2. AC Test Load OUTPUT LOAD OUTPUT BUFFER TEST POINT UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM OUTPUT WAVEFORM 2.4 2.4 0.4 0.4 2.4 2.4 0.4 tr NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.4 to 2.4 V unloaded. 3. Fall time is measured from 2.4 to 0.4 V unloaded. 0.4 tf Figure 3. Unloaded Rise and Fall Time Characterization MOTOROLA FAST SRAM MCM69P817 9 3.6 3.135 PULL–UP 2.8 I (mA) MIN I (mA) MAX – 0.5 – 40 – 120 0 – 40 – 120 1.4 – 40 – 120 1.65 – 37 – 104 2.0 – 28 – 81 3.135 0 – 20 3.6 0 0 VOLTAGE (V) VOLTAGE (V) 1.65 1.4 0 0 – 40 – 120 CURRENT (mA) (a) Pull–Up for 3.3 V I/O Supply 2.9 2.5 PULL–UP I (mA) MIN I (mA) MAX – 0.5 – 26 – 75 0 – 26 – 75 0.8 – 26 – 75 1.25 – 18 – 58 1.5 – 14 – 49 2.3 0 – 21 2.7 0 –7 2.9 0 0 2.3 2.1 VOLTAGE (V) VOLTAGE (V) 1.25 0.8 0 0 – 26 CURRENT (mA) – 75 (b) Pull–Up for 2.5 V I/O Supply VDD PULL–DOWN I (mA) MIN I (mA) MAX – 0.5 – 34 – 126 0 0 0 0.5 17 47 1 35 90 1.65 45 114 1.8 46 120 3.6 46 120 4 46 120 1.8 VOLTAGE (V) VOLTAGE (V) 1.65 0.3 0 0 46 CURRENT (mA) 120 (c) Pull–Down for 3.3 V and 2.5 V I/O Supply Figure 4. Typical Output Buffer Characteristics MCM69P817 10 MOTOROLA FAST SRAM MOTOROLA FAST SRAM MCM69P817 11 Q(n) B SINGLE READ tKHQX1 A Q(A) Q(B) tKHQX2 t KHQV tKHKL NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low. DESELECTED tKHQZ DQx G W E SE1 ADV ADSC ADSP SA K tKHKH Q(B+2) BURST READ Q(B+1) tGHQZ Q(B+3) BURST WRAPS AROUND tKLKH Q(B) ADSP, SA SE2, SE3 IGNORED READ/WRITE CYCLES D(C) C D(C+2) BURST WRITE D(C+1) D(C+3) tGLQX D SINGLE READ Q(D) t KHQV APPLICATION INFORMATION STOP CLOCK OPERATION In the stop clock mode of operation, the SRAM will hold all state and data values even though the clock is not running (full static operation). The SRAM design allows the clock to start with ADSP and ADSC, and stops the clock after the last write data is latched, or the last read data is driven out. When starting and stopping the clock, the AC clock timing and parametrics must be strictly maintained. For example, clock pulse width and edge rates must be guaranteed when starting and stopping the clocks. To achieve the lowest power operation for all three stop clock modes, stop read, stop write, and stop deselect: • Force the clock to a low state. • Force the control signals to an inactive state (this guarantees any potential source of noise on the clock input will not start an unplanned on activity). • Force the address inputs to a low state. STOP CLOCK WITH READ TIMING K ADSP ADDRESS A1 A2 ADV DQx Q(A1) ADSP (INITIATES BURST READ) CLOCK STOP (CONTINUE BURST READ) Q(A1+1) Q(A2) WAKE UP ADSP (INITIATES BURST READ) NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL). Best results are obtained if VIL < 0.2 V. MCM69P817 12 MOTOROLA FAST SRAM STOP CLOCK WITH WRITE TIMING K ADSC ADDRESS A1 A2 WRITE ADV DATA IN D(A1) D(A1+1) VIH OR VIL FIXED (SEE NOTE) D(A2) HIGH–Z DQx ADSC (INITIATES BURST WRITE) CLOCK STOP (CONTINUE BURST WRITE) WAKE UP ADSC (INITIATES BURST WRITE) NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control lines held in an inactive state. MOTOROLA FAST SRAM MCM69P817 13 STOP CLOCK WITH DESELECT OPERATION TIMING K ADSC SE1 DATA IN VIH OR VIL FIXED (SEE NOTE 1) HIGH–Z DQx DATA CONTINUE BURST READ DATA CLOCK STOP (DESELECTED) WAKE UP (DESELECTED) NOTES: 1. While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control lines held in an inactive state. 2. For best possible power savings, the data–in should be driven low. MCM69P817 14 MOTOROLA FAST SRAM CONTROL PIN TIE VALUES (H ≥ VIH, L ≤ VIL) NON–BURST SYNCHRONOUS OPERATION Although this BurstRAM has been designed for PowerPC– based and other high end MPU–based based systems, these SRAMs can be used in other high speed L2 cache or memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM69P817. The burst counter feature of the BurstRAM can be disabled, and the SRAM can be configured to act upon a continuous stream of addresses. See Figure 5. Non–Burst ADSP ADSC ADV SE1 LBO H L H L X Sync Non–Burst, Pipelined SRAM NOTE: Although X is specified in the table as a don’t care, the pin must be tied either high or low. K ADDR A B C D E F G H D(G) D(H) W G DQ Q(A) Q(B) Q(C) Q(D) D(E) READS D(F) WRITES Figure 5. Configured as Non–Burst Synchronous SRAM ORDERING INFORMATION (Order by Full Part Number) MCM 69P817 XX X X Motorola Memory Prefix Blank = Trays, R = Tape and Reel Part Number Speed (2.5 = 2.5 ns, 3 = 3.0 ns, 3.5 = 3.5 ns) Package (ZP = PBGA) Full Part Numbers — MCM69P817ZP2.5 MCM69P817ZP2.5R MOTOROLA FAST SRAM MCM69P817ZP3 MCM69P817ZP3R MCM69P817ZP3.5 MCM69P817ZP3.5R MCM69P817 15 PACKAGE DIMENSIONS ZP PACKAGE 7 x 17 BUMP PBGA CASE 999–01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 0.20 (0.008) 4X A –W– PIN 1A IDENTIFIER 7 6 5 4 3 2 1 B –L– P S 16X N A B C D E F G H J K L M N P R T U G 6X DIM A B C D E F G K N P R S 119X G INCHES MIN MAX 0.551 BSC 0.866 BSC ––– 0.094 0.024 0.035 0.020 0.028 0.051 0.067 0.050 BSC 0.031 0.039 0.469 0.476 0.764 0.772 0.300 BSC 0.800 BSC D R 0.30 (0.012) S T W BOTTOM VIEW 0.10 (0.004) S T TOP VIEW MILLIMETERS MIN MAX 14.00 BSC 22.00 BSC ––– 2.40 0.60 0.90 0.50 0.70 1.30 1.70 1.27 BSC 0.80 1.00 11.90 12.10 19.40 19.60 7.62 BSC 20.32 BSC S L S 0.25 (0.010) T F 0.35 (0.014) T 0.15 (0.006) T C –T– K SIDE VIEW E Motorola reserves the right to make changes without further notice to any products herein. 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