SEMICONDUCTOR TECHNICAL DATA %" #" " !$ !" !$ "" $ " The MC74LVQ646 is a high performance, non–inverting octal transceiver/registered transceiver operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. The MC74LVQ646 is suitable for memory address driving and all TTL level bus oriented transceiver applications. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes from a LOW–to–HIGH logic level. Output Enable (OE) and DIR pins are provided to control the transceiver outputs. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls (SBA, SAB) can multiplex stored and real–time (transparent mode) data. The direction control (DIR) determines which bus will receive data when the enable OE is active LOW. In the isolation mode (OE HIGH), A data may be stored in the B register or B data may be stored in the A register. Only one of the two buses, A or B, may be driven at one time. LVQ LOW–VOLTAGE CMOS OCTAL TRANSCEIVER/ REGISTERED TRANSCEIVER DW SUFFIX PLASTIC SOIC CASE 751E–04 24 1 • Designed for 2.7 to 3.6V VCC Operation – Ideal for Low Power/Low SD SUFFIX PLASTIC SSOP CASE 940D–03 24 Noise Applications • Guaranteed Simultaneous Switching Noise Level and Dynamic 1 Threshold Performance • Guaranteed Skew Specifications • Guaranteed Incident Wave Switching into 75Ω • Low Static Supply Current (10µA) Substantially Reduces System Power DT SUFFIX PLASTIC TSSOP CASE 948H–01 24 Requirements • Latchup Performance Exceeds 500mA 1 • ESD Performance: Human Body Model >2000V PIN NAMES VCC CBA SBA 24 23 22 OE B0 B1 B2 B3 B4 B5 B6 B7 21 20 19 18 17 16 15 14 13 Pinout: 24–Lead Package (Top View) 1 2 3 CAB SAB DIR 4 5 6 7 8 9 10 11 12 A0 A1 A2 A3 A4 A5 A6 A7 GND Pins Function A0–A7 B0–B7 CAB, CBA SAB, SBA DIR, OE Side A Inputs/Outputs Side B Inputs/Outputs Clock Pulse Inputs Select Control Inputs Output Enable Inputs 12/95 Motorola, Inc. 1995 1 REV 0 MC74LVQ646 1 CBA 3 DIR 21 OE LOGIC DIAGRAM 22 SBA 2 SAB 23 CAB C Q A0 D C Q B0 D 1 of 8 Channels To 7 Other Channels FUNCTION TABLE Storage Registers Inputs OE DIR H X L L CAB CBA SAB SBA QA QB Data Ports Operating Mode An Bn Input Input Operating Mode ↑ ↑ X X NC NC X X Isolation, Hold Storage ↑ ↑ X X L H X X X X L H L H X X X X L H Store A and/or B Data Input Output ↑ X* L X NC NC NC NC L H L H H X NC NC X QA ↑ X* L X L H NC NC L H L H H X L H NC NC L H QA QA Output Input X L NC NC NC NC L H L H Real Time B Data to A Bus X H NC NC QB X Stored B Data to A Bus X L NC NC L H L H L H Real Time B Data to A Bus; Store B Data X H NC NC L H QB QB L H Stored B Data to A Bus; Store B Data H L X* ↑ X* ↑ Real Time A Data to B Bus Stored A Data to B Bus Real Time A Data to B Bus; Store A Data Stored A Data to B Bus; Store A Data H = High Voltage Level; L = Low Voltage Level; X = Don’t Care; ↑ = Low–to–High Clock Transition; ↑ = NOT Low–to–High Clock Transition; NC = No Change; * = The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs. MOTOROLA 2 LVQ DATA BR1478 MC74LVQ646 BUS APPLICATIONS BUS A BUS A OE DIR CAB CBA SAB SBA OE DIR CAB CBA SAB SBA L L X X X L L H X X L X BUS A BUS A BUS B Transfer Storage Data to Bus A or Bus B BUS B Store Data from Bus A, Bus B or Busses A and B LCX DATA BR1478 BUS B Real Time Transfer – Bus A to Bus B BUS B Real Time Transfer – Bus B to Bus A OE DIR CAB CBA SAB SBA OE DIR CAB CBA SAB SBA X X H X X X ↑ X ↑ X ↑ ↑ X X X X X X L L L H X H or L H or L X X H H X 3 MOTOROLA MC74LVQ646 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter VCC DC Supply Voltage VI Value Condition Unit –0.5 to +7.0 V DC Input Voltage –0.5 ≤ VI ≤ VCC + 0.5V V VO DC Output Voltage –0.5 ≤ VO ≤ VCC + 0.5 Output in HIGH or LOW State V IIK DC Input Diode Current –20 VI = –0.5V mA +20 VI = VCC + 0.5V mA –20 VO = –0.5V mA +20 VI = VCC + 0.5V mA IOK DC Output Diode Current IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current ±400 mA IGND DC Ground Current ±400 mA TSTG Storage Temperature Range –65 to +150 °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage VI Input Voltage VO Output Voltage TA Operating Free–Air Temperature ∆V/∆t Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V, VCC = 3.0V Min Typ Max Unit 2.0 3.3 3.6 V 0 VCC V 0 VCC V –40 +85 °C 0 125 mV/ns DC ELECTRICAL CHARACTERISTICS TA = –40°C to +85°C Symbol Characteristic Condition Min 2.0 VIH HIGH Level Input Voltage (Note 1) 2.7V ≤ VCC ≤ 3.6V, VO = 0.1V or VCC – 0.1V VIL LOW Level Input Voltage (Note 1) 2.7V ≤ VCC ≤ 3.6V, VO = 0.1V or VCC – 0.1V VOH HIGH Level Output Voltage VOL LOW Level Output Voltage II Input Leakage Current IOZT Maximum I/O Leakage Current IOLD Minimum Dynamic Output Current (Note 2) IOHD ICC Quiescent Supply Current Max V 0.8 2.7V ≤ VCC ≤ 3.6V; IOH = –50µA VCC – 0.1 VCC = 2.7V; IOH = –12mA 2.2 VCC = 3.0V; IOH = –12mA 2.48 Unit V V 2.7V ≤ VCC ≤ 3.6V; IOL = 50µA 0.1 2.7V ≤ VCC ≤ 3.6V; IOL= 12mA 0.4 2.7V ≤ VCC ≤3.6V; VI= VCC, GND ±1.0 µA VI(OE) = VIL, VIH; VI, VO= VCC, GND ±3 µA VCC = 3.6V; VOLD = 0.8V Max 36 mA VCC = 3.6V; VOHD = 2.0V Min –25 mA 2.7V ≤ VCC ≤3.6V; VI = VCC, GND 10 µA V 1. These values of VI are used to test DC electrical characteristics only. Functional test should use VIH ≥ 2.4V, VIL ≤ 0.5V. 2. Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed. Maximum test duration is 2ms, one output loaded at a time. MOTOROLA 4 LVQ DATA BR1478 MC74LVQ646 DYNAMIC SWITCHING CHARACTERISTICS (VCC = 3.3V) TA = +25°C Symbol Characteristic Condition VOLP Dynamic LOW Peak Voltage (Note 1) VOLV Dynamic LOW Valley Voltage (Note 1) VIHD VILD Min Typ Max Unit CL = 50pF, VIH = 3.3V, VIL = 0V 0.6 1.0 V CL = 50pF, VIH = 3.3V, VIL = 0V –0.5 –1.0 V High Level Dynamic Input Voltage (Note 2) Input–Under–Test Switching 0V to Threshold, f=1MHz 1.5 2.0 V Low Level Dynamic Input Voltage (Note 2) Input–Under–Test Switching 3.3V to Threshold, f=1MHz 1.5 0.8 V 1. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW. The remaining output is measured in the LOW state. 2. Number of data inputs is defined as “n” switching, “n–1” inputs switching 0V to 3.3V. AC CHARACTERISTICS1 (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω) Limits TA = +25°C VCC = 3.0V to 3.6V Symbol Parameter Min Typ Max TA = –40°C to +85°C VCC = 2.7V Min Typ VCC = 3.0V to 3.6V Max Min Max VCC = 2.7V Max Unit fmax Clock Pulse Frequency 150 150 MHz tPLH tPHL Propagation Delay Clock to Output 1.5 1.5 12.5 10.0 15.0 13.0 1.5 1.5 14.0 12.0 18.0 15.0 1.5 1.5 17.0 14.5 20.0 17.0 ns tPLH tPHL Propagation Delay Input to Output 1.5 1.5 9.5 8.0 12.0 11.0 1.5 1.5 11.0 9.5 13.5 12.5 1.5 1.5 13.5 12.0 14.5 14.0 ns tPLH tPHL Propagation Delay Select to Output 1.5 1.5 9.5 8.5 12.0 11.0 1.5 1.5 11.0 10.0 13.0 12.5 1.5 1.5 13.0 12.5 14.5 14.0 ns tPZH tPZL Output Enable Time OE to An, Bn 1.5 1.5 8.0 9.0 10.5 11.0 1.5 1.5 9.5 10.0 12.0 12.5 1.5 1.5 11.0 12.0 13.0 14.0 ns tPHZ tPLZ Output Disable Time OE to An, Bn 1.5 1.5 9.0 8.5 11.0 10.5 1.5 1.5 10.5 9.5 12.5 12.5 1.5 1.5 12.0 12.0 14.0 14.0 ns tPZH tPZL Output Enable Time DIR to An, Bn 1.5 1.5 9.0 10.0 12.0 12.0 1.5 1.5 12.0 11.0 14.0 14.0 1.5 1.5 13.0 12.5 16.0 16.0 ns tPHZ tPLZ Output Disable Time DIR to An, Bn 1.5 1.5 9.0 10.0 11.0 12.5 1.5 1.5 10.0 13.0 13.0 15.5 1.5 1.5 12.0 14.0 15.0 18.0 ns tOSHL tOSLH Output–to–Output Skew (Note 2) 1.0 1.0 1.5 1.5 1.0 1.0 1.5 1.5 1.5 1.5 ns 1. These AC parameters are preliminary and may be modified prior to release. The maximum AC limits are design targets. Actual performance will be specified upon completion of characterization. 2. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter guaranteed by design. AC OPERATING REQUIREMENTS (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω) Limits TA = +25°C TA = –40°C to +85°C VCC = 3.0V to 3.6V VCC = 2.7V VCC = 3.0V to 3.6V VCC = 2.7V Parameter Min Min Min Min Unit ts Setup TIme, HIGH or LOW Dn to LE 2.5 4.0 2.5 4.5 ns th Hold TIme, HIGH or LOW Dn to LE 1.5 1.5 1.5 1.5 ns tw LE Pulse Width, HIGH 3.3 5.0 3.3 6.0 ns Symbol LCX DATA BR1478 5 MOTOROLA MC74LVQ646 CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Unit 10MHz, VCC = 3.3V, VI = 0V or VCC 50 pF CPD Power Dissipation Capacitance CIN Input Capacitance VCC = Open, VI = 0V or VCC 4.5 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 15 pF VCC An, Bn, SBA, SAB 50% VCC 0V tPLH, tPHL VOH Bn, An 50% VCC VOL WAVEFORM 1 – SAB to B and SBA to A, An to Bn PROPAGATION DELAYS tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns VCC OE 50% VCC 50% VCC 0V DIR tPZH tPHZ VOH – 0.3V 50% VCC An, Bn ≈ 0V tPZL An, Bn tPLZ ≈ 3.0V 50% VCC VOL + 0.3V WAVEFORM 2 – OE/DIR to An/Bn OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns Figure 1. AC Waveforms MOTOROLA 6 LVQ DATA BR1478 MC74LVQ646 VCC An, Bn 50% VCC 0V ts th VCC CAB, 50% V CC CBA tw 50% VCC 0V fmax tPLH, tPHL VOH Bn, An 50% VCC VOL WAVEFORM 3 – CLOCK to Bn/An PROPAGATION DELAYS, CLOCK MINIMUM PULSE WIDTH, An/Bn to CLOCK SETUP AND HOLD TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted tw NEGATIVE PULSE 50% VCC 50% VCC POSITIVE PULSE 50% VCC 50% VCC tw WAVEFORM 4 – INPUT PULSE DEFINITION tR = tF = 2.5ns, 10% to 90% of 0V to VCC Figure 2. AC Waveforms VCC PULSE GENERATOR R1 DUT CL RT TEST 6V OPEN GND RL SWITCH tPLH, tPHL Open tPZL, tPLZ 6V Open Collector/Drain tPLH and tPHL tPZH, tPHZ 6V GND CL = 50pF or equivalent (Includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) Figure 3. Test Circuit LCX DATA BR1478 7 MOTOROLA MC74LVQ646 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E–04 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A – 24 13 –B – 1 P 12 PL 0.010 (0.25) M B M 12 J D 24 PL 0.010 (0.25) T A M B S DIM A B C D F G J K M P R S F R X 45° C –T – SEATING PLANE M K G 22 PL MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0° 8° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0° 8° 0.395 0.415 0.010 0.029 SD SUFFIX PLASTIC SSOP PACKAGE CASE 940D–03 ISSUE B 24X K REF 0.12 (0.005) M T U S V ÇÇÇÇ ÇÇÇÇ ÉÉÉ ÇÇÇÇ ÉÉÉ ÇÇÇÇ ÉÉÉ ÇÇÇÇ S K L/2 24 J 13 K1 B L J1 SECTION N–N PIN 1 IDENT 1 12 0.20 (0.008) M T U 0.25 (0.010) –U– A –V– N M S NOTES: 4 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 CONTROLLING DIMENSION: MILLIMETER. 6 DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 7 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 8 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 9 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 10 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. N F DETAIL E 0.076 (0.003) –T– SEATING PLANE –W– C D G H MOTOROLA DETAIL E 8 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 8.07 8.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.44 0.60 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.317 0.328 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.017 0.024 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_ LVQ DATA BR1478 MC74LVQ646 OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948H–01 ISSUE O 24X K REF 0.10 (0.004) 0.15 (0.006) T U T U M V S S S 2X 24 L/2 13 B –U– L PIN 1 IDENT. 12 1 0.15 (0.006) T U NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. S A –V– DIM A B C D F G H J J1 K K1 L M C 0.10 (0.004) –T– SEATING PLANE G D H –W– MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ DETAIL E ÉÉ ÇÇÇ ÇÇÇ ÉÉ ÇÇÇ ÉÉ ÇÇÇ ÉÉ N 0.25 (0.010) K K1 J1 M N F SECTION N–N DETAIL E J LCX DATA BR1478 9 MOTOROLA MC74LVQ646 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MOTOROLA 10 *MC74LVQ646/D* MC74LVQ646/D LVQ DATA BR1478