INTERSIL ICM7224IPL

ICM7224
®
NO R
DUCT
ENT
E PR O
T
E
L
O
L ACEM
P
E
OBS
R
ED
MEND
EC O M
4 1/2 Digit LCD Display Counter
May 2001
Features
Description
• High Frequency Counting - Guaranteed 15MHz, Typically
25MHz at 5V
The ICM7224 device is a high-performance, CMOS 41/2
digit counter, including decoder, output latch, display driver,
count inhibit, leading zero blanking, and reset circuitry.
• Low Power Operation - Typically Less Than 100µW
Quiescent
The counter section provides direct static counting, guaranteed from DC to 15MHz, using a 5V ±10% supply over the
operating temperature range. At normal ambient temperatures, the devices will typically count up to 25MHz. The
COUNT input is provided with a Schmitt trigger to allow
operation in noisy environments and correct counting with
slowly changing inputs. The COUNT INHIBIT, STORE and
RESET inputs allow a direct interface with the ICM7207 and
ICM7207A to implement a low cost, low power frequency
counter with a minimum component count.
• STORE and RESET Inputs Permit Operation as
Frequency or Period Counter
• True COUNT INHIBIT Disables First Counter Stage
• CARRY Output for Cascading Four-Digit Blocks
• Schmitt-Trigger on the COUNT Input Allows Operation
in Noisy Environments or with Slowly Changing Inputs
• Leading Zero Blanking INput and OUTput for Correct
Leading Zero Blanking with Cascaded Devices
These devices also incorporate several features intended to
simplify cascading four-digit blocks. The CARRY output
allows the counter to be cascaded, while the Leading Zero
Blanking INput and OUTput allows correct Leading Zero
Blanking between four-decade blocks. The BackPlane driver
of the LCD devices may be disabled, allowing the segments
to be slaved to another backplane signal, necessary when
using an eight or twelve digit, single backplane display.
• Provides Complete Onboard Oscillator and Divider
Chain to Generate Backplane Frequency, or
Backplane Driver May be Disabled Allowing Segments
to be Slaved to a Master Backplane Signal
Pinout
These devices provide maximum count of 19999. The
display drivers are not of the multiplexed type and each display segment has its own individual drive pin, providing high
quality display outputs.
ICM7224
(PDIP)
TOP VIEW
VDD
1
40 D1
E1
2
39 C1
G1
3
38 B1
F1
4
37 A1
BP
5
36 OSCILLATOR
A2
6
35 VSS
B2
7
34 STORE
C2
8
33 RESET
D2
9
32 COUNT
E2
10
31 COUNT INHIBIT
G2
11
30 LZB OUT
F2
12
29 LZB IN
A3
13
28 CARRY
B3
14
27 1/2 - DIGIT
C3
15
26 F4
D3
16
25 G4
E3
17
24 E4
G3
18
23 D4
F3
19
22 C4
A4
20
21 B4
Part Number Information
PART NUMBER
ICM7224IPL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
TEMP.
RANGE ( oC)
-25 to 85
PKG.
NO.
PACKAGE
40 Ld PDIP
E40.6
File Number
3168.2
ICM7224
Functional Block Diagram
STORE
LSD
DIGIT 1
SEGMENT OUTPUTS
DIGIT 2
SEGMENT OUTPUTS
DIGIT 3
SEGMENT OUTPUTS
DIGIT 4
SEGMENT OUTPUTS
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE LATCH
7 WIDE LATCH
7 WIDE LATCH
7 WIDE LATCH
DECODER
DECODER
DECODER
DECODER
LEADING
ZERO
BLANKING
OUTPUT
COUNT
INHIBIT
COUNT
INPUT
OUTPUT
1/ DIGIT
2
DRIVER
1/ DIGIT
2
LATCH
VDD
Q
SCHMITT
TRIGGER
MSD
1/ DIGIT
2
÷2
CL
Q
÷2
÷5
CL
R
Q
CL
R
R
CL
Q
÷5
Q
R
÷2
CL
R
CL
÷5
Q
R
Q
÷2
CL
R
CL
÷5
Q
R
LEADING
ZERO
BLANKING
INPUT
D
1/
2
DIGIT
CL
R
Q
RESET
OSCILLATOR
INPUT
OSCILLATOR
+124
BLACKPLANE
DRIVER
ENABLE
ENABLE
DETECTOR
2
CARRY
OUTPUT
BP INPUT/OUTPUT
ICM7224
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V DD - VSS ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Input Voltage (Any Terminal) (Note 1) . . . (VDD + 0.3V) to (VSS - 0.3V)
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may
cause destructive device latchup. For this reason, it is recommended that no inputs from sources operating on a different power supply
be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7224 be turned on first.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
VDD = 5V, VSS = 0V, TA = 25oC, Unless Otherwise Indicated
Electrical Specifications
PARAMETER
TEST CONDITIONS
Operating Current, IDD
MIN
TYP
MAX
UNIT
-
10
50
µA
3
-
6
V
Test Circuit, Display Blank
Operating Supply Voltage Range
(VDD - VSS), VSUPPLY
OSClLLATOR Input Current, IOSCI
Pin 36
-
±2
±10
µA
Segment Rise/Fall Time, tr , tf
CLOAD = 200pF
-
0.5
-
µs
BackPlane Rise/Fall Time, tr , tf
CLOAD = 5000pF
-
1.5
-
µs
Oscillator Frequency, fOSC
Pin 36 Floating
-
19
-
kHz
Backplane Frequency, fBP
Pin 36 Floating
-
150
-
Hz
Input Pullup Currents, IP
Pins 29, 31, 33, 34, VIN = VDD - 3V
-
10
-
µA
Input High Voltage, VIH
Pins 29, 31, 33, 34
3
-
-
V
Input Low Voltage, VIL
Pins 29, 31, 33, 34
-
-
1
V
COUNT Input Threshold, V CT
-
2
-
V
COUNT Input Hysteresis, VCH
-
0.5
-
V
Output High Current, IOH
CARRY Pin 28
Leading Zero Blanking OUT Pin 30
VOUT = VDD - 3V
-350
-500
-
µA
Output Low Current, IOL
CARRY Pin 28
Leading Zero Blanking OUT Pin 30
VOUT = +3V
350
500
-
µA
Count Frequency, fCOUNT
4.5V < VDD < 6V
0
-
15
MHz
3
-
-
µs
STORE, RESET Minimum Pulse Width, tS , tr
Timing Waveforms
OSCILLATOR
FREQUENCY
128 CYCLES
BACKPLANE
INPUT/OUTPUT
OFF SEGMENTS
64 CYCLES
64 CYCLES
ON SEGMENTS
FIGURE 1. ICM7224 DISPLAY WAVEFORMS
3
ICM7224
Typical Performance Curves
30
25
LCD DEVICES
TA = 25oC
VSUPPLY = 5V
TA = -20oC
15
TA = 25oC
10
1
2
3
4
5
SUPPLY VOLTAGE (V)
6
1
7
1
10
100
1000
COSC (pF)
FIGURE 3. BACKPLANE FREQUENCY AS A FUNCTION OF
OSCILLATOR CAPACITOR COSC
45
10
V+ = 5V
TA = 25 oC
SINE WAVE INPUT
SWINGING FULL SUPPLY
SUPPLY CURRENT (mA)
ƒMAX (MHz)
VSUPPLY = 4V
10
VSUPPLY = 3V
FIGURE 2. OPERATING SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
40
VSUPPLY = 6V
TA = 70oC
5
0
100
128
20
ƒBP = ƒOSC HZ
SUPPLY CURRENT (µA)
1000
LCD DEVICES, TEST CIRCUIT
DISPLAY BLANK
PIN 36 OPEN
TA = -20 oC
35
30
TA = 25oC
25
TA = 70oC
1
0.1
20
15
4
5
SUPPLY VOLTAGE (V)
0.01
1kHz
6
FIGURE 4. MAXIMUM COUNT FREQUENCY (TYPICAL) AS A
FUNCTION OF SUPPLY VOLTAGE
10kHz
100kHz
1MHz
ƒCOUNT
10MHz
FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF COUNT
FREQUENCY
TABLE 1. CONTROL INPUT DEFINITIONS
TERMINAL
29
31
33
34
INPUT
VOLTAGE
FUNCTION
Leading Zero Blanking
VDD or Floating
Leading Zero Blanking Enabled
INput
VSS
Leading Zeroes Displayed
COUNT INHIBIT
VDD or Floating
Counter Enabled
VSS
Counter Disabled
VDD or Floating
Inactive
VSS
Counter Reset to 0000
VDD or Floating
Output Latches not Updated
VSS
Output Latches Updated
RESET
STORE
100MHz
4
ICM7224
Control Input Definitions
disabled during the negative portion of the overdriving signal
(which could cause a DC component to the display). This
can be done by driving the OSCILLATOR input between the
positive supply and a level out of the range where the backplane disable is sensed, about one fifth of the supply voltage
above the negative supply. Another technique for overdriving the oscillator (with a signal swinging the full supply) is to
skew the duty cycle of the overdriving signal such that the
negative portion has a duration shorter than about one
microsecond. The backplane disable sensing circuit will not
respond to signals of this duration.
In Table 1, VDD and VSS are considered to be normal operating input logic levels. Actual input low and high levels are
specified in the Operating Characteristics. For lowest power
consumption, input signals should swing over the full supply.
Detailed Description
The ICM7224 provides outputs suitable for driving conventional 41/2 digit by seven segment LCD displays. It includes
29 individual segment drivers, a backplane driver, and a selfcontained oscillator and divider chain to generate the backplane frequency (See Functional Block Diagram).
Counter Section
The lCM7224 implements a four-digit ripple carry resettable
counter, including a Schmitt trigger on the COUNT input and
a CARRY output. Also included is an extra D-type flip-flop,
clocked by the CARRY signal which controls the half-digit
segment driver. This output driver can be used as either a
true half-digit or as an overflow indicator. The counter will
increment on the negative-going edge of the signal at the
COUNT input, while the CARRY output provides a negativegoing edge following the count which increments the counter
from 9999 to 10000. Once the half-digit flip-flop has been
clocked, it can only be reset (with the rest of the counter) by
a negative level at the RESET terminal, pin 33. However, the
four decades will continue to count in a normal fashion after
the half-digit is set, and subsequent CARRY outputs will not
be affected.
The segment and backplane drivers each consist of a
CMOS inverter, with the N-Channel and P-Channel devices
ratioed to provide identical on resistances, and thus equal
rise and fall times. This eliminates any DC component which
could arise from differing rise and fall times, and ensures
maximum display life.
The backplane output can be disabled by connecting the
OSCILLATOR input (pin 36) to VSS . This synchronizes the
29 segment outputs directly with a signal input at the BP terminal (pin 5) and allows cascading of several slave devices
to the backplane output of one master device. The backplane may also be derived from an external source. This
allows the use of displays with characters in multiples of four
and a single backplane. A slave device will represent a load
of approximately 200pF (comparable to one additional segment). The limitation on the number of devices that can be
slaved to one master device backplane driver is the additional load represented by the larger backplane of displays
of more than four digits, and the effect of that load on the
backplane rise and fall times. A good rule of thumb to
observe in order to minimize power consumption, is to keep
the rise and fall times less than about 5 microseconds. The
backplane driver of one device should handle the back-plane
to a display of 16 one-half-inch characters without the rise
and fall times exceeding 5µs (i.e., 3 slave devices and the
display backplane driven by a fourth master device). It is recommended that if more than four devices are to be slaved
together, that the backplane signal be derived externally and
all the lCM7224 devices be slaved to it.
A negative level at the COUNT INHIBIT input disables the
first divide-by-two in the counter chain without affecting its
clock. This provides a true inhibit, not sensitive to the state of
the COUNT input, which prevents false counts that can
result from using a normal logic gate to prevent counting.
Each decade of the counter directly drives a four-to-seven
segment decoder which develops the required output data.
The output data is latched at the driver. When the STORE
pin is low, these latches are updated, and when it is high or
floating, the latches hold their contents.
The decoders also include zero detect and blanking logic to
provide leading zero blanking. When the Leading Zero
Blanking INput is floating or at a positive level, this circuitry is
enabled and the device will blank leading zeroes. When it is
low, or the half-digit is set, leading zero blanking is inhibited,
and zeroes in the four digits will be displayed. The Leading
Zero Blanking OUTput is provided to allow cascaded
devices to blank leading zeroes correctly. This output will
assume a positive level only when all four digits are blanked;
this can only occur when the Leading Zero Blanking INput is
at a positive level and the half-digit is not set.
This external backplane signal should be capable of driving
very large capacitive loads with short (1-2µs) rise and fall
times. The maximum frequency for a backplane signal
should be about 150Hz, although this may be too fast for
optimum display response at lower display temperatures,
depending on the display used.
The onboard oscillator is designed to free run at approximately
19kHz, at microampere power levels. The oscillator frequency
is divided by 126 to provide the backplane frequency, which
will be approximately 150Hz with the oscillator free-running.
The oscillator frequency may be reduced by connecting an
external capacitor between the OSCillator terminal (pin 36)
and VDD; see the plot of oscillator/back-plane frequency in
“Typical Performance Curves” for detailed information.
For example, in an eight-decade counter with overflow using
two lCM7224 devices, the Leading Zero Blanking OUTput of
the high order digit would be connected to the Leading Zero
Blanking INput of the low order digit device. This will assure
correct leading zero blanking for all eight digits.
The STORE, RESET, COUNT INHIBIT, and Leading Zero
Blanking INputs are provided with pullup devices, so that
they may be left open when a positive level is desired. The
CARRY and Leading Zero Blanking OUTputs are suitable for
The oscillator may also be overdriven if desired, although
care must be taken to insure that the backplane driver is not
5
ICM7224
interfacing to CMOS logic in general, and are specifically
designed to allow cascading of the devices in four-digit
blocks.
Applications
Figure 8 shows an 8-digit precision frequency counter. The
circuit uses two ICM7224s cascaded to provide an 8-digit
display. Backplane output of the second device is disabled
and is driven by the first device. The 1/2 digit output of the
second device is used for overflow indication. The input signal is fed to the first device and the COUNT input of the second is driven by the CARRY output of the first. Notice that
leading zero blanking is controlled on the second device and
the LZB OUT of the second one is tied to LZB IN of the first
one. An ICM7207A device is used as a timebase generator
and frequency counter controller. It generates count window,
store and reset signals which are directly compatible with
ICM7224 inputs (notice the need for an inverter at COUNT
INHIBIT input). The ICM7207A provides two count window
signals (1s and 0.1s gating) for displaying frequencies in Hz
or tens of Hz (x10Hz).
+
200pF
5V
200pF
c
d
DP
39
ICM7224
38
4
5 BP
e
40
3
200pF
b
g
-
1 VDD
2
a
f
37
OSCILLATOR 36
6
VSS 35
7
STORE 34
8
RESET 33
9
COUNT 32
10
COUNT INHIBIT 31
11
LZB OUT 30
12
LZB IN 29
13
CARRY 28
14
1/ DIGIT 27
2
15
26
16
25
17
24
18
23
19
22
20
21
(BLANK)
FIGURE 7. SEGMENT ASSIGNMENT AND DISPLAY FONT
200pF
EACH SEGMENT TO
BACKPLANE WITH
200pF CAPACITOR
FIGURE 6. TEST CIRCUIT
6
ICM7224
LOW ORDER DIGITS
HIGH ORDER DIGITS
8-DIGIT LCD DISPLAY
WITH OVERFLOW
1 OVERFLOW
4 SEG
3 SEG
6 SEG
4 SEG
1 BACKPLANE
6 SEG
15 SEG
15 SEG
3 SEG
21
36
35
34
33
32
31
30
29
28
27
21
40
20
40
ICM7224
LOW ORDER DIGITS
MASTER BACKPLANE
1 VDD
1 VDD
36
35
34
33
32
31
30
29
28
27
OSC
5 BP
VSS
STORE
RESET
COUNT
COUNT INHIBIT
LZB OUT
LZB IN
CARRY
OSC
5 BP
VSS
STORE
RESET
COUNT
COUNT INHIBIT
LZB OUT
LZB IN
CARRY
20
ICM7224
HIGH ORDER DIGITS
SLAVE BACKPLANE
SWITCH CLOSED INHIBITS
LEADING ZERO BLANKING
10kΩ
VDD
3V - 6V
+
-
1
14
2
13
3
12
SWITCH OPEN
1s GATING
4
11
SWITCH CLOSED
0.1s GATING
5
10
6
9
7
8
ICM7207A
COUT
CIN
CRYSTAL
CIN = 22pF
COUT = 22pF
fO = 5.24288MHz
RS < 75Ω
CS = 0.015pF
CP = 3.5pF
1/ CD4069C
4
INPUT
SIGNAL
CONDITIONING
(PRESCALER
LEVEL SHIFTING)
FIGURE 8. EIGHT-DIGIT PRECISION FREQUENCY COUNTER
7
INPUT SIGNAL