[ /Title (ICM7 217) /Subject (4Digit LED Display, Programmable Up/Do wn Counte r) /Autho r () /Keywords (Intersil Corporation, Semiconductor, Programmable UpDown Counte r, Common Anode, LED, Com- July 2001 UCT PROD E PRODUCT E T E L UT OBSO UBSTIT 88-INTERSIL S E L -8 POSSIB m ions 1 FOR A tral Applicat @intersil.co p n p e a t C call il: cen or em a ICM7217 4-Digit LED Display, Programmable Up/Down Counter Features Description • Four Decade, Presettable Up-Down Counter with Parallel Zero Detect The ICM7217 is a four digit, presettable up/down counter with an onboard presettable register continuously compared to the counter. The ICM7217 is intended for use in hard-wired applications where thumbwheel switches are used for loading data, and simple SPDT switches are used for chip control. • Settable Register with Contents Continuously Compared to Counter • Directly Drives Multiplexed 7 Segment Common Anode or Common Cathode LED Displays This circuit provides multiplexed 7 segment LED display outputs, with common anode or common cathode configurations available. Digit and segment drivers are provided to directly drive displays of up to 0.8 inch character height (common anode) at a 25% duty cycle. The frequency of the onboard multiplex oscillator may be controlled with a single capacitor, or the oscillator may be allowed to free run. Leading zeros can be blanked. The data appearing at the 7 segment and BCD outputs is latched; the content of the counter is transferred into the latches under external control by means of the Store pin. • On-Board Multiplex Scan Oscillator • Schmitt Trigger On Count Input • TTL Compatible BCD I/O Port, Carry/Borrow, Equal, and Zero Outputs • Display Blank Control for Lower Power Operation; Quiescent Power Dissipation <5mW • All Terminals Fully Protected Against Static Discharge The ICM7217 (common anode) and ICM7217A (common cathode) versions are decade counters, providing a maximum count of 9999, while the ICM7217B (common anode) and ICM7217C (common cathode) are intended for timing purposes, providing a maximum count of 5959. • Single 5V Supply Operation This circuit provides 3 main outputs; a CARRY/BORROW output, which allows for direct cascading of counters, a ZERO output, which indicates when the count is zero, and an EQUAL output, which indicates when the count is equal to the value contained in the register. Data is multiplexed to and from the device by means of a three-state BCD I/O port. The CARRY/BORROW, EQUAL, ZERO outputs, and the BCD port will each drive one standard TTL load. To permit operation in noisy environments and to prevent multiple triggering with slowly changing inputs, the count input is provided with a Schmitt trigger. Input frequency is guaranteed to 2MHz, although the device will typically run with fIN as high as 5MHz. Counting and comparing (EQUAL output) will typically run 750kHz maximum. Part Number Information PART NUMBER TEMP. RANGE (oC) DISPLAY DRIVER TYPE PACKAGE COUNT OPTION/ MAX COUNT PKG. NO. ICM7217AIPI -25 to 85 28 Ld PDIP Common Cathode Decade/9999 E28.6 ICM7217CIPl -25 to 85 28 Ld PDIP Common Cathode Timing/5959 E28.6 ICM7217IJI -25 to 85 28 Ld CERDIP Common Anode Decade/9999 F28.6 lCM7217BlJl -25 to 85 28 Ld CERDIP Common Anode Timing/5959 F28.6 1-888-INTERSIL or 321-724-7143 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001 1 File Number 3167.3 ICM7217 Pinouts ICM7217 (PDIP) COMMON CATHODE TOP VIEW ICM7217 (CERDIP) COMMON ANODE TOP VIEW CARRY/BORROW 1 28 D1 CARRY/BORROW 1 28 SEG d ZERO 2 27 D2 ZERO 2 27 SEG b EQUAL 3 26 D3 EQUAL 3 26 SEG f BCD I/O 8s 4 25 D4 BCD I/O 8s 4 25 SEG c BCD I/O 4s 5 24 VDD BCD I/O 4s 5 24 VDD BCD I/O 2s 6 23 DISPLAY CONT. BCD I/O 2s 6 23 SEG a BCD I/O 1s 7 22 SEG g BCD I/O 1s 7 21 SEG b COUNT INPUT 8 COUNT INPUT 8 ICM7217 ICM7217B 20 VSS STORE 9 22 SEG e ICM7217A ICM7217C 21 SEG g 20 DISPLAY CONT. STORE 9 UP/DOWN 10 19 SEG e UP/DOWN 10 LOAD REGISTER/OFF 11 18 SEG f LOAD REGISTER/OFF 11 18 D1 LOAD COUNTER/I/O OFF 12 17 D2 19 VSS LOAD COUNTER/I/O OFF 12 17 SEG d SCAN 13 16 SEG a SCAN 13 16 D3 RESET 14 15 SEG c RESET 14 15 D4 Functional Block Diagram 4 ZERO 4 T.G. T.G. 1 4 D1 10 VDD UP/DN COUNT T.G. 2 4 RS D2 10 1 4 4 T.G. 3 D3 10 2 T.G. 4 4 4 4 RS 4 RS D4 10 3 4 3 T.G. 4 RS ZERO ZERO ZERO ZERO U/D U/D U/D U/D CL CARRY CL CARRY CL CARRY CL CARRY 4 4 D1 REG. 4 2 4 3 D2 REG. 4 COMP. 4 T.G. T.G. 1 4 2 4 COMP. 4 4 4 4 D3 REG. D4 REG. 1 4 4 COMP. COMP. 4 4 VSS CARRY/BARROW 8s T.G. T.G. T.G. T.G. 4s 4 4 4 4 BDC I/O 2s LATCH 1s LATCH LATCH MUX MUX MUX 4 4 4 4 SEGMENT DRIVERS (7) B C D E F L.R. G VDD LATCH L.C. RESET VDD MUX. I/O AND DISPLAY CONTROL LOGIC DISPLAY BLANK + OFF DIGIT DRIVERS (4) D4 D3 D2 STORE RESET LOAD VSS COUNTER VDD LOAD VSS REGISTER VDD VSS DISPLAY CONTROL 4 A VDD MUX SEGMENT DECODER EQUAL DIGIT MUX BCD I/O INPUTS COM. ANODE: PULL DOWN COM. CATHODE: PULL UP D1 2 4 MUX. OSCILLATOR SCAN ICM7217 Absolute Maximum Ratings Thermal Information Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Input Voltage (Any Terminal) . . . . . . . . (VSS - 0.3V) to (VDD + 0.3V) (Note 1) Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 55 14 PDIP Package . . . . . . . . . . . . . . . . . . . 55 N/A Maximum Junction Temperature PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than VDD or less than VSS may cause destructive device latchup. For this reason it is recommended that the power supply to the device be established before any inputs are applied and that in multiple systems the supply to the ICM7217 be turned on first. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = 5V, VSS = 0V, TA = 25oC, Display Diode Drop 1 .7V, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Current (Lowest Power Mode), IDD (7217) Display Off, LC, DC, UP/DN, ST, RS, BCD I/O Floating or at VDD (Note 1) - 350 500 µA Supply Current, OPERATING, IOP Common Anode, Display On, all “8’s” 140 200 - mA Supply Current, OPERATING, IOP Common Cathode, Display On, all “8’s” VSUPPLY , VDD 50 100 - mA 4.5 5 5.5 V Digit Driver Output Current, IDIG Common Anode, VOUT = VDD - 2.0V 140 200 - mAPEAK SEGment Driver Output Current, ISEG Common Anode, VOUT = +1.5V 20 35 - mAPEAK Digit Driver, Output Current, IDIG Common Cathode, VOUT = +1.0V -50 -75 - mAPEAK SEGment Driver Output Current, ISEG Common Cathode VOUT = VDD - 2V -9 -12.5 - mAPEAK ST, RS, UP/DN Input Pullup Current, IP VIN = VDD - 2V (Note 1) 5 25 - µA 3 Level Input Impendance, ZIN 40 - 350 kΩ BCD I/O Input, High Voltage VBIH ICM7217 Common Anode (Note 2) 1.5 - - V ICM7217 Common Cathode (Note 2) 4.40 - - V BCD I/O Input, Low Voltage VBIL ICM7217 Common Anode (Note 2) - - 0.60 V ICM7217 Common Cathode (Note 2) - - 3.2V V BCD I/O Input, Pullup Current IBPU ICM7217 Common Cathode VIN = VDD - 2V (Note 2) 5 25 - µA BCD I/O Input Pulldown Current, IBPD ICM7217 Common Anode VIN = +2V (Note 2) 5 25 - µA BCD I/O, ZERO, EQUAL Outputs Output High Voltage, VOH IOH = -100µA 3.5 - - V BCD I/O, CARRY/BORROW ZERO, EQUAL Outputs Output Low Voltage, VOL IOL = 1.6mA - - 0.4 V Count Input Frequency, fIN -20oC to 70oC - 5 - MHz Guaranteed 0 - 2 MHz Count Input Threshold, VTH (Note 3) - 2 - V Count Input Hysteresis, VHYS (Note 3) - 0.5 - V Count Input LO, VCIL - - 0.40 V Count Input HI, VCIH 3.5 - - V 3 ICM7217 Electrical Specifications VDD = 5V, VSS = 0V, TA = 25oC, Display Diode Drop 1 .7V, Unless Otherwise Specified PARAMETER Display Scan Oscillator Frequency, fDS TEST CONDITIONS MIN TYP MAX UNIT Free-running (SCAN Terminal Open Circuit) - 2.5 10 kHz Switching Specifications VDD = 5V, VSS = 0V, TA = 25oC PARAMETER MIN TYP MAX UNIT UP/DOWN Setup Time, tUCS 300 - - ns UP/DOWN Hold Time, tUCH 1500 750 - ns COUNT Pulse Width High, tCWH 250 100 - ns COUNT Pulse Width Low, tCWI 250 100 - ns COUNT to CARRY/BORROW Delay, tCB - 750 - ns CARRY/BORROW Pulse Width tBW - 100 - ns COUNT to EQUAL Delay, tCE - 500 - ns COUNT to ZERO Delay, tCZ - 300 - ns 1000 500 - ns RESET Pulse Width, tRST NOTES: 1. In the ICM7217 the UP/DOWN, STORE, RESET and the BCD I/O as inputs have pullup or pulldown devices which consume power when connected to the opposite supply. Under these conditions, with the display off, the device will consume typically 750µA. 2. These voltages are adjusted to allow the use of thumbwheel switches for the ICM7217. Note that a high level is taken as an input logic zero for ICM7217 common-cathode versions. 3. Parameters not tested (Guaranteed by Design). 4 ICM7217 Timing Waveforms SCAN 10µs TYP FREE-RUNNING 400µs TYP FREE-RUNNING INTERNAL OSC OUTPUT D4 INTERNAL (BCD AND SEGMENT ENABLE) D3 D2 D1 D4 INTERNAL (COMMON ANODE DIGIT STROBES) D3 INTERDIGIT BLANK D2 D1 FIGURE 1. MULTIPLEX TIMING tUCS tUCH UP/DOWN tCWL tCWH COUNT INPUT tCB tBW CARRY/BORROW tCEL tCEH EQUAL tCZL tCZH ZERO FIGURE 2. COUNT AND OUTPUTS TIMING 5 ICM7217 Timing Waveforms LOAD COUNTER (OR LOAD REGISTER) SCAN D4 D3 D2 D1 INTERNAL OPERATING MODE INPUT OUTPUT BCD I/O COUNT INHIBITED IF LOAD COUNTER D4 IN DN OUT D3 IN D2 IN D1 IN D4 OUT D3 OUT = HIGH IMPEDANCE = THREE-STATE W/PULLDOWN FIGURE 3. BCD I/O AND LOADING TIMING Typical Performance Curves 80 300 TA = 25oC 4.5 ≤ VDD ≤ 6V V+ = 5.5V ICM7217 ICM7217B ISEG (mA) IDIG (mA) 200 100 25oC 85oC 40 V+ = 4.5V V+ = 5V 20 -20oC 0 0 ICM7217 ICM7217B 60 1 VDD - VOUT (V) 2 0 3 0 1 2 VOUT (V) FIGURE 4. TYPICAL IDIG vs V+ FIGURE 5. TYPICAL ISEG vs VOUT 6 3 ICM7217 Typical Performance Curves 80 200 V+ = 5V V+ = 5V -20oC ICM7217 ICM7217B 150 IDIGIT (mA) ISEG (mA) 60 40 25oC 20 0 -20oC ICM7217A ICM7217C 100 25oC 50 85oC 85oC 0 0 1 2 0 3 1 FIGURE 6. TYPICAL ISEG vs VOUT 30 TA = 25oC -20oC 4.5 ≤ VDD − VSS ≤ 6V 25oC V+ = 5.5V 150 3 FIGURE 7. TYPICAL IDIGIT vs VOUT 200 ICM7217A ICM7217C 20 ICM7217A ICM7217C 100 ISEG (mA) IDIGIT (mA) 2 VOUT (V) VOUT (V) V+ = 4.5V 85oC 10 V+ = 5V 50 0 0 1 2 0 3 VOUT (V) 0 1 VDD - VOUT (V) 2 3 FIGURE 9. TYPICAL ISEG vs VDD - VOUT FIGURE 8. TYPICAL IDIGIT vs VOUT Detailed Description Control Outputs drive a single TTL load over the full range of supply voltage and ambient temperature; for a logic zero, these outputs will sink 1.6mA at 0.4V and for a logic one, the outputs will source >60µA. A 10kΩ pull-up resistor to VDD on the EQUAL or ZERO outputs is recommended for highest speed operation, and on the CARRY/BORROW output when it is being used for cascading. Figure 2 shows control outputs timing diagram. The CARRY/BORROW output is a positive going pulse occurring typically 500ns after the positive going edge of the COUNT INPUT. It occurs when the counter is clocked from 9999 to 0000 when counting up and from 0000 to 9999 when counting down. This output allows direct cascading of counters. The CARRY/BORROW output is not valid during load counter and reset operation. When the count is 6000 or higher, a reset generates a CARRY/BORROW pulse. Display Outputs and Control The EQUAL output assumes a negative level when the contents of the counter and register are equal. The Digit and SEGment drivers provide a decoded 7-segment display system, capable of directly driving common anode LED displays at typical peak currents of 35mA/seg. This corresponds to average currents of 8mA/seg at 25% multiplex duty cycle. For the common cathode versions, peak segment currents are 12.5mA, corre- The ZERO output assumes a negative level when the content of the counter is 0000. The CARRY/BORROW, EQUAL and ZERO outputs will 7 ICM7217 sponding to average segment currents of 3.1mA. Figure 1 shows the multiplex timing. The DISPLAY pin controls the display output using three level logic. The pin is self-biased to a voltage approximately 1/2 (VDD); this corresponds to normal operation. When this pin is connected to VDD , the segments are disabled and when connected to VSS , the leading zero blanking feature is inhibited. For normal operation (display on with leading zero blanking) the pin should be left open. The display may be controlled with a 3 position SPDT switch; see Test Circuit. Multiplex SCAN Oscillator The on-board multiplex scan oscillator has a nominal freerunning frequency of 2.5kHz. This may be reduced by the addition of a single capacitor between the SCAN pin and the positive supply. Capacitor values and corresponding nominal oscillator frequencies, digit repetition rates, and loading times are shown in Table 1. SCAN INPUT ICM7217 SCAN INPUT ICM7217 R1 10kΩ R2 20kΩ 500Ω C 1MΩ 1MΩ 500Ω 0.01µF 0.01µF FIGURE 10A. FIGURE 10B. VDD = 5V 10kΩ 7 8 3kΩ 4 ICM7555 3 SCAN INPUT ICM7217 200Ω 2 6 1 8s 0.05µF 0.05µF 0V FIGURE 10C. FIGURE 10. BRIGHTNESS CONTROL CIRCUITS During load counter and load register operations, the multiplex oscillator is disconnected from the SCAN input and is allowed to free-run. In all other conditions, the oscillator may be directly overdriven to about 20kHz, however the external oscillator signal should have the same duty cycle as the internal signal, since the digits are blanked during the time the external signal is at a positive level (see Figure 1). To insure proper leading zero blanking, the interdigit blanking time should not be less than about 2µs. Overdriving the oscillator at less than 200Hz may cause display flickering. TABLE 1. ICM7217 MULTIPLEXED RATE CONTROL SCAN CAPACITOR NOMINAL OSCILLATOR FREQUENCY DIGIT REPETITION RATE SCAN CYCLE TIME (4 DIGITS) None 2.5kHz 625Hz 1.6ms 20pF 1.25kHz 300Hz 3.2ms 90pF 600Hz 150Hz 8ms The internal oscillator output has a duty cycle of approximately 25:1, providing a short pulse occurring at the oscillator frequency. This pulse clocks the four-state counter which provides the four multiplex phases. The short pulse width is used to delay the digit driver outputs, thereby providing inter-digit blanking which prevents ghosting. The digits are scanned from MSD (D4) to LSD (D1). See Figure 1 for the display digit multiplex timing. The display brightness may be altered by varying the duty cycle. Figure 10 shows several variable-duty-cycle oscillators suitable for brightness control at the ICM7217 SCAN input. The inverters should be CMOS CD4000 series and the diodes may be any inexpensive device such as lN914. Counting Control, STORE, RESET As shown in Figure 2, the counter is incremented by the 8 ICM7217 rising edge of the COUNT INPUT signal when UP/DOWN is high. It is decremented when UP/DOWN is low. A Schmitt trigger on the COUNT INPUT provides hysteresis to prevent double triggering on slow rising edges and permits operation in noisy environments. The COUNT INPUT is inhibited during reset and load counter operations. is connected to VDD , the count input is inhibited and the levels at the BCD pins are multiplexed into the counter. When LR is connected to VDD , the levels at the BCD pins are multiplexed into the register without disturbing the counter. When both are connected to VDD , the count is inhibited and both register and counter will be loaded. The STORE pin controls the internal latches and consequently the signals appearing at the 7-Segment and BCD outputs. Bringing the STORE pin low transfers the contents of the counter into the latches. The LOAD COUNTER and LOAD REGISTER inputs are edge-triggered, and pulsing them high for 500ns at room temperature will initiate a full sequence of data entry cycle operations (see Figure 3). When the circuit recognizes that either or both of the LC or LR pins input is high, the multiplex oscillator and counter are reset (to D4). The internal oscillator is then disconnected from the SCAN pin and the preset circuitry is enabled. The oscillator starts and runs with a frequency determined by its internal capacitor, (which may vary from chip to chip). When the chip finishes a full 4-digit multiplex cycle (loading each digit from D4 to D3 to D2 to D1 in turn), it again samples the LOAD REGISTER and LOAD COUNTER inputs. If either or both is still high, it repeats the load cycle, if both are floating or low, the oscillator is reconnected to the SCAN pin and the chip returns to normal operation. Total load time is digit “on” time multiplied by 4. lf the Digit outputs are used to strobe the BCD data into the BCD I/O inputs, the input must be synchronized to the appropriate digit (Figure 3). Input data must be valid at the trailing edge of the digit output. The counter is asynchronously reset to 0000 by bringing the RESET pin low. The circuit performs the reset operation by forcing the BCD input lines to zero, and “presetting” all four decades of counter in parallel. This affects register loading; if LOAD REGISTER is activated when the RESET input is low, the register will also be set to zero. The STORE, RESET and UP/DOWN pins are provided with pullup resistors of approximately 75kΩ. BCD I/O Pins The BCD I/O port provides a means of transferring data to and from the device. The ICM7217 versions can multiplex data into the counter or register via thumbwheel switches, depending on inputs to the LOAD COUNTER or LOAD REGISTER pins; (see below). When functioning as outputs, the BCD I/O pins will drive one standard TTL load. Common anode versions have internal pull down resistors and common cathode versions have internal pull up resistors on the four BCD I/O lines when used as inputs. The BCD I/O pins, the LOAD COUNTER (LC), and LOAD REGISTER (LR) pins combine to provide presetting and compare functions. LC and LR are 3-level inputs, being selfbiased at approximately 1/2VDD for normal operation. With both LC and LR open, the BCD I/O pins provide a multiplexed BCD output of the latch contents, scanned from MSD to LSD by the display multiplex. When LR is connected to GROUND, the oscillator is inhibited, the BCD I/O pins go to the high impedance state, and the segment and digit drivers are turned off. This allows the display to be used for other purposes and minimizes power consumption. In this display off condition, the circuit will continue to count, and the CARRY/BORROW, EQUAL, ZERO, UP/DOWN, RESET and STORE functions operate as normal. When LC is connected to ground, the BCD I/O pins are forced to the high impedance state without disturbing the counter or register. See “Control Input Definitions” (Table 2) for a list of the pins that function as three-state selfbiased inputs and their respective operations. When either the LOAD COUNTER (Pin 12) or LOAD REGISTER (Pin 11) is taken low, the drivers are turned off and the BCD pins become high-impedance inputs. When LC Note that the ICM7217 and ICM7217B have been designed to drive common anode displays. The BCD inputs are high true, as are the BCD outputs. LOADing the COUNTER and REGISTER CD4069 INPUT 1N4148 INPUT OUTPUT CD4069 INPUT 1N4148 OUTPUT OUTPUT INPUT OUTPUT High High High Disconnected Low Disconnected Low High FIGURE 11A. CMOS INVERTER FIGURE 11B. CMOS INVERTER CD4502B INPUT A CD74HC03 INPUT A OUTPUT INPUT B INPUT B 9 OUTPUT ICM7217 CD4069 INPUT 1N4148 OUTPUT INPUT CD4069 INPUT OUTPUT 1N4148 OUTPUT INPUT OUTPUT INPUT B INPUT A OUTPUT INPUT B INPUT A OUTPUT High High Low High High Disconnected High Low Disconnected High Low Disconnected Low High Disconnected Low High High Low Low Disconnected Low Low Low FIGURE 11C. CMOS OPEN DRAIN FIGURE 11D. CMOS THREE-STATE BUFFER FIGURE 11. DRIVING 3-LEVEL INPUTS OF ICM7217 VDD 50kΩ DN DIGIT LINE 50kΩ DN DIGIT LINE DISPLAY CONTROL 50kΩ DISPLAY CONTROL ICM7217A ICM7217C VDD ICM7217 ICM7217B FIGURE 12B. COMMON CATHODE FIGURE 12A. COMMON ANODE FIGURE 12. FORCING LEADING ZERO DISPLAY VDD DIGIT DRIVE ICM7217 ICM7217B VDD SEGMENT DRIVE 2N2219 OR SIMILAR ICM7217 ICM7217C VSS VDD SEGMENT DRIVE 2N2219 OR SIMILAR VSS VDD DIGIT DRIVE 2N6034 OR SIMILAR VSS 2N6034 OR SIMILAR VSS FIGURE 13A. COMMON ANODE DISPLAY FIGURE 13B. COMMON CATHODE DISPLAY FIGURE 13. DRIVING HIGH CURRENT DISPLAYS 10 ICM7217 VDD = 5V VDD = 5V 35 D4 LCD DISPLAY D3 37 - 40 D2 ICM7211 2 - 26 28 SEGMENTS AND BACKPLANE D1 DB3 DB2 DB1 DB0 34 33 32 31 30 4 29 5 28 6 27 7 COUNT STORE UP/DN RESET 1 2 4 C 8 1 2 4 8 C 1 2 4 8 1 C 2 4 8s VDD 24 4s 2s DC 23 20 1s 8 D1 28 9 D2 ICM7217 D3 IJI D4 27 10 14 26 25 8 C 10kΩ - 20kΩ FIGURE 14. LCD DISPLAY INTERFACE (WITH THUMBWHEEL SWITCHES) cause erroneous glitches on the EQUAL and ZERO outputs when codes cross. The lCM7217A and the ICM7217C are used to drive common cathode displays, and the BCD inputs are low true. BCD outputs are high true. LOAD COUNTER or LOAD REGISTER, and RESET input can not be activated at the same time or within a short period of each other. Operation of each input must be delayed 1.6ms typical (5ms for guaranteed proper operation) relating to the preceding one. Notes on Thumbwheel Switches and Multiplexing As it was mentioned, the ICM7217 is basically designed to be used with thumbwheel switches for loading the data to the device. See Figure 14 and Figure 17. Counter and register can be loaded together with the same value if LC and LR inputs become activated exactly at the same time. The thumbwheel switches used with these circuits (both common anode and common cathode) are TRUE BCD coded; i.e. all switches open corresponds to 0000. Since the thumbwheel switches are connected in parallel, diodes must be provided to prevent crosstalk between digits. In order to maintain reasonable noise margins, these diodes should be specified with low forward voltage drops (IN914). Similarly, if the BCD outputs are to be used, resistors should be inserted in the Digit lines to avoid loading problems. Notice the setup and hold time of UP/DOWN input when it is changing during counting operation. Violation of UP/ DOWN hold time will result in incrementing or decrementing the counter by 1000, 100 or 10 where the preceding digit is transitioning from 5 to 6 or 6 to 5. The RESET input may be susceptible to noise if its input rise time is greater than about 500µs This will present no problems when this input is driven by active devices (i.e., TTL or CMOS logic) but in hardwired systems adding virtually any capacitance to the RESET input can cause trouble. A simple circuit which provides a reliable power-up reset and a fast rise time on the RESET input is shown on Figure 15. Output and Input Restrictions LOAD COUNTER and LOAD REGISTER operations take 1.6ms typical (5ms maximum) after LC or LR are released. During this load period the EQUAL and ZERO outputs are not valid (see Figure 3). Since the Counter and register are compared by XOR gates, loading the counter or register can 11 ICM7217 When using the circuit as a programmable divider (÷ by n with equal outputs) a short time delay (about 1µs) is needed from the EQUAL output to the RESET input to establish a pulse of adequate duration. (See Figure 16). N.O. When the circuit is configured to reload the counter or register with a new value from the BCD lines (upon reaching EQUAL), loading time will be digit “on” time multiplied by four. If this load time is longer than one period of the input count, a count can be lost. Since the circuit will retain data in the register, the register need only be updated when a new value is to be entered. RESET will not clear the register. VDD 0.047µF 10Ω RESET INPUT ICM7217 5kΩ 10kΩ VSS FIGURE 15. POWER ON RESET VDD 47pF 33K EQUAL RESET FIGURE 16. EQUAL TO RESET DELAY Test Circuit c a COMMON ANODE DISPLAY a f b g e a f b g c e c d d D4 f b g e b d g c e d D3 a a f f c e d D2 b D1 g THUMBWHEEL SWITCHES D4 BCD I/O 8s BCD I/O 4s BCD I/O 2s BCD I/O 1s COUNT INPUT D3 D2 D1 CARRY 1 28 ZERO 2 27 EQUAL 3 26 4 25 5 24 6 23 9999 7 STORE UP/DOWN LOAD REGISTER LOAD COUNTER SCAN RESET VDD 8 ICM7217 ICM7217B 21 9 20 10 19 11 18 12 17 13 16 14 15 N.O. VDD +5V VSS 12 22 DISPLAY CONTROL ICM7217 Applications a “fine” control. CD40106Bs are used as a monostable multivibrator and reset time delay. 3-Level Inputs Tape Recorder Position Indicator/controller ICM7217 has three inputs with 3-level logic states; High, Low and Disconnected. These inputs are: LOAD REGISTER/OFF, LOAD COUNTER/I/O OFF and DISPLAY CONT. The circuit in Figure 20 shows an application which uses the up/down counting feature of the ICM7217 to keep track of tape position. This circuit is representative of the many applications of up/down counting in monitoring dimensional position. The circuits illustrated on Figure 11 can be used to drive these inputs in different applications. Fixed Decimal Point In the tape recorder application, the LOAD REGISTER, EQUAL and ZERO outputs are used to control the recorder. To make the recorder stop at a particular point on the tape, the register can be set with the stop point and the EQUAL output used to stop the recorder either on fast forward, play or rewind. In the common anode versions, a fixed decimal point may be activated by connecting the DP segment lead from the appropriate digit (with separate digit displays) through a 39Ω series resistor to Ground. With common cathode devices, the DP segment lead should be connected through a 75Ω series resistor to VDD . To make the recorder stop before the tape comes free of the reel on rewind, a leader should be used. Resetting the counter at the starting point of the tape, a few feet from the end of the leader, allows the ZERO output to be used to stop the recorder on rewind, leaving the leader on the reel. To force the device to display leading zeroes after a fixed decimal point, use a bipolar transistor and base resistor in a configuration like that shown in Figure 12 with the resistor connected to the digit output driving the DP for left hand DP displays, and to the next least significant digit output for right hand DP display. The 1MΩ resistor and 0.0047µF capacitor on the COUNT INPUT provide a time constant of about 5ms to debounce the reel switch. The Schmitt trigger on the COUNT INPUT of the ICM7217 squares up the signal before applying it to the counter. This technique may be used to debounce switch-closure inputs in other applications. Driving Larger Displays For displays requiring more current than the ICM7217 can provide, the circuits of Figure 13 can be used. LCD Display Interface Precision Elapsed Time/Countdown Timer The low-power operation of the ICM7217 makes an LCD interface desirable. The Intersil ICM7211 4-digit, BCD-to-LCD display driver easily interfaces to the ICM7217 as shown in Figure 14. Total system power consumption is less than 5mW. System timing margins can be improved by using capacitance to ground to slow down the BCD lines. The circuit in Figure 21 uses an ICM7213 precision one minute/one second timebase generator using a 4.1943MHz crystal for generating pulses counted by an ICM7217B. The thumbwheel switches allow a starting time to be entered into the counter for a preset-countdown type timer, and allow the register to be set for compare functions. For instance, to make a 24-hour clock with BCD output the register can be preset with 2400 and the EQUAL output used to reset the counter. Note the 10K resistor connected between the LOAD COUNTER terminal and Ground. This resistor pulls the LOAD COUNTER input low when not loading, thereby inhibiting the BCD output drivers. This resistor should be eliminated and SW4 replaced with an SPDT center-off switch if the BCD outputs are to be used. The 10kΩ - 20kΩ resistors on the switch BCD lines serve to isolate the switches during BCD output. Unit Counter with BCD Output The simplest application of the ICM7217 is a 4-digit unit counter (Figure 18). All that is required is an ICM7217, a power supply and a 4 digit display. Add a momentary switch for reset, an SPDT center-off switch to blank the display or view leading zeroes, and one more SPDT switch for up/ down control. Using an ICM7217A with a common-cathode calculator-type display results in the least expensive digital counter/display system available. This technique may be used on any 3-level input. The 100kΩ pullup resistor on the count input is used to ensure proper logic voltage swing from the ICM7213. For a less expensive (and less accurate) timebase, an ICM7555 timer may be used in a configuration like that shown in Figure 19 to generate a 1Hz reference. Inexpensive Frequency Counter/ Tachometer This circuit uses the low power ICM7555 (CMOS 555) to generate the gating, STORE and RESET signals as shown in Figure 19. To provide the gating signal, the timer is configured as an a stable multivibrator, using RA, RB and C to provide an output that is positive for approximately one second and negative for approximately 300µs - 500µs. The positive waveform time is given by tWP = 0.693 (RA + RB)C while the negative waveform is given by two = 0.693 RBC. The system is calibrated by using a 5MΩ potentiometer for RA as a “coarse” control and a 1kΩ potentiometer for RB as 8-Digit Up/Down Counter This circuit (Figure 22) shows how to cascade counters and retain correct leading zero blanking. The NAND gate detects whether a digit is active since one of the two segments a or b is active on any unblanked number. The flip flop is clocked by the least significant digit of the high order counter, and if this digit is not blanked, the Q output of the flip flop goes high and turns on the NPN transistor, thereby inhibiting leading zero blanking on the low order counter. 13 ICM7217 It is possible to use separate thumbwheel switches for presetting, but since the devices load data with the oscillator free-running, the multiplexing of the two devices is difficult to synchronize. be measured must be multiplied by 60. This can be done electronically using a phase-locked loop, or mechanically by using a disc rotating with the object with the appropriate number of holes drilled around its edge to interrupt the light from an LED to a photo-dector. For faster updating, use 0.1s gating, and multiply the rotational frequency by 600. Precision Frequency Counter/Tachometer The circuit shown in Figure 23 is a simple implementation of a four digit frequency counter, using an ICM7207A to provide the one second gating window and the STORE and RESET signals. In this configuration, the display reads hertz directly. With Pin 11 of the ICM7027A connected to VDD , the gating time will be 0.1s; this will display tens of hertz at the least significant digit. For shorter gating times, an ICM7207 may be used (with a 6.5536MHz crystal), giving a 0.01s gating with Pin 11 connected to VDD , and a 0.1s gating with Pin 11 open. Auto-Tare System This circuit uses the count-up and count-down functions of the ICM7217, controlled via the EQUAL and ZERO outputs, to count in SYNC with an ICL7109A and ICL7109D Converter as shown in Figure 24. By RESETing the ICM7217 on a “tare” value conversion, and STORE-ing the result of a true value conversion, an automatic fare subtraction occurs in the result. The ICM7217 stays in step with the ICL7109 by counting up and down between 0 and 4095, for 8192 total counts, the same number as the ICL7109 cycle. See applications note No. A047 for more details. To implement a four digit tachometer, the ICM7207A with one second gating should be used. To get the display to read directly in RPM, the rotational frequency of the object to TABLE 2. CONTROL INPUT DEFINITIONS ICM7217 INPUT TERMINAL VOLTAGE FUNCTION STORE 9 VDD (or floating) VSS Output Latches Not Updated Output Latches Updated UP/DOWN 10 VDD (or floating) VSS Counter Counts Up Counter Counts Down RESET 14 VDD (or floating) VSS Normal Operation Counter Reset LOAD COUNTER/ I/O OFF 12 Unconnected VDD VSS Normal Operation Counter Loaded with BCD data BCD Port Forced to Hi-Z Condition LOAD REGlSTER/ OFF 11 Unconnected VDD VSS Normal Operation Register Loaded with BCD Data Display Drivers Disabled; BCD Port Forced to Hi-Z Condition, mpx Counter Reset to D4; mpx Oscillator Inhibited DISPLAY CONTrol 23 Common Anode 20 Common Cathode Unconnected Normal Operation Segment Drivers Disabled Leading Zero Blanking Inhibited VDD VSS 14 ICM7217 TO D4 STROBE TO D1 STROBE TO D4 STROBE TO D1 STROBE C C C C 8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1 IN914 OR EQUIVALENT 8 4 2 1 8 TO BCD INPUTS OF ICM7217, ICM7217B 1 ZERO 2 21 - 23 25 - 28 7 SEGMENTS COMMON CATHODE LED DISPLAY 4 5 BCD I/O 6 7 8 COUNT INPUT STORE 9 ICM7217A 24 20 DISPLAY CONTROL VDD BLANK NORMAL INHIBIT LZB 19 14 2 1 TO BCD INPUTS OF ICM7217A, ICM7217C FIGURE 17. THUMBWHEEL SWITCH/DIODE CONNECTIONS CARRY 4 15 - 18 4-DIGIT RESET FIGURE 18. UNIT COUNTER 15 ICM7217 5M RA 7 8 4 RS VDD DIS OUT 3K 10K 9 3 VDD STORE 24 0.047µF 1K LED DISPLAY RB 2 6 ICM7217 8 GATE TR COUNT TH VSS 0.47µF C CV 1 14 5 RESET VSS 20 GND INVERTERS: CD40106B NANDS: CD4011B COUNT INPUT FIGURE 19A. 300µs 1s GATE 50µs STORE RESET FIGURE 19B. FIGURE 19. INEXPENSIVE FREQUENCY COUNTER STOP LOGIC TO GENERATE RECORDER CONTROL SIGNALS EQ THUMBWHEEL SWITCHES REEL SWITCH CLOSED ONCE/REV VDD 1M 4 DIGIT 9999 1 CARRY d ZERO b EQUAL 0.0047µF BCD I/O VDD a e g UP/DOWN LOAD REG D1 LOAD CTR D2 SCAN D3 RESET D4 N.O. SET PT VDD INHIBIT LZB RESET FIGURE 20. TAPE RECORDER POSITION INDICATOR 16 BLANK NORMAL REWIND VDD 7 SEGMENTS f FORWARD N.O. 28 c COUNT IN STORE VDD COMMON CATHODE LED DISPLAY ZERO 4 DIGITS ICM7217 VDD RUN MIN/SEC 30pF 1 14 2 13 3 12 4 ICM7213 STOP 100K SW1 RUN HRS/MIN 11 5 10 6 9 7 8 VDD (4V MAX) EQUAL ZERO TO LOGIC GENERATING SIGNALS FOR CONTROL OF EXTERNAL EQUIPMENT 4 30pF 4.1943MHz CRYSTAL RS < 75Ω CARRY D1 ZERO D2 EQUAL D3 BCD I/O VDD THUMBWHEEL SWITCHES 5959 D4 4 VDD LOAD SET PT. DISPLAY OFF VDD SW2 g VDD UP/DOWN LOAD REG SW3 10K PRESET SW4 RESET VDD DIS. CONT. COUNT IN STORE ELAPSED COUNTDOWN DIGITS 4 LOAD CTR b VSS e SW6 VDD INHIBIT LZB COMMON ANODE LED DISPLAY f d SCAN a RESET c ICM7217 SW5 FIGURE 21. PRECISION TIMER 17 BLANK 7 SEGMENTS ICM7217 COMMON-ANODE LED DISPLAY COUNT INPUT CARRY OUT 1 BCD OUTPUTS HIGH ORDER DIGITS 4 25 - 28 4-7 4 DIGITS CARRY/BORROW 4 DIGITS 7 SEGMENTS D1 BCD OUTPUTS HIGH ORDER DIGITS 24 1 V+ 7 SEGMENTS 20 4 25 - 28 4-7 ICM7217 24 8 V+ N.O. RESET 20 1A 9 UP/DOWN 10 15 - 19 21, 22 1B 14 V+ ICM7217 1/ 4 CD4011 23 8 HIGH ORDER 9 10 15 - 19 21, 22 14 LOW ORDER V+ 50kΩ 3kΩ D 1/ 2 CD4013 Q CL FIGURE 22. 8-DIGIT UP/DOWN COUNTER 18 50kΩ NPN TRANSISTOR V+ = 5V 22pF 22pF 10kΩ 25 - 28 4 DIGITS 4 14 6 7 13 2 24 5 BCD OUT ICM7207A 10kΩ COMMON ANODE LED DISPLAY ICM7217 10 4 5 COUNT 6 CRYSTAL f = 5.24288MHz RS = 75Ω 1/ 8 STORE 15 - 19 21, 22 9 4 7 SEGMENTS CD4011 RESET 20 14 INPUT FIGURE 23. PRECISION FREQUENCY COUNTER (MHz MAXIMUM) +5V 400mV FULL SCALE INPUT + - 4 DIGIT COMMON ANODE LED DISPLAY D 0.1µF 1 GND 2 STATUS VDD 40 REF IN - 39 3 POL REF CAP - 38 4 OR REF CAP + 37 5 B12 REF IN + 36 6 B11 IN HI 35 7 B10 IN LO 34 8 B9 COMMON 33 9 B8 INT 32 10 B7 ICM7109 BUF 30 12 B5 REF OUT 29 13 B4 VSS 28 14 B3 SEND 27 15 B2 RUN/HOLD 26 OSC SEL 24 18 LBEN OSC OUT 23 19 HBEN OSC IN 22 20 CE/LOAD MODE 21 Q D S R Q 270 7 Q LED MINUS SIGN 10K 5 x 1N4148 1 CARRY/ BORROW 2 ZERO D0 28 3 EQUAL D2 26 4 BCD 8 D3 25 0.22µF 5 BCD 4 VDD 24 DISP. 23 CONT. G 22 47K 7 BCD 1 100K +5V 8 COUNT B 21 9 STORE VSS 20 10 UP/DOWN 100pF +5V 10µF 100K +5V F 18 12 LOAD CTR. D 17 13 SCAN A 16 14 RESET C 15 FIGURE 24. AUTO-TARE SYSTEM FOR A/D CONVERTER 19 E 19 11 LOAD REG. TARE 7 D1 27 0.1µF 6 BCD 2 BUF OSC OUT 25 17 TEST R Q 100K 1µF AZ 31 11 B6 16 B1 +5V +5V S ICM7217 +5V 47µF ICM7217 All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 20 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369