AD REF19XGBC

Precision Micropower, Low Dropout
Voltage References
REF19x Series
PIN CONFIGURATIONS
8-Lead Narrow-Body SOIC and TSSOP
(S Suffix and RU Suffix)
FEATURES
Initial Accuracy: ⴞ2 mV Max
Temperature Coefficient: 5 ppm/ⴗC Max
Low Supply Current: 45 ␮A Max
Sleep Mode: 15 ␮A Max
Low Dropout Voltage
Load Regulation: 4 ppm/mA
Line Regulation: 4 ppm/V
High Output Current: 30 mA
Short Circuit Protection
1
TP
VS
2
SLEEP
3
GND
4
8 NC
REF19x
SERIES
7 NC
TOP VIEW
(Not to Scale)
6 OUTPUT
5 TP
NC = NO CONNECT
TP PINS ARE FACTORY TEST POINTS,
NO USER CONNECTION
APPLICATIONS
Portable Instrumentation
A-to-D and D-to-A Converters
Smart Sensors
Solar Powered Applications
Loop Current Powered Instrumentations
8-Lead Epoxy DIP (P Suffix)
GENERAL DESCRIPTION
REF19x series precision band gap voltage references use a patented temperature drift curvature correction circuit and laser
trimming of highly stable thin film resistors to achieve a very low
temperature coefficient and a high initial accuracy.
8 NC
TP
1
VS
2
REF19x
SERIES
SLEEP
3
TOP VIEW
(Not to Scale)
GND
4
7
NC
6
OUTPUT
5
TP
NC = NO CONNECT
TP PINS ARE FACTORY TEST POINTS,
NO USER CONNECTION
The REF19x series is made up of micropower, Low Dropout
Voltage (LDV) devices providing a stable output voltage from
supplies as low as 100 mV above the output voltage and consuming less than 45 µA of supply current. In sleep mode, which is
enabled by applying a low TTL or CMOS level to the sleep pin,
the output is turned off and supply current is further reduced to
less than 15 µA.
Table I.
The REF19x series references are specified over the extended
industrial temperature range (–40°C to +85°C) with typical
performance specifications over –40°C to +125°C for applications
such as automotive.
All electrical grades are available in 8-lead SOIC; the PDIP and
TSSOP are only available in the lowest electrical grade. Products
are also available in die form.
Part
Number
Nominal Output
Voltage (V)
REF191
REF192
REF193
REF194
REF195
REF196
REF198
2.048
2.50
3.00
4.50
5.00
3.30
4.096
ORDERING GUIDE
Test Pins (TP)
The test pins, Pin 1 and Pin 5, are reserved for in-package
Zener-zap. To achieve the highest level of accuracy at the output,
the Zener-zapping technique is used to trim the output voltage.
Since each unit may require a different amount of adjustment, the
resistance value at the test pins will vary widely from pin to pin as
well as from part to part. The user should not make any physical
nor electrical connections to Pin 1 and Pin 5.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Model
Temperature
Range
Package
Description
Package
Option1
REF19xGP
REF19xES3
REF19xFS3
REF19xGS
REF19xGRU4
REF19xGBC
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
25°C
8-Lead Plastic DIP2
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead TSSOP
DICE
N-8
SOIC-8
SOIC-8
SOIC-8
RU-8
NOTES
1
N = Plastic DIP, SOIC = Small Outline, RU = Thin Shrink Small Outline.
2
8-lead plastic DIP is only available in “G” grade.
3
REF193 and REF196 are only available in “G” grade.
4
Available for REF192, REF195, and REF198 only.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = 25ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
Max
Unit
VO
IOUT = 0 mA
2.046
2.043
2.038
2.048
2.050
2.053
2.058
V
V
V
LINE REGULATION2
E Grade
F and G Grades
⌬VO /⌬VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
2
4
4
8
ppm/V
ppm/V
LOAD REGULATION2
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA
4
6
10
15
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.15 V, ILOAD = 2 mA
VS = 3.3 V, ILOAD = 10 mA
VS = 3.6 V, ILOAD = 30 mA
0.95
1.25
1.55
V
V
V
LONG-TERM STABILITY3
DVO
1000 Hours @ 125°C
1.2
mV
NOISE VOLTAGE
eN
0.1 Hz to 10 Hz
20
µV p-p
1
INITIAL ACCURACY
E Grade
F Grade
G Grade
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +85ⴗC, unless otherwise noted.)
S
Parameter
Symbol
A
Condition
Min
Typ
Max
Unit
TEMPERATURE COEFFICIENT1, 2
E” Grade
TCVO/°C
F Grade
G Grade3
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
E Grade
F and G Grades
⌬VO /⌬VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
5
10
10
20
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 C
5
10
15
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.15 V, ILOAD = 2 mA
VS = 3.3 V, ILOAD = 10 mA
VS = 3.6 V, ILOAD = 25 mA
0.95
1.25
1.55
V
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
–8
0.8
–8
V
µA
V
µA
45
15
µA
µA
SUPPLY CURRENT
Sleep Mode
2.4
No Load
No Load
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
–2–
REV. E
REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
Max
Unit
TCVO/°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
E Grade
F and G Grades
⌬VO /⌬VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
10
20
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA
10
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.3 V, ILOAD = 10 mA
VS = 3.6 V, ILOAD = 20 mA
1, 2
TEMPERATURE COEFFICIENT
E Grade
F Grade
G Grade3
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. E
–3–
1.25
1.55
V
V
REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = 25ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
Max
Unit
VO
IOUT = 0 mA
2.498
2.495
2.490
2.500
2.502
2.505
2.510
V
V
V
LINE REGULATION2
E Grade
F and G Grades
⌬VO /⌬VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
2
4
4
8
ppm/V
ppm/V
LOAD REGULATION2
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA
4
6
10
15
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.5 V, ILOAD = 10 mA
VS = 3.9 V, ILOAD = 30 mA
1.00
1.40
V
V
LONG-TERM STABILITY3
DVO
1000 Hours @ 125°C
1.2
mV
NOISE VOLTAGE
eN
0.1 Hz to 10 Hz
25
µV p-p
1
INITIAL ACCURACY
E Grade
F Grade
G Grade
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = –40ⴗC ≤ T ≤ +85ⴗC, unless otherwise noted.)
S
Parameter
A
A
Symbol
Condition
TCVO/°C
LINE REGULATION4
E Grade
F and G Grades
Min
Typ
Max
Unit
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
⌬VO /⌬VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
5
10
10
20
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA
5
10
15
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.5 V, ILOAD = 10 mA
VS = 4.0 V, ILOAD = 25 mA
1.00
1.50
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
–8
0.8
–8
V
µA
V
µA
45
15
µA
µA
1, 2
TEMPERATURE COEFFICIENT
E Grade
F Grade
G Grade3
SUPPLY CURRENT
Sleep Mode
2.4
No Load
No Load
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
–4–
REV. E
REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
Max
Unit
TCVO/°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
E Grade
F and G Grades
⌬VO /⌬VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
10
20
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA
10
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.5 V, ILOAD = 10 mA
VS = 4.0 V, ILOAD = 20 mA
1, 2
TEMPERATURE COEFFICIENT
E Grade
F Grade
G Grade3
1.00
1.50
V
V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
(@ VS = 3.3 V, TA = 25ⴗC, unless otherwise noted.)
Symbol
Condition
Min
Typ
Max
Unit
VO
IOUT = 0 mA
2.990
3.0
3.010
V
⌬VO /⌬VIN
3.3 V, ≤ VS ≤ 15 V, IOUT = 0 mA
4
8
ppm/V
LOAD REGULATION
G Grade
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA
6
15
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.8 V, ILOAD = 10 mA
VS = 4.0 V, ILOAD = 30 mA
0.80
1.00
V
V
LONG-TERM STABILITY 3
DVO
1000 Hours @ 125°C
1.2
mV
NOISE VOLTAGE
eN
0.1 Hz to 10 Hz
30
µV p-p
INITIAL ACCURACY1
G Grade
2
LINE REGULATION
G Grades
2
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
REV. E
–5–
REF19x Series
REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
(@ VS = 3.3 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Symbol
Condition
TCVO/°C
Min
Typ
Max
Unit
IOUT = 0 mA
10
25
ppm/°C
⌬VO /⌬VIN
3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA
10
20
ppm/V
LOAD REGULATION
G Grade
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA
10
20
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.8 V, ILOAD = 10 mA
VS = 4.1 V, ILOAD = 30 mA
0.80
1.10
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
–8
0.8
–8
V
µA
V
µA
45
15
µA
µA
Max
Unit
1, 2
TEMPERATURE COEFFICIENT
G Grade3
4
LINE REGULATION
G Grade
4
2.4
SUPPLY CURRENT
Sleep Mode
No Load
No Load
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
TCVO/°C
IOUT = 0 mA
10
ppm/°C
⌬VO /⌬VIN
3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA
20
ppm/V
LOAD REGULATION
G Grade
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA
10
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.8 V, ILOAD = 10 mA
VS = 4.1 V, ILOAD = 20 mA
1, 2
TEMPERATURE COEFFICIENT
G Grade3
4
LINE REGULATION
G Grade
4
0.80
1.10
V
V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
–6–
REV. E
REF19x Series
REF194–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, T = 25ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
Max
Unit
VO
IOUT = 0 mA
4.498
4.495
4.490
4.5
4.502
4.505
4.510
V
V
V
LINE REGULATION2
E Grade
F and G Grades
⌬VO /⌬VIN
4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA
2
4
4
8
ppm/V
ppm/V
LOAD REGULATION2
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.8 V, 0 mA ≤ IOUT ≤ 30 mA
2
4
4
8
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.00 V, ILOAD = 10 mA
VS = 5.8 V, ILOAD = 30 mA
0.50
1.30
V
V
LONG-TERM STABILITY3
DVO
1000 Hours @ 125°C
2
mV
NOISE VOLTAGE
eN
0.1 Hz to 10 Hz
45
µV p-p
1
INITIAL ACCURACY
E Grade
F Grade
G Grade
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
Parameter
(@ VS = 5.0 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Symbol
Condition
TCVO/°C
LINE REGULATION4
E Grade
F and G Grades
Min
Typ
Max
Unit
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
⌬VO /⌬VIN
4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA
5
10
10
20
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.80 V, 0 mA ≤ IOUT ≤ 25 mA
5
10
15
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.00 V, ILOAD = 10 mA
VS = 5.80 V, ILOAD = 25 mA
0.5
1.30
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
–8
0.8
–8
V
µA
V
µA
45
15
µA
µA
1, 2
TEMPERATURE COEFFICIENT
E Grade
F Grade
G Grade3
SUPPLY CURRENT
Sleep Mode
2.4
No Load
No Load
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. E
–7–
REF19x Series
REF194–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
Max
Unit
TCVO/°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
E Grade
F and G Grades
⌬VO /⌬VIN
4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA
5
10
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.80 V, mA 0 ≤ IOUT ≤ 20 mA
5
10
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.10 V, ILOAD = 10 mA
VS = 5.95 V, ILOAD = 20 mA
1, 2
TEMPERATURE COEFFICIENT
E Grade
F Grade
G Grade3
0.60
1.45
V
V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
–8–
REV. E
REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.10 V, T = 25ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
Max
Unit
VO
IOUT = 0 mA
4.998
4.995
4.990
5.0
5.002
5.005
5.010
V
V
V
LINE REGULATION2
E Grade
F and G Grades
⌬VO /⌬VIN
5.10 V ≤ VS ≤ 15 V, IOUT = 0 mA
2
4
4
8
ppm/V
ppm/V
LOAD REGULATION2
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 6.30 V, 0 mA ≤ IOUT ≤ 30 mA
2
4
4
8
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.50 V, ILOAD = 10 mA
VS = 6.30 V, ILOAD = 30 mA
0.50
1.30
V
V
LONG-TERM STABILITY3
DVO
1000 Hours @ 125°C
1.2
mV
NOISE VOLTAGE
eN
0.1 Hz to 10 Hz
50
µV p-p
1
INITIAL ACCURACY
E Grade
F Grade
G Grade
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
Parameter
(@ VS = 5.15 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Symbol
Condition
TCVO/°C
LINE REGULATION4
E Grade
F and G Grades
Min
Typ
Max
Unit
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
⌬VO /⌬VIN
5.15 V ≤ VS ≤ 15 V, IOUT = 0 mA
5
10
10
20
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 6.30 V, 0 mA ≤ IOUT ≤ 25 mA
5
10
10
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.50 V, ILOAD = 10 mA
VS = 6.30 V, ILOAD = 25 mA
0.50
1.30
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
–8
0.8
–8
V
µA
V
µA
45
15
µA
µA
1, 2
TEMPERATURE COEFFICIENT
E Grade
F Grade
G Grade3
SUPPLY CURRENT
Sleep Mode
2.4
No Load
No Load
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. E
–9–
REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.20 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
Max
Unit
TCVO/°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
E Grade
F and G Grades
⌬VO /⌬VIN
5.20 V ≤ VS ≤ 15 V, IOUT = 0 mA
5
10
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 6.45 V, 0 mA ≤ IOUT ≤ 20 mA
5
10
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.60 V, ILOAD = 10 mA
VS = 6.45 V, ILOAD = 20 mA
1, 2
TEMPERATURE COEFFICIENT
E Grade
F Grade
G Grade3
0.60
1.45
V
V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REF196–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.5 V, T = 25ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
Min
Typ
Max
Unit
VO
IOUT = 0 mA
3.290
3.3
3.310
V
⌬VO /⌬VIN
3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA
4
8
ppm/V
LOAD REGULATION
G Grade
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA
6
15
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 4.1 V, ILOAD = 10 mA
VS = 4.3 V, ILOAD = 30 mA
0.80
1.00
V
V
LONG-TERM STABILITY3
DVO
1000 Hours @ 125°C
1.2
mV
NOISE VOLTAGE
eN
0.1 Hz to 10 Hz
33
µV p-p
1
INITIAL ACCURACY
G Grade
LINE REGULATION2
G Grades
2
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
–10–
REV. E
REF19x Series
REF196–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
(@ VS = 3.5 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Symbol
Condition
TCVO/°C
Min
Typ
Max
Unit
IOUT = 0 mA
10
25
ppm/°C
⌬VO /⌬VIN
3.5 V ≤ VS ≤ 15 V, IOUT = 0 mA
10
20
ppm/V
LOAD REGULATION
G Grade
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA
10
20
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 4.1 V, ILOAD = 10 mA
VS = 4.3 V, ILOAD = 25 mA
0.80
1.00
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
–8
0.8
–8
V
µA
V
µA
45
15
µA
µA
Max
Unit
1, 2
TEMPERATURE COEFFICIENT
G Grade3
4
LINE REGULATION
G Grade
4
2.4
SUPPLY CURRENT
Sleep Mode
No Load
No Load
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
Parameter
(@ VS = 3.50 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Symbol
Condition
Min
Typ
TCVO/°C
IOUT = 0 mA
10
ppm/°C
⌬VO /⌬VIN
3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA
20
ppm/V
LOAD REGULATION
G Grade
⌬VO /⌬VLOAD
VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA
20
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 4.1 V, ILOAD = 10 mA
VS = 4.4 V, ILOAD = 20 mA
1, 2
TEMPERATURE COEFFICIENT
G Grade3
4
LINE REGULATION
G Grade
4
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. E
–11–
0.80
1.10
V
V
REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
(@ VS = 5.0 V, TA = 25ⴗC, unless otherwise noted.)
Symbol
Condition
Min
Typ
Max
Unit
VO
IOUT = 0 mA
4.094
4.091
4.086
4.096
4.098
4.101
4.106
V
V
V
LINE REGULATION2
E Grade
F and G Grades
⌬VO /⌬VIN
4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA
2
4
4
8
ppm/V
ppm/V
LOAD REGULATION2
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.4 V, 0 mA ≤ IOUT ≤ 30 mA
2
4
4
8
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 4.6 V, ILOAD = 10 mA
VS = 5.4 V, ILOAD = 30 mA
0.50
1.30
V
V
LONG-TERM STABILITY3
DVO
1000 Hours @ 125°C
1.2
mV
NOISE VOLTAGE
eN
0.1 Hz to 10 Hz
40
µV p-p
1
INITIAL ACCURACY
E Grade
F Grade
G Grade
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, –40ⴗC ≤ T ≤ +85ⴗC, unless otherwise noted.)
S
Parameter
A
Symbol
Condition
TCVO/°C
LINE REGULATION4
E Grade
F and G Grades
Min
Typ
Max
Unit
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
⌬VO /⌬VIN
4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA
5
10
10
20
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.4 V, 0 mA ≤ IOUT ≤ 25 mA
5
10
10
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 4.6 V, ILOAD = 10 mA
VS = 5.4 V, ILOAD = 25 mA
0.50
1.30
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
–8
0.8
–8
V
µA
V
µA
45
15
µA
µA
1, 2
TEMPERATURE COEFFICIENT
E Grade
F Grade
G Grade3
SUPPLY CURRENT
Sleep Mode
2.4
No Load
No Load
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
–12–
REV. E
REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
(@ VS = 5.0 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Symbol
Condition
Min
Typ
Max
Unit
TCVO /°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
E Grade
F and G Grades
⌬VO /⌬VIN
4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA
5
10
ppm/V
ppm/V
LOAD REGULATION4
E Grade
F and G Grades
⌬VO /⌬VLOAD
VS = 5.6 V, 0 mA ≤ IOUT ≤ 20 mA
5
10
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 4.7 V, ILOAD = 10 mA
VS = 5.6 V, ILOAD = 20 mA
1, 2
TEMPERATURE COEFFICIENT
E Grade
F Grade
G Grade3
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. E
–13–
0.60
1.50
V
V
REF19x Series
WAFER TEST LIMITS (@ I
Parameter
INITIAL ACCURACY
REF191
REF192
REF193
REF194
REF195
REF196
REF198
LOAD
= 0 mA, TA = 25ⴗC, unless otherwise noted.)
Symbol
Condition
VO
Limit
Unit
2.043/2.053
2.495/2.505
2.990/3.010
4.495/4.505
4.995/5.005
3.290/3.310
4.091/4.101
V
V
V
V
V
V
V
LINE REGULATION
⌬VO /⌬VIN
(VO + 0.5 V) < VIN < 15 V, IOUT = 0 mA
15
ppm/V
LOAD REGULATION
⌬VO /⌬ILOAD
0 mA < ILOAD < 30 mA, VIN = (VO + 1.3 V)
15
ppm/mA
DROPOUT VOLTAGE
VO – V+
ILOAD = 10 mA
ILOAD = 30 mA
1.25
1.55
V
V
SLEEP MODE INPUT
Logic Input High
Logic Input Low
VIH
VIL
2.4
0.8
V
V
45
15
µA
µA
SUPPLY CURRENT
Sleep Mode
VIN = 15 V
No Load
No Load
For proper operation, a 1 µF capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer probe to the limits shown.
Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications
based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS 1
DICE CHARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V
Output to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VS + 0.3 V
Output to GND Short-Circuit Duration . . . . . . . . . Indefinite
Storage Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
REF19x . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
Package Type
␪JA2
␪JC
Unit
8-Lead PDIP (P)
8-Lead SOIC (S)
8-Lead TSSOP (RU)
103
158
240
43
43
43
°C/W
°C/W
°C/W
NOTES
1
Absolute maximum rating applies to both DICE and packaged parts, unless
otherwise noted.
2
θJA is specified for worst case conditions, i.e., θJA is specified for device in socket for
PDIP, and θJA is specified for device soldered in circuit board for SOIC package.
OUTPUT
6
OUTPUT
6
2
Vⴙ
3
SLEEP
4
GND
REF19x Die Size 0.041” ⫻ 0.057”, 2,337 Square Mils
Substrate Is Connected to V+, Number of Transistors:
Bipolar 25, MOSFET4. Process: CBCMOS1
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
REF19x features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–14–
REV. E
Typical Performance Characteristics–REF19x Series
50
5.004
3 TYPICAL PARTS
5.15V < VIN < 15V
45
PERCENTAGE OF PARTS – %
OUTPUT VOLTAGE – V
5.003
5.002
5.001
5.000
4.999
4.998
4.997
–40ⴗC
TA
+85ⴗC
10
15
40
35
30
25
20
15
10
5
4.996
–50
–25
0
25
50
TEMPERATURE – ⴗC
75
0
–20
100
TPC 1. REF195 Output Voltage vs. Temperature
–15
–10
–5
0
5
TC – VOUT – ppm/ⴗC
20
TPC 4. TC – VOUT Distribution
32
40
28
35
5.15V
VS
NORMAL MODE
15V
24
SUPPLY CURRENT – ␮A
LOAD REGULATION – ppm/V
BASED ON 600
UNITS, 4 RUNS
–40ⴗC
20
16
+25ⴗC
12
+85ⴗC
8
30
25
20
15
10
SLEEP MODE
4
0
5
0
5
10
15
ILOAD – mA
20
25
0
–50
30
TPC 2. REF195 Load Regulation vs. ILOAD
0
25
50
TEMPERATURE – ⴗC
+85ⴗC
–5
SLEEP PIN CURRENT – ␮A
16
+25ⴗC
12
–40ⴗC
8
4
–4
–3
–2
VL
–1
4
6
8
10
VIN – V
12
14
0
–50
16
TPC 3. REF195 Line Regulation vs. VIN
REV. E
100
–6
0mA ⱕ IOUT < 25mA
0
75
TPC 5. Quiescent Current vs. Temperature
20
LINE REGULATION – ppm/mA
–25
VH
–25
0
25
50
TEMPERATURE – ⴗC
75
100
TPC 6. SLEEP Pin Current vs. Temperature
–15–
REF19x Series
VIN = 15V
0
2
REF19x
4
6
10mA
RIPPLE REJECTION – dB
1␮F
0
–20
TPC 9b. Load Transient Response Measurement Circuit
–40
–60
–80
2V
–100
100
90
–120
10
100
1k
10k
FREQUENCY – Hz
100k
1M
1mA
LOAD
TPC 7a. Ripple Rejection vs. Frequency
30mA
LOAD
10
0%
100␮s
2V
10␮F
1k⍀
2
VIN = +15V
REF19x
10␮F
OUTPUT
1␮F
4
TPC 10a. Power ON Response Time
10␮F
6
1k⍀
2
REF
4
VIN = 7V
TPC 7b. Ripple Rejection vs. Frequency
Measurement Circuit
6
REF19x
1␮F
TPC 10b. Power ON Response Time Measurement Circuit
VIN = 7V 2
REF19x
1␮F
6
4 1␮F
200V
VG = 2V p-p
Z
5V
VS = 4V
ON
100
90
OFF
4
ZO – ⍀
IL = 10mA
2
10
0%
1
0
IL = 1mA
VOUT
3
2ms
1V
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 11a. SLEEP Response Time
TPC 8. Output Impedance vs. Frequency
VIN = 15V
2
3
REF19x
VOUT
6
5V
OFF
ON
4
100
1␮F
90
TPC 11b. SLEEP Response Time Measurement Circuit
10
0%
20mV
100␮s
TPC 9a. Load Transient Response
–16–
REV. E
REF19x Series
35
LOAD CURRENT – mA
30
5V
100
90
25
20
15
10
5
10
0
0%
200mV
200␮s
0.2
0.3
0.4
0.5
0.6
0.7
REF195 DROPOUT VOLTAGE – V
0.8
0.9
Output Voltage Bypassing
+V
For stable operation, low dropout voltage regulators and references generally require a bypass capacitor connected from their
VOUT pins to their GND pins. Although the REF19x family of
references is capable of stable operation with capacitive loads
exceeding 100 µF, a 1 µF capacitor is sufficient to guarantee rated
performance. The addition of a 0.1 µF ceramic capacitor in parallel
with the bypass capacitor will improve load current transient
performance. For best line voltage transient performance, it is
recommended that the voltage inputs of these devices be bypassed
with a 10 µF electrolytic capacitor in parallel with a 0.1 µF
ceramic capacitor.
VOUT
SLEEP (SHUTDOWN)
Sleep Mode Operation
GND
Figure 1. Simplified Schematic
APPLICATIONS SECTION
Output Short Circuit Behavior
The REF19x family of devices is totally protected from damage
due to accidental output shorts to GND or to V+. In the event
of an accidental short circuit condition, the reference device will
shut down and limit its supply current to 40 mA.
The REF19x family of references is capable of delivering load
currents to 30 mA with an input voltage that ranges from 3.3 V
to 15 V. When these devices are used in applications with large
input voltages, care should be exercised to avoid exceeding
these devices’ maximum internal power dissipation. Exceeding
the published specifications for maximum power dissipation or
junction temperature could result in premature device failure.
The following formula should be used to calculate a device’s
maximum junction temperature or dissipation:
TJ – TA
PD =
θ JA
In this equation, TJ and TA are the junction and ambient temperatures, respectively, PD is the device power dissipation, and θJA is
the device package thermal resistance.
0.1
TPC 13. Dropout Voltage vs. Load Current
TPC 12. Line Transient Response
Device Power Dissipation Considerations
0
All REF19x devices include a sleep capability that is TTL/CMOS
level compatible. Internally, a pull-up current source to VIN is
connected at the SLEEP pin. This permits the SLEEP pin to be
driven from an open collector/drain driver. A logic LOW or a 0 V
condition on the SLEEP pin is required to turn the output stage
OFF. During sleep, the output of the references becomes a high
impedance state where its potential would then be determined
by external circuitry. If the sleep feature is not used, it is recommended that the SLEEP pin be connected to VIN (Pin 2).
Basic Voltage Reference Connections
The circuit in Figure 2 illustrates the basic configuration for the
REF19x family of references. Note the 10 µF/0.1 µF bypass network on the input and the 1 µF/0.1 µF bypass network on the
output. It is recommended that no connections be made to Pins 1,
5, 7, and 8. If the sleep feature is not required, Pin 3 should be
connected to VIN.
NC
VIN
10␮F
0.1␮F
8 NC
1
2
SLEEP 3
4
REF19x
7 NC
OUTPUT
6
5 NC
1␮F
TANT
0.1␮F
NC = NO CONNECT
Figure 2. Basic Voltage Reference Configuration
REV. E
–17–
REF19x Series
Membrane Switch Controlled Power Supply
With output load currents in the tens of mA, the REF19x family
of references can operate as a low dropout power supply in handheld instrument applications. In the circuit shown in Figure 3,
a membrane ON/OFF switch is used to control the operation of
the reference. During an initial power-on condition, the SLEEP
pin is held to GND by the 10 kΩ resistor. Recall that this condition
disables (read: three-state) the REF19x output. When the membrane ON switch is pressed, the SLEEP pin is momentarily pulled to
VIN, enabling the REF19x output. At this point, current through
the 10 kΩ is reduced and the internal current source connected
to the SLEEP pin takes control. Pin 3 assumes and remains at the
same potential as VIN. When the membrane OFF switch is pressed,
the SLEEP pin is momentarily connected to GND, which once
again disables the REF19x output.
8 NC
NC 1
VIN
7 NC
2
REF19x
1k⍀
5%
ON
OUTPUT
3
6
4
5 NC
1␮F
TANT
10k⍀
NC = NO CONNECT
Figure 3. Membrane Switch Controlled Power Supply
While the 30 mA rated output current of the REF19x series is
higher than typical of other reference ICs, it can be boosted to
higher levels if desired with the addition of a simple external
PNP transistor, as shown in Figure 4. Full time current limiting
is used for protection of the pass transistor against shorts.
Q1
TIP32A
(SEE TEXT)
Q2
2N3906
C2
100␮F/25V
D1
VC
1N4148
(SEE TEXT)
R2
1.5k⍀
U1
REF196
(SEE TABLE)
(SEE TEXT
ON SLEEP)
R3
1.82k⍀
VS
COMMON
OUTPUT TABLE
R1
1k⍀
C3
0.1␮F
F
U1
VOUT (V)
REF192
REF193
REF196
REF194
REF195
2.5
3.0
3.3
4.5
5.0
A Negative Precision Reference without Precision Resistors
+VOUT
3.3V
@ 150mA
S
C1
10␮F/25V
(TANTALUM)
R1
S
F
The requirement for a heat sink on Q1 depends on the maximum
input voltage and short circuit current. With VS = 5 V and a
300 mA current limit, the worst case dissipation of Q1 is 1.5 W,
less than the TO-220 package 2 W limit. However, if smaller
TO-39 or TO-5 packaged devices such as the 2N4033 are used,
the current limit should be reduced to keep maximum dissipation below the package rating. This is accomplished by simply
raising R4.
Shutdown control of the booster stage is shown as an option,
and when used some cautions are in order. Because of the additional active devices in the VS line to U1, direct drive to Pin 3
does not work as with an unbuffered REF19x device. To enable
shutdown control, the connection to U1-2 is broken at the “X,”
and diode D1 then allows a CMOS control source VC to drive
U1-3 for ON-OFF operation. Startup from shutdown is not as
clean under heavy load as it is in basic REF19x series and can
require several milliseconds under load. Nevertheless, it is still
effective and can fully control 150 mA loads. When shutdown
control is used, heavy capacitive loads should be minimized.
Current-Boosted References with Current Limiting
R4
2⍀
Because of the current limiting configuration, the dropout voltage
circuit is raised about 1.1 V over that of the REF19x devices, due
to the VBE of Q1 and the drop across current sense resistor R4.
However, overall dropout is typically still low enough to allow
operation of a 5 V to 3.3 V regulator/reference using the REF196
for U1 as noted, with a VS as low as 4.5 V and a load current
of 150 mA.
A tantalum output capacitor is used at C1 for its low ESR
(Equivalent Series Resistance), and the higher value is required
for stability. Capacitor C2 provides input bypassing and can be
an ordinary electrolytic.
OFF
+VS = 6V TO 9V
clamps drive to Q1 at about 300 mA of load current with values
as shown. With this separation of control and power functions,
dc stability is optimum, allowing best advantage use of premium
grade REF19x devices for U1. Of course, load management
should still be exercised. A short, heavy, low DCR (dc resistance)
conductor should be used from U1–6 to the VOUT sense point
“S,” where the collector of Q1 connects to the load, point “F.”
VOUT
COMMON
Figure 4. A Boosted 3.3 V Reference with Current Limiting
In this circuit, the power supply current of reference U1 flowing
through R1–R2 develops a base drive for Q1, whose collector
provides the bulk of the output current. With a typical gain of
100 in Q1 for 100 mA to 200 mA loads, U1 is never required to
furnish more than a few mA, so this factor minimizes temperature
related drift. Short circuit protection is provided by Q2, which
In many current-output CMOS DAC applications where the
output signal voltage must be of the same polarity as the reference
voltage, it is often required to reconfigure a current-switching DAC
into a voltage-switching DAC through the use of a 1.25 V reference,
an op amp, and a pair of resistors. Using a current-switching
DAC directly requires an additional operational amplifier at the
output to reinvert the signal. A negative voltage reference is then
desirable from the point that an additional operational amplifier
is not required for either reinversion (current-switching mode) or
amplification (voltage switching mode) of the DAC output voltage.
In general, any positive voltage reference can be converted into
a negative voltage reference through the use of an operational
amplifier and a pair of matched resistors in an inverting configuration. The disadvantage to that approach is that the largest single
source of error in the circuit is the relative matching of the
resistors used.
–18–
REV. E
REF19x Series
The circuit illustrated in Figure 5 avoids the need for tightly
matched resistors with the use of an active integrator circuit. In
this circuit, the output of the voltage reference provides the input
drive for the integrator. The integrator, to maintain circuit equilibrium, adjusts its output to establish the proper relationship
between the reference’s VOUT and GND. Thus, any desired
negative output voltage can be chosen by simply substituting for
the appropriate reference IC. The sleep feature is maintained in
the circuit with the simple addition of a PNP transistor and a
10 kΩ resistor. One caveat with this approach should be mentioned: although rail-to-rail output amplifiers work best in the
application, these operational amplifiers require a finite amount
(mV) of headroom when required to provide any load current.
The choice for the circuit’s negative supply should take this issue
into account.
VIN
SLEEP
TTL/CMOS
2N3906
2
1␮F
1k⍀
3 SLEEP VOUT 6
+5V
REF19x
GND
4
10k⍀
1␮F
100⍀
A1
While this concept is simple, some cautions are in order. Since
the lower reference circuit must sink a small bias current from
U2 (50 µA to 100 µA), plus the base current from the series PNP
output transistor in U2, either the external load of U1 or R1
must provide a path for this current. If the U1 minimum load is
not well defined, resistor R1 should be used, set to a value that
will conservatively pass 600 µA of current with the applicable
VOUT1 across it. Note that the two U1 and U2 reference circuits
are locally treated as macrocells, each having its own bypasses at
input and output for best stability. Both U1 and U2 in this circuit
can source dc currents up to their full rating. The minimum
input voltage, VS, is determined by the sum of the outputs, VOUT2,
plus the dropout voltage of U2.
A related variation on stacking two three-terminal references
is shown in Figure 6, where U1, a REF192, is stacked with a
two-terminal reference diode such as the AD589. Like the threeterminal stacked reference above, this circuit provides two outputs,
VOUT1 and VOUT2, which are the individual terminal voltages of
D1 and U1 respectively. Here this is 1.235 and 2.5, which provides a VOUT2 of 3.735 V. When using two-terminal reference
diodes such as D1, the rated minimum and maximum device
currents must be observed and the maximum load current from
VOUT1 can be no greater than the current set up by R1 and VO(U1).
In the case with VO(U1) equal to 2.5 V, R1 provides a 500 µA
bias to D1, so the maximum load current available at VOUT1 is
450 µA or less.
10k⍀
VIN
VOUT2 is the sum of this voltage and the terminal voltage of U2.
U1 and U2 are simply chosen for the two voltages that supply
the required outputs (see Table I). If, for example, both U1 and
U2 are REF192s, the two outputs are 2.5 V and 5.0 V.
–VREF
100k⍀
–5V
A1 = 1/2 OP295,
1/2 OP291
Figure 5. A Negative Precision Voltage Reference
Uses No Precision Resistors
Stacking Reference ICs for Arbitrary Outputs
+VS
VS > VOUT2 +0.15V
Some applications may require two reference voltage sources that
are a combined sum of standard outputs. The circuit of Figure 6
shows how this “stacked output” reference can be implemented.
C1
0.1␮F
U1
REF192
VO (U1)
C2
1␮F
+VOUT2
3.735V
R1
4.99k⍀
(SEE TEXT)
OUTPUT TABLE
U1/U2
+VS
VS > VOUT2 +0.15V
VOUT1 (V) VOUT2 (V)
REF192/REF192
REF192/REF194
REF192/REF195
C1
0.1␮F
2.5
2.5
2.5
U2
REF19x
(SEE TABLE)
5.0
7.0
7.5
D1
AD589
VIN
COMMON
+VOUT2
VO (U2)
C2
1␮F
VO (D1)
C3
1␮F
+VOUT1
1.235V
VOUT
COMMON
Figure 7. Stacking Voltage References with the REF19x
A Precision Current Source
C3
0.1␮F
U1
REF19x
+VOUT1
(SEE TABLE)
VO (U1)
VIN
COMMON
C4
1␮F
R1
3.9k⍀
(SEE TEXT)
VOUT
COMMON
Figure 6. Stacking Voltage References with the REF19x
Two reference ICs are used, fed from a common unregulated
input, VS. The outputs of the individual ICs are simply connected in series as shown, which provides two output voltages,
VOUT1 and VOUT2. VOUT1 is the terminal voltage of U1, while
REV. E
Many times, in low power applications, the need arises for a
precision current source that can operate on low supply voltages.
As shown in Figure 8, any one of the devices in the REF19x
family of references can be configured as a precision current
source. The circuit configuration illustrated is a floating current
source with a grounded load. The reference’s output voltage is
bootstrapped across RSET, which sets the output current into the
load. With this configuration, circuit precision is maintained for
load currents in the range from the reference’s supply current
(typically, 30 µA) to approximately 30 mA. The low dropout
voltage of these devices maximizes the current source’s output
voltage compliance without excess headroom.
–19–
REF19x Series
VIN
OUTPUT TABLE
VIN
+VS = 6V
REF19x
SLEEP
VREF
GND
1␮F
ISY
ADJUST
R1
VC
RSET
1
2
3
4
U1
REF19x
U1/U2
VC* VOUT (V)
REF195/
REF196
REF194/
REF195
HI
LO
HI
LO
5.0
3.3
4.5
5.0
*CMOS LOGIC LEVELS
(SEE TABLE)
P1
U3A
74HC04
IOUT
I OUT ⴛ RL (MAX) + VSY (MIN)
RL
V
IOUT = OUT + ISY (REF19x)
RSET
VOUT
E.G. REF195 : VOUT = 5V
>> ISY
IOUT = 5mA
RSET
R1 = 953⍀
P1 = 100⍀, 10-TURN
U3B
74HC04
+VOUT
VIN
U2
REF19x
(SEE TABLE)
C1
0.1␮F
VIN
COMMON
Figure 8. A Low Dropout, Precision Current Source
The circuit’s governing equations are:
V IN = IOUT × RL (max)+V SY (min, REF19x)
V OUT
+ I SY (REF19x)
IOUT =
RSET
V OUT
〉〉I (REF19x)
RSET SY
C2
1␮F
VOUT
COMMON
Figure 9. Switched Output Reference
Applications often require digital control of reference voltages,
selecting between one stable voltage and a second. With the
sleep feature inherent to the REF19x series, switched output
reference configurations are easily implemented with relatively
little additional hardware.
Using dissimilar REF19x series devices with this configuration
allows logic selection between the U1/U2 specified terminal
voltages. For example, with U1 (a REF195) and U2 (a REF196),
as noted in the table, changing the CMOS compatible VC logic
control voltage from HI to LO selects between a nominal output
of 5.000 V and 3.300 V and vice versa. Other REF19x family
units can also be used for U1/U2, with similar operation in a
logic sense, but with outputs as per the individual paired devices
(see table, again). Of course, the exact output voltage tolerance,
drift, and overall quality of the reference voltage will be consistent
with the grade of individual U1 and U2 devices.
The circuit of Figure 9 illustrates the general technique, which
takes advantage of the output “wire-OR” capability of the REF19x
device family. When OFF, a REF19x device is effectively an
open circuit at the output node with respect to the power supply.
When ON, a REF19x device can source current up to its current
rating, but sink only a few µA (essentially just the relatively low
current of the internal output scaling divider). As a result, for
two devices wired together at their common outputs, the output
voltage is simply that of the ON device. The OFF state device
will draw a small standby current of 15 µA (max), but otherwise
will not interfere with operation of the ON device, which can
operate to its full current rating. Note that the two devices in
the circuit conveniently share both input and output capacitors,
and with CMOS logic drive, it is power efficient.
Because of the nature of the wire–OR, there is one application
caveat that should be understood about this circuit. Since U1
and U2 can only source current effectively, negative going output
voltage changes, which require the sinking of current, will necessarily take longer than positive going changes. In practice, this
means that the circuit is quite fast when undergoing a transition
from 3.3 V to 5 V, but the transition from 5 V to 3.3 V will take
longer. Exactly how much longer will be a function of the load
resistance, RL, seen at the output and the typical 1 µF value of
C2. In general, a conservative transition time here will be on the
order of several milliseconds for load resistances in the range of
100 Ω to 1 kΩ. Note that for highest accuracy at the new output
voltage, several time constants should be allowed (>7.6 time
constants for <1/2 LSB error @ 10 bits, for example).
Switched Output 5 V/3.3 V Reference
–20–
REV. E
REF19x Series
Kelvin Connections
A Fail-Safe 5 V Reference
In many portable instrumentation applications where PC board
cost and area go hand-in-hand, circuit interconnects are very
often of dimensionally minimum width. These narrow lines
can cause large voltage drops if the voltage reference is required
to provide load currents to various functions. In fact, a circuit’s interconnects can exhibit a typical line resistance of
0.45 mΩ/square (1 oz. Cu, for example). In those applications
where these devices are configured as low dropout voltage regulators, these wiring voltage drops can become a large source of
error. To circumvent this problem, force and sense connections
can be made to the reference through the use of an operational
amplifier, as shown in Figure 10. This method provides a means
by which the effects of wiring resistance voltage drops can be
eliminated. Load currents flowing through wiring resistance
produce an I-R error (ILOAD ⫻ RWIRE) at the load. However, the
Kelvin connection overcomes the problem by including the
wiring resistance within the forcing loop of the op amp. Since the
op amp senses the load voltage, op amp loop control forces the
output to compensate for the wiring error and to produce the
correct voltage at the load. Depending on the reference device
chosen, operational amplifiers that can be used in this application
are the OP295, the OP291, and the OP183/OP283.
Some critical applications require a reference voltage to be maintained constant, even with a loss of primary power. The low standby
power of the REF19x series and the switched output capability
allow a “fail-safe” reference configuration to be implemented
rather easily. This reference maintains a tight output voltage
tolerance for either a primary power source (ac line derived) or
a standby (battery derived) power source, automatically switching
between the two as the power conditions change.
VIN
VIN
RLW
VIN
2
REF19x
SLEEP
VOUT
GND
3
1␮F
1
A1
+VOUT
SENSE
RLW
+VOUT
FORCE
RL
100k⍀
A1 = 1/2 OP295
1/2 OP292
1/2 OP283
Figure 10. A Low Dropout, Kelvin Connected
Voltage Reference
The circuit in Figure 11 illustrates the concept, which borrows
from the switched output idea of Figure 8, again using the REF19x
device family output “wire-OR” capability. In this case, since a
constant 5 V reference voltage is desired for all conditions, two
REF195 devices are used for U1 and U2, with their ON/OFF
switching controlled by the presence or absence of the primary
dc supply source, VS. VBAT is a 6 V battery backup source that supplies power to the load only when VS fails. For normal (VS present)
power conditions, VBAT sees only the 15 µA (max) standby current
drain of U1 in its OFF state.
In operation, it is assumed that for all conditions either U1 or U2
is ON and a 5 V reference output is available. With this voltage
constant, a scaled down version is applied to the comparator IC
U3, providing a fixed 0.5 V input to the (–) input for all power
conditions. The R1–R2 divider provides a signal to the U3 (+)
input proportional to VS, which switches U3 and U1/U2 dependent
upon the absolute level of VS. Op amp U3 is configured here as
a comparator with hysteresis, which provides for clean, noise free
output switching. This hysteresis is important to eliminate rapid
switching at the threshold due to VS ripple. Further, the device
chosen is the AD820, a rail-to-rail output device that provides
HI and LO output states within a few mV of VS and ground for
accurate thresholds and compatible drive for U2 for all VS conditions. R3 provides positive feedback for circuit hysteresis, changing
the threshold at the (+) input as a function of U3’s output.
+VBAT
C2
0.1␮F
+VS
R1
1.1M⍀
R3
10M⍀
R6
100⍀
3
U1
REF195
Q1
2N3904
7
5.000V
C1
0.1␮F
6
2
R2
100k⍀
VS, VBAT
COMMON
C4
0.1␮F
U3
4 AD820
U2
REF195
R4
900k⍀
R5
100k⍀
VOUT
COMMON
Figure 11. A Fail-Safe 5 V Reference
REV. E
C3
1␮F
–21–
REF19x Series
For VS levels lower than the LOWER threshold, U3’s output is
low, thus U2 and Q1 are OFF, while U1 is ON. For VS levels
higher than the UPPER threshold, the situation reverses, with
U1 OFF and both U2 and Q1 ON. In the interest of battery
power conservation, all of the comparison switching circuitry
is powered from VS and is arranged so that when VS fails, the
default output comes from U1.
100⍀
10␮F
REF195
1␮F
10␮F
57k⍀
1%
For the R1–R3 values as shown, the LOWER/UPPER VS switching
thresholds are approximately 5.5 V and 6 V, respectively. These
can obviously be changed to suit other VS supplies, as can the
REF19x devices used for U1 and U2, over a range of 2.5 V to
5 V of output. U3 can operate down to a VS of 3.3 V, which is
generally compatible with all family devices.
0.1␮F
0.1␮F
1/4
OP492
10k⍀
1%
2N2222
500⍀
0.1%
A Low Power, Strain Gage Circuit
As shown in Figure 12, the REF19x family of references can be
used in conjunction with low supply voltage operational amplifiers, such as the OP492 and the OP283, in a self-contained strain
gage circuit. In this circuit, the REF195 was used as the core of
this low power, strain gage circuit. Other references can be easily
accommodated by changing circuit element values. The references
play a dual role as the voltage regulator to provide the supply
voltage requirements of the strain gage and the operational
amplifiers as well as a precision voltage reference for the current
source used to stimulate the bridge. A distinct feature of the
circuit is that it can be remotely controlled ON or OFF by digital
means via the SLEEP pin.
0.01␮F
10k⍀
1%
20k⍀
1%
1/4
OP492
2.21k⍀
20k⍀
1%
1/4
OP492
10k⍀
1%
1/4
OP492
OUTPUT
20k⍀
1%
20k⍀
1%
Figure 12. A Low Power, Strain Gage Circuit
–22–
REV. E
REF19x Series
OUTLINE DIMENSIONS
8-Lead Plastic DIP (P Suffix)
(N-8)
Dimensions shown in inches and (millimeters)
0.430 (10.92)
0.348 (8.84)
8
5
1
0.280 (7.11)
0.240 (6.10)
4
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
0.160 (4.06)
MIN
0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77) SEATING
PLANE
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
0.015 (0.381)
0.008 (0.204)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Narrow Body SOIC (S Suffix)
(SOIC-8)
Dimensions shown in inches and (millimeters)
0.1968 (5.00)
0.1890 (4.80)
8
5
0.1574 (4.00)
0.1497 (3.80) 1
PIN 1
0.0098 (0.25)
0.0040 (0.10)
4
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
x 45
0.0099 (0.25)
0.0500 0.0192 (0.49)
SEATING (1.27)
0.0098 (0.25)
PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
8
0
0.0500 (1.27)
0.0160 (0.41)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead TSSOP (RU Suffix)
(RU-8)
Dimensions shown in inches and (millimeters)
8
5
1
4
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
0.122 (3.10)
0.114 (2.90)
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0256 (0.65)
BSC
0.0118 (0.30)
SEATING
PLANE 0.0075 (0.19)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
8
0
0.028 (0.70)
0.020 (0.50)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. E
–23–
REF19x Series
Revision History
Location
Page
1/03—Data Sheet changed from REV. D to REV. E.
Changes to Output Short Circuit Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PRINTED IN U.S.A.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
C00371–0–1/03(E)
Changes to TPCs 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–24–
REV. E