Final Electrical Specifications
LTC1668
16-Bit, 50Msps DAC
February 2000
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FEATURES
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DESCRIPTIO
The LTC®1668 is a 16-bit, 50Msps differential current
output DAC implemented on a high performance BiCMOS
process with laser trimmed, thin-film resistors. The combination of a novel current-steering architecture and a
high performance process produces a DAC with exceptional AC and DC performance. This is the first 16-bit DAC
in the marketplace to exhibit an SFDR (spurious free
dynamic range) of 87dB for an output signal frequency of
1MHz.
50Msps Update Rate
16-Bit Resolution
High Spectral Purity: 87dB SFDR at 1MHz fOUT
Differential Current Outputs
30ns Settling Time
5pV-s Glitch Impulse
Low Power: 180mW from ±5V Supplies
TTL/CMOS (3.3V or 5V) Inputs
Small Package: 28-Pin SSOP
Operating from ±5V supplies, the LTC1668 can be configured to provide full-scale output currents up to 10mA.
The differential current outputs of the DAC allow singleended or true differential operation. The –1V to 1V output
compliance of the LTC1668 allows the outputs to be connected directly to external resistors to produce a differential output voltage without degrading the converter’s
linearity. Alternatively, the outputs can be connected to the
summing junction of a high speed operational amplifier,
or to a transformer.
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APPLICATIO S
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Cellular Base Stations
Multicarrier Base Stations
Wireless Communication
Direct Digital Synthesis (DDS)
xDSL Modems
Arbitrary Waveform Generation
Automated Test Equipment
Instrumentation
The LTC1668 is available in a 28-pin SSOP and is fully
specified over the industrial temperature range.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
16-Bit, 50Msps DAC
5V
0.1µF
0.1µF
VDD
2.5V
REFERENCE
LTC1668
–15
IREFIN
52.3Ω
IOUT A
+
16-BIT
HIGH SPEED
DAC
–
52.3Ω
IOUT B
COMP1
C1
0.1µF
LADCOM
COMP2
+
VOUT 1VP-P
DIFFERENTIAL
–
SIGNAL AMPLITUDE (dBm)
REFOUT
RSET
2k
Single Tone SFDR
–5
–25
–35
fCLOCK = 25Msps
fOUT = 1.007MHz
AMPLITUDE = 0dBFS
= –8.5dBm
SFDR = 86dBc
–45
–55
–65
–75
–85
–95
C2
0.1µF
VSS
AGND DGND
CLK
DB15
DB0
1668 TA01
0.1µF
–105
0.05
CLOCK 16-BIT DATA
INPUT
INPUT
6.3
FREQUENCY (1.25MHz/DIV)
12.55
1668 G01
– 5V
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1668
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage (VDD) ................................................ 6V
Negative Supply Voltage (VSS) ............................... – 6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Digital Input Voltage .................... – 0.3V to (VDD + 0.3V)
Analog Output Voltage
(IOUT A and IOUT B) ........ (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1668C .............................................. 0°C to 70°C
LTC1668I ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
ORDER PART
NUMBER
DB13
1
28 DB14
DB12
2
27 DB15 (MSB)
DB11
3
26 CLK
DB10
4
25 VDD
DB9
5
24 DGND
DB8
6
23 VSS
DB7
7
22 COMP2
DB6
8
21 COMP1
DB5
9
20 IOUT A
DB4 10
19 IOUT B
DB3 11
18 LADCOM
DB2 12
17 AGND
DB1 13
16 IREFIN
DB0 (LSB) 14
LTC1668CG
LTC1668IG
15 REFOUT
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 100°C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = – 5V, LADCOM = AGND = DGND = 0V, IOUTFS = 10mA.
SYMBOL
PARAMETER
CONDITIONS
DC Accuracy (Measured at IOUTA, Driving a Virtual Ground)
Resolution
Monotonicity
INL
Integral Nonlinearity
DNL
Differential Nonlinearity
Offset Error
Offset Error Drift
GE
Gain Error
Internal Reference, RIREFIN = 2k
External Reference, VREF = 2.5V, RIREFIN = 2k
Gain Error Drift
Internal Reference
External Reference
PSRR
Power Supply Rejection Ratio
VDD = 5V ±5%
VSS = –5V ±5%
Analog Output
IOUTFS
Full-Scale Output Current
Output Compliance Range
IFS = 10mA
Output Resistance; RIOUTA, RIOUTB
IOUTA, B to LADCOM
Output Capacitance
Reference Output
Reference Voltage
REFOUT Tied to IREFIN Through 2kΩ
Reference Output Drift
Reference Output Load Regulation
2
ILOAD = 0mA to 5mA
MIN
TYP
MAX
16
14
±1
0.1
5
±8
±4
±0.2
2
1
75
50
±0.1
±0.1
●
●
●
1
–1
0.7
2.475
1.1
5
2.5
25
6
10
1
1.5
2.525
UNITS
Bits
Bits
LSB
LSB
% FSR
ppm/°C
% FSR
% FSR
ppm/°C
ppm/°C
% FSR/V
% FSR/V
mA
V
kΩ
pF
V
ppm/°C
mV/mA
LTC1668
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = – 5V, LADCOM = AGND = DGND = 0V, IOUTFS = 10mA.
SYMBOL
PARAMETER
Reference Input
Reference Small-Signal Bandwidth
CONDITIONS
MIN
IFS = 10mA, CCOMP1 = 0.1µF
TYP
MAX
20
UNITS
kHz
Power Supply
VDD
VSS
Positive Supply Voltage
Negative Supply Voltage
5
–5
5.25
– 5.25
IDD
ISS
Positive Supply Current
Negative Supply Current
IFS = 10mA, fCLK = 25Msps, fOUT = 1MHz
IFS = 10mA, fCLK = 25Msps, fOUT = 1MHz
●
●
3
33
5
40
PDIS
Power Dissipation
IFS = 10mA, fCLK = 25Msps, fOUT = 1MHz
IFS = 1mA, fCLK = 25Msps, fOUT = 1MHz
●
●
180
85
mW
mW
Dynamic Performance (Differential Transformer Coupled Output, 50Ω Double Terminated, Unless Otherwise Noted)
fCLOCK
Maximum Update Rate
●
50
75
Msps
tS
tPD
●
●
V
V
mA
mA
Output Settling Time
Output Propagation Delay
To 0.1% FSR
30
8
ns
ns
Glitch Impulse
Single Ended
Differential
15
5
pV-s
pV-s
4
4
ns
ns
50
30
pA/√Hz
pA/√Hz
87
87
86
80
dB
dB
dB
dB
fCLK = 50Msps, fOUT = 1MHz
fCLK = 50Msps, fOUT = 2.5MHz
84
80
dB
dB
fCLK = 50Msps, fOUT = 5MHz
fCLK = 50Msps, fOUT = 20MHz
77
65
dB
dB
96
88
dB
dB
tr
tf
Output Rise Time
Output Fall Time
iNO
Output Noise
IFS = 10mA
IFS = 1mA
Spurious Free Dynamic Range
to Nyquist
fCLK = 25Msps, fOUT = 1MHz
0dB FS Output
– 6dB FS Output
–12dB FS Output
–18dB FS Output
AC Linearity
SFDR
4.75
– 4.75
Spurious Free Dynamic Range
Within a Window
fCLK = 25Msps, fOUT = 1MHz, 2MHz Span
fCLK = 50Msps, fOUT = 5MHz, 4MHz Span
THD
Total Harmonic Distortion
fCLK = 25Msps, fOUT = 1MHz
fCLK = 50Msps, fOUT = 5MHz
Digital Inputs
VIH
VIL
IIN
CIN
tDS
tDH
tCLKH
tCLKL
Digital High Input Voltage
Digital Low Input Voltage
Digital Input Current
Digital Input Capacitance
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
78
86
–84
–76
●
2.4
0.8
±10
●
●
5
●
●
●
●
–77
8
4
5
8
dB
dB
V
V
µA
pF
ns
ns
ns
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
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LTC1668
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TYPICAL PERFOR A CE CHARACTERISTICS
Single Tone SFDR
fCLOCK = 25Msps
fOUT = 1.007MHz
AMPLITUDE = 0dBFS
= –8.5dBm
SFDR = 86dBc
–15
SIGNAL AMPLITUDE (dBm)
2-Tone SFDR
–25
–35
–45
–55
–65
–75
–85
–10
fCLOCK = 50Msps
fOUT1 =
4.028MHz
fOUT2 =
4.419MHz
AMPLITUDE 1, 2
= –6dBFS
= –14.5dBm
SFDR > 77dBc
–20
SIGNAL AMPLITUDE (dBm)
–5
–30
–40
–50
–60
–70
–80
–90
–100
–95
–105
0.05
6.3
FREQUENCY (1.25MHz/DIV)
–110
3.2
12.55
4.2
FREQUENCY (0.2MHz/DIV)
1668 G02
1668 G01
Integral Nonlinearity
Differential Nonlinearity
5
2.0
DIFFERENTIAL NONLINEARITY (LSB)
4
INTEGRAL NONLINEARITY (LSB)
5.2
3
2
1
0
–1
–2
–3
–4
–5
49152
32768
16384
DIGITAL INPUT CODE
65535
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
32768
16384
49152
DIGITAL INPUT CODE
1668 G03
65535
1668 G04
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PI FU CTIO S
REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1µF bypass capacitor
to AGND.
IREFIN (Pin 16): Reference Input Current. Nominal value is
1.25mA for IFS = 10mA. IFS = IREFIN • 8.
AGND (Pin 17): Analog Ground.
COMP1 (Pin 21): Current Source Control Amplifier Compensation. Bypass to VSS with 0.1µF.
COMP2 (Pin 22): Internal Bypass Point. Bypass to VSS
with 0.1µF.
VSS (Pin 23): Negative Supply Voltage. Nominal value is
– 5V.
LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.
DGND (Pin 24): Digital Ground.
IOUT B (Pin 19): Complementary DAC Output Current. Fullscale output current occurs when all data bits are 0s.
CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.
IOUT A (Pin 20): DAC Output Current. Full-scale output
current occurs when all data bits are 1s.
DB15 to DB0 (Pins 27, 28, 1 to 14): Digital Input Data Bits.
4
VDD (Pin 25): Positive Supply Voltage. Nominal value is 5V.
LTC1668
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BLOCK DIAGRA
5V
0.1µF
25
LTC1668
VREF
15
REFOUT
2.5V
REFERENCE
0.1µF
IFS/8
+
IINT
22
0.1µF
20
+
IOUT B
19
–
52.3Ω
52.3Ω
VOUT
1VP-P
DIFFERENTIAL
CURRENT SOURCE ARRAY
–
21
IOUT A
SEGMENTED SWITCHES
FOR DB15–DB12
LSB SWITCHES
IREFIN
18
ATTENUATOR
LADDER
RSET
2k
16
LADCOM
•••
•••
COMP1
INPUT LATCHES
COMP2
0.1µF
VSS
23
–5V
AGND
DGND
17
24
0.1µF
CLK
DB15
26
•••
27
CLOCK
INPUT
DB0
14
1668 BD
16-BIT
DATA INPUT
WU
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TI I G DIAGRA
DB0
TO DB15
N–1
N
tDS
N+1
tDH
CLK
tCLKL
tCLKH
tPD
IOUT A/IOUT B
N–1
tST
N
0.1%
1668 TD
5
LTC1668
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APPLICATIO S I FOR ATIO
Theory of Operation
The LTC1668 is a high speed current steering 16-Bit DAC
made on an advanced BiCMOS process. Precision thin
film resistors and well matched bipolar transistors result
in excellent DC linearity and stability. A low glitch current
switching design gives excellent AC performance at sample
rates up to 50Msps. The device is complete with a 2.5V
internal bandgap reference and edge triggered latches,
and sets a new standard for DAC applications requiring
very high dynamic range at output frequencies up to
several megahertz.
Referring to the Block Diagram, the DAC contains an array
of current sources that are steered to IOUTA or IOUTB with
NMOS differential current switches. The four most significant bits, DB15 to DB12 are made up of 15 current
segments of equal weight. The lower bits, DB11 to DB0 are
binary weighted, using a combination of current scaling
and a differential resistive attenuator ladder. All bits and
segments are precisely matched, both in current weight
for DC linearity, and in switch timing for low glitch impulse
and low spurious tone AC performance.
Setting the Full-Scale Current, IOUTFS
The full-scale DAC output current, IOUTFS, is nominally
10mA, and can be adjusted down to 1mA. Placing a
resistor, RSET, between the REFOUT pin, and the IREFIN pin
sets IOUTFS as follows.
The internal reference control loop amplifier maintains a
virtual ground at IREFIN by servoing the internal current
source, IINT, to sink the exact current flowing into IREFIN.
IINT is a scaled replica of the DAC current sources and
IOUTFS = 8 • (IINT), therefore:
IOUTFS = 8 • (IREFIN) = 8 • (VREF/RSET)
For fixed reference voltage applications, CCOMP1 should
be 0.1µF or more. The reference control loop small-signal
bandwidth is approximately 1/(2π) • CCOMP1 • 80 or 20kHz
for CCOMP1 = 0.1µF.
Internal Reference Output—REFOUT
The onboard 2.5V bandgap voltage reference drives the
REFOUT pin. It is trimmed and specified to drive a 2k
resistor tied from REFOUT to IREFIN, corresponding to a
1.25mA load (IOUTFS = 10mA). REFOUT has nominal
output impedance of 6Ω, or 0.24% per mA, so it must be
buffered to drive any additional external load. A 0.1µF
capacitor is required on the REFOUT pin for compensation. Note that this capacitor is required for stability, even
if the internal reference is not being used.
DAC Transfer Function
The LTC1668 uses straight binary digital coding. The
complementary current outputs, IOUT A and IOUT B, sink
current from 0 to IOUTFS. For IOUTFS = 10mA (nominal),
IOUT A swings from 0mA when all bits are low (i.e., Code =
0) to 10mA when all bits are high (i.e., Code = 65535) (decimal representation). IOUT B is complementary to IOUT A.
IOUT A and IOUT B are given by the following formulas:
IOUT A = IOUTFS • (DAC Code/65536)
(2)
IOUT B = IOUTFS • (65535-DAC Code)/65536
(3)
In typical applications, the LTC1668 differential output
currents either drive a resistive load directly or drive an
equivalent resistive load through a transformer, or as the
feedback resistor of an I-to-V converter. The voltage
outputs generated by the IOUT A and IOUT B output currents
are then:
(1)
VOUT A = IOUT A • RLOAD
(4)
For example, if RSET = 2k and is tied to VREF = REFOUT =
2.5V, IREFIN = 2.5/2k = 1.25mA and IOUTFS = 8 • (1.25mA)
= 10mA.
VOUT B = IOUT B • RLOAD
(5)
The reference control loop requires a capacitor on the
COMP1 pin for compensation. For optimal AC performance, CCOMP1 should be connected to VSS and be placed
very close to the package (less than 0.1").
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The differential voltage is:
VDIFF = VOUT A – VOUT B
= (IOUT A – IOUT B) • (RLOAD)
(6)
LTC1668
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APPLICATIO S I FOR ATIO
Substituting the values found earlier for IOUT A, IOUT B and
IOUTFS:
VDIFF = {2 • DAC Code – 65535)/65536} • 8 •
(RLOAD/RSET) • (VREF)
LADCOM
LTC1668
RIOUT B
1.1k
(7)
From these equations some of the advantages of differential mode operation can be seen. First, any common mode
noise or error on IOUT A and IOUT B is cancelled. Second, the
signal power is twice as large as in the single-ended case.
Third, any errors and noise that multiply times IOUT A and
IOUT B, such as reference or IOUTFS noise, cancel near
midscale, where AC signal waveforms tend to spend the
most time. Fourth, this transfer function is bipolar; e.g. the
output swings positive and negative around a zero output
at mid-scale input, which is more convenient for AC
applications.
Note that the term (RLOAD/RSET) appears in both the
differential and single-ended transfer functions. This means
that the Gain Error of the DAC depends on the ratio of
RLOAD to RSET, and the Gain Error tempco is affected by the
temperature tracking of RLOAD with RSET. Note also that
the absolute tempco of RLOAD is very critical for DC
nonlinearity. As the DAC output changes from 0mA to
10mA the RLOAD resistor will heat up slightly, and even a
very low tempco can produce enough INL bowing to be
significant at the 16-bit level. This effect disappears with
medium to high frequency AC signals due to the slow
thermal time constant of the load resistor.
Analog Outputs
The LTC1668 has two complementary current outputs,
IOUT A and IOUT B (see DAC Transfer Function). The output
impedance of IOUT A and IOUT B (RIOUT A and RIOUT B) is
typically 1.1kΩ to LADCOM. (See the Equivalent Analog
Output Circuit, Figure 1.) The LADCOM pin is the common connection for the internal DAC attenuator ladder. It
usually is tied to analog ground, but more generally it
should connect to the same potential as the lead resistors
on IOUT A and IOUT B. The LADCOM pin carries a constant
current to VSS of approximately 0.32 • (IOUTFS), plus any
current that flows from IOUT A and IOUT B through the
RIOUT A and RIOUT B resistors.
RIOUT A
1.1k
IOUT A
IOUT B
18
20
52.3Ω
19
52.3Ω
5pF
5pF
VSS
– 5V
23
1668 F01
Figure 1. Equivalent Analog Output Circuit
The specified output compliance voltage range is ±1V. The
DC linearity specifications, INL and DNL, are trimmed and
guaranteed on IOUT A into the virtual ground of an
I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linearity. Below – 1V, the DAC switches will start to approach the
transition from saturation to linear region. This will degrade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than ±0.5VP-P on IOUT A and
IOUT B due to nonlinear capacitance and other large-signal
effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC performance generally behave as additive currents, so decreasing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.
The LTC1668 is specified to operate with full-scale output
current, IOUTFS, from the nominal 10mA down to 1mA.
This can be useful to reduce power dissipation or to adjust
full-scale value. However, that the LTC1668 DC and AC
accuracy is specified only at IOUTFS = 10mA, and DC and
AC accuracy will fall off significantly at lower IOUTFS values.
At IOUTFS = 1mA, INL and DNL typically degrade to the 14bit to 13-bit level, compared to 16-bit to 15-bit typical
accuracy at 10mA IOUTFS. Increasing IOUTFS from 1mA, the
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LTC1668
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APPLICATIO S I FOR ATIO
accuracy improves rapidly, roughly in proportion to
1/IOUTFS. The AC performance tends to be less affected by
reducing IOUTFS, except for the unavoidable affects on
SFDR and THD due to increased INL and DNL.
Output Configurations
IOUTFS noise is gone at zero scale and is fully present at full
scale. In differential mode, IOUTFS noise is cancelled at
midscale input, corresponding to zero analog output.
Many AC signals, including broadband and multitone
communications signals with high peak to average ratios,
stay mostly near midscale.
Based on the specific application requirements, the
LTC1668 allows a choice of the best of several output
configurations. Voltage outputs can be generated by external load resistors, transformer coupling or with an op
amp I-to-V converter. Single-ended DAC output configurations use only one of the outputs, preferably IOUT A, to
produce a single-ended voltage output. Differential mode
configurations use the difference between IOUT A and
IOUT B to generate an output voltage, VDIFF, as shown in
equation 7. Differential mode gives much better accuracy
in most AC applications. Because the DAC chip is the point
of interface between the digital input signals and the
analog output, some small amount of noise coupling to
IOUT A and IOUT B is unavoidable. Most of that digital noise
is common mode and is canceled by the differential mode
circuit. Other significant digital noise components can be
modeled as VREF or IOUTFS noise. In single-ended mode,
Differential transformer-coupled output configurations
usually give the best AC performance. An example is the
AC Characterization Setup circuit, Figure 2. The advantages of transformer coupling include excellent rejection
of common mode distortion and noise over a broad
frequency range and convenient differential-to-singleended conversion with isolation or level shifting. Also, as
much as twice the power can be delivered to the load, and
impedance matching can be accomplished by selecting
the appropriate transformer turns ratio. The center tap on
the primary side of the transformer is tied to ground to
provide the DC current path for IOUT A and IOUT B. For low
distortion, the DC average of the IOUT A and IOUT B currents
must be exactly equal to avoid biasing the core. This is
especially important for compact RF transformers with
small cores. The circuit in Figure 2 uses a Mini-Circuits
T1-1T RF transformer with a 1:1 turns ratio. The load
5V
0.1µF
REFOUT
0.1µF
RSET
2k
2.5V
REFERENCE
VDD
LTC1668
MINI-CIRCUITS
T1–1T
IREFIN
IOUT A
+
16-BIT
HIGH SPEED
DAC
–
110Ω
IOUT B
COMP1
C1
0.1µF
50Ω
LADCOM
COMP2
C2
0.1µF
AGND DGND
VSS
CLK
DB15
DB0
16
0.1µF
DIGITAL
DATA
– 5V
OUT 1 OUT 2
CLK HP8110A DUAL
IN PULSE GENERATOR
HP1663EA
CLK
LOGIC ANALYZER WITH
IN
PATTERN GENERATOR
1668 F02
LOW JITTER
CLOCK SOURCE
Figure 2. AC Characterization Setup
8
50Ω
TO HP3589A
SPECTRUM
ANALYZER
50Ω INPUT
LTC1668
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APPLICATIO S I FOR ATIO
resistance on IOUT A and IOUT B is equivalent to a single
differential resistor of 50Ω, and the 1:1 turns ratio means
the output impedance from the transformer is 50Ω. Note
that the load resistors are optional, and they dissipate half
of the output power. However, in lab environments or
when driving long transmission lines it is very desirable to
have a 50Ω output impedance. This could also be done
with a 50Ω resistor at the transformer secondary, but
putting the load resistors on IOUT A and IOUT B is preferred
since it reduces the current through the transformer. At
signal frequencies lower than about 1MHz, the transformer core size required to maintain low distortion gets
larger, and at some lower frequencies this becomes
impractical.
A differential resistor loaded output configuration is shown
in the Block Diagram. It is simple and economical, but it
can drive only differential loads with impedance levels and
amplitudes appropriate for the DAC outputs.
The recommended single-ended resistor loaded configuration is essentially the same circuit as the differential
resistor loaded, case—simply use the IOUT A output,
referred to ground. Rather than tying the unused IOUT B
output to ground, it is preferred to load it with the equivalent RLOAD of IOUT A. Then IOUT B will still swing with a
waveform complementary to IOUT A.
Adding an op amp differential to single-ended converter
circuit to the differential resistor loaded output gives the
circuit of Figure 10.
This circuit complements the capabilities of the transformer-coupled application at lower frequencies, since
available op amps can deliver good AC distortion performance at signal frequencies of a few MHz down to DC. The
optional capacitor adds a single real pole of filtering, and
helps reduce distortion by limiting the high frequency
signal amplitude at the op amp inputs. The circuit swings
±1V around ground.
Figure 3 shows a simplified circuit for a single-ended
output using I-to-V converter to produce a unipolar
buffered voltage output. This configuration typically has
the best DC linearity performance, but its AC distortion at
higher frequencies is limited by U1’s slewing capabilities.
COUT
RFB
200Ω
IOUTFS
10mA
IOUT A
U1
LT®1812
LTC1668
+
IOUT B
LADCOM
–
VOUT
0V TO 2V
200Ω
1668 F03
Figure 3. Unipolar Buffered Voltage Output
Digital Interface
The LTC1668 has 16 parallel inputs that are latched on the
rising edge of the clock input. They accept CMOS levels
from either 5V or 3.3V logic and can accept clock rates of
up to 50MHz.
Referring to the Timing Diagram and Block Diagram, the
data inputs go to master-slave latches that update on the
rising edge of the clock. The input logic thresholds, VIH =
2.4V min, VIL = 0.8V max, work with 3.3V or 5V CMOS
levels over temperature. The guaranteed setup time, tDS,
is 8ns minimum and the hold time, tDH, is 4ns minimum.
The minimum clock high and low times are guaranteed at
6ns and 8ns, respectively. These specifications allow the
LTC1668 to be clocked at up to 50Msps minimum.
For best AC performance, the data and clock waveforms
need to be clean and free of undershoot and overshoot.
Clock and data interconnect lines should be twisted pair,
coax or microstrip, and proper line termination is important. If the digital input signals to the DAC are considered
as analog AC voltage signals, they are rich in spectral
components over a broad frequency range, usually including the output signal band of interest. Therefore, any
direct coupling of the digital signals to the analog output
will produce spurious tones that vary with the exact digital
input pattern.
Clock jitter should be minimized to avoid degrading the
noise floor of the device in AC applications, especially
where high output frequencies are being generated. Any
noise coupling from the digital inputs to the clock input will
9
LTC1668
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APPLICATIO S I FOR ATIO
cause phase modulation of the clock signal and the DAC
waveform, and can produce spurious tones. It is normally
best to place the digital data transitions near the falling
clock edge, well away from the active rising clock edge.
Because the clock signal contains spectral components
only at the sampling frequency and its multiples, it is
usually not a source of in band spurious tones. Overall, it
is better to treat the clock as you would an analog signal
and route it separately from the digital data input signals.
The clock trace should be routed either over the analog
ground plane or over its own section of the ground plane.
The clock line needs to have accurately controlled impedance and should be well terminated near the LTC1668.
Printed Circuit Board Layout Considerations—
Grounding, Bypassing and Output Signal Routing
The close proximity of high frequency digital data lines and
high dynamic range, wide-band analog signals makes
clean printed circuit board design and layout an absolute
necessity. Figures 5 to 9 are the printed circuit board layers
for an AC evaluation circuit for the LTC1668. Ground
planes should be split between digital and analog sections
as shown. All bypass capacitors should have minimum
trace length and be ceramic 0.1µF or larger with low ESR.
10
Bypass capacitors are required on VSS, VDD and REFOUT,
and all connected to the AGND plane. The COMP2 pin ties
to a node in the output current switching circuitry, and it
requires a 0.1µF bypass capacitor. It should be bypassed
to VSS along with COMP1. The AGND and DGND pins
should both tie directly to the AGND plane, and the tie point
between the AGND and DGND planes should nominally be
near the DGND pin. LADCOM should either be tied directly
to the AGND plane or be bypassed to AGND. The IOUT A and
IOUT B traces should be close together, short, and well
matched for good AC CMRR. The transformer output
ground should be capable of optionally being isolated or
being tied to the AGND plane, depending on which gives
better performance in the system.
Suggested Evaluation Circuit
Figure 4 is the schematic and Figures 5 to 9 are the circuit
board layouts for a suggested evaluation circuit, DC245A.
The circuit can be programmed with component selection
and jumpers for a variety of differentially coupled transformer output and differential and single-ended resistor
loaded output configurations.
J10
J7
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
4
GND
+
C14
10µF
25V
OPTIONAL
SIP
PULL-UP/
PULL-DOWN
RESISTORS
(NOT
INSTALLED)
J11
J8
10
9
7
8
C21
0.1µF
11
6
+5VA
12
5
22Ω
13
4
9
8
14
10
7
15
11
6
3
12
5
2
13
4
16
14
3
1
15
2
22Ω
RN6
16
+
C15
10µF
25V
TP9
TESTPOINT BLK
C23
0.1µF
1
JP9
2
26
14
13
12
11
10
9
8
7
6
5
4
3
2
1
28
27
16
J9
R12
49.9Ω
3 1%
CLK
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
–5V
J6
EXTCLK
24
17
25
23
22
21
18
–5V
C11
0.1µF
C8
0.1µF
C20
0.1µF
C16
10µF
25V
TP8
TESTPOINT RED
AGND DGND
GROUND PLANE
TIE POINT
5V
C10
0.1µF
C7
0.1µF
TP5
TESTPOINT WHT
19
20
15
C22
0.1µF
DGND
AGND
VDD
VSS
COMP2
COMP1
LADCOM
IOUT B
IOUT A
REFOUT
DB15 (MSB)
REFIN
LTC1668-28
C17
0.1µF
C3
0.1µF
Figure 4. Suggested Evaluation Circuit
R3
1.91k
0.1%
OPTIONAL
SIP
PULL-UP/
PULL-DOWN
RESISTORS
(NOT
INSTALLED)
+5VD
R2
200Ω
TP7
TESTPOINT RED
TP2
TESTPOINT WHT
2.5VREF
1
RN5
6
+5VD
4
6
5
VIN VOUT
3
2
2
JP1
1
LT1460DCS8-2.5
TP6
TESTPOINT RED
C19
0.1µF
3
4
+5VD
1
2
AMP
102159-9
C2
0.1µF
5V
C1
0.1µF
TP10
TESTPOINT BLK
C12
22pF
JP6
C8
0.1µF
JP5
R9
50Ω
0.1%
JP7
JP4
R10
50Ω
0.1%
J2
IOUT A
J5
IOUT B
C9
0.1µF
JP8
TP4
C4 TESTPOINT WHT
C12
22pF
1668 F04
C18
0.1µF
R7
110Ω
R6
R5
JP3
R4
JP2
TP3
TESTPOINT
WHT
5V
1
2
3
MINICIRCUITS
T1–1T
6
T1 4
R8
C5
J4
VOUT
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APPLICATIO S I FOR ATIO
U
R1
10Ω
+
J1
EXTREF
LTC1668
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APPLICATIO S I FOR ATIO
Figure 5. Suggested Evaluation Circuit Board—Silkscreen
Figure 6. Suggested Evaluation Circuit Board—Component Side
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Figure 7. Suggested Evaluation Circuit Board—GND Plane
Figure 8. Suggested Evaluation Circuit Board—Power Plane
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Figure 9. Suggested Evaluation Circuit Board—Solder Side
14
LTC1668
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PACKAGE DESCRIPTIO
Dimensions in millimeters (inches) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
10.07 – 10.33*
(0.397 – 0.407)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
7.65 – 7.90
(0.301 – 0.311)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
0° – 8°
0.13 – 0.22
(0.005 – 0.009)
0.55 – 0.95
(0.022 – 0.037)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
0.65
(0.0256)
BSC
0.25 – 0.38
(0.010 – 0.015)
0.05 – 0.21
(0.002 – 0.008)
G28 SSOP 1098
15
LTC1668
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TYPICAL APPLICATIO
5V
0.1µF
REFOUT
0.1µF
RSET
2k
VDD
2.5V
REFERENCE
LTC1668
500Ω
IREFIN
+
16-BIT
HIGH SPEED
DAC
–
IOUT A
200Ω
IOUT B
200Ω
+
VOUT
±1V
10dBm
500Ω
LADCOM
COMP2
0.1µF
LT®1812
COPT
COMP1
0.1µF
–
AGND DGND
VSS
CLK
DB15
52.3Ω
DB0
52.3Ω
1668 F10
CLOCK 16-BIT DATA
INPUT
INPUT
0.1µF
– 5V
Figure 10. High Speed Buffered VOUT DAC
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1406
8-Bit, 20Msps ADC
Undersampling Capability Up to 70MHz Input
LTC1414
14-Bit, 2.2Msps ADC
84dB SFDR at 1.1MHz fIN
LTC1420
12-Bit, 10Msps ADC
72dB SINAD at 5MHz fIN
LTC1604
16-Bit, 333ksps ADC
16-Bit, No Missing Codes, 90dB SINAD, –100dB THD
16
Linear Technology Corporation
1668i LT/TP 0200 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 2000