Precision, Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifiers AD8510/AD8512/AD8513 –IN 2 AD8510 8 NC NULL 1 7 V+ –IN 2 TOP VIEW 6 OUT (Not to Scale) V– 4 5 NULL NC V+ TOP VIEW 6 OUT (Not to Scale) V– 4 5 NULL +IN 3 7 +IN 3 02729-003 NC = NO CONNECT 8 AD8510 NC = NO CONNECT Figure 2. 8-Lead SOIC_N (R Suffix) OUT A 1 OUT A 1 –IN A 2 AD8512 8 V+ 7 OUT B TOP VIEW 6 –IN B (Not to Scale) V– 4 5 +IN B +IN A 3 –IN A 2 Figure 3. 8-Lead MSOP (RM Suffix) +IN A 3 V– 4 AD8512 8 V+ 7 OUT B TOP VIEW 6 –IN B (Not to Scale) 5 +IN B Figure 4. 8-Lead SOIC_N (R Suffix) OUT A 1 14 OUT D OUT A 1 14 OUT D –IN A 2 13 –IN D –IN A 2 13 –IN D +IN A 3 12 +IN D +IN A 3 12 +IN D 11 V– TOP VIEW +IN B 5 (Not to Scale) 10 +IN C V+ 4 V+ 4 AD8513 –IN B 6 9 –IN C OUT B 7 8 OUT C 02729-002 Figure 1. 8-Lead MSOP (RM Suffix) AD8513 11 V– TOP VIEW +IN B 5 (Not to Scale) 10 +IN C Figure 5. 14-Lead SOIC_N (R Suffix) –IN B 6 9 –IN C OUT B 7 8 OUT C 02729-006 Instrumentation Multipole filters Precision current measurement Photodiode amplifiers Sensors Audio NULL 1 02729-001 APPLICATIONS PIN CONFIGURATIONS 02729-005 Fast settling time: 500 ns to 0.1% Low offset voltage: 400 μV maximum Low TCVOS: 1 μV/°C typical Low input bias current: 25 pA typical at VS = ±15 V Dual-supply operation: ±5 V to ±15 V Low noise: 8 nV/√Hz typical at f = 1 kHz Low distortion: 0.0005% No phase reversal Unity gain stable 02729-004 FEATURES Figure 6. 14-Lead TSSOP (RU Suffix) GENERAL DESCRIPTION The AD8510/AD8512/AD8513 are single-, dual-, and quadprecision JFET amplifiers that feature low offset voltage, input bias current, input voltage noise, and input current noise. The combination of low offsets, low noise, and very low input bias currents makes these amplifiers especially suitable for high impedance sensor amplification and precise current measurements using shunts. The combination of dc precision, low noise, and fast settling time results in superior accuracy in medical instruments, electronic measurement, and automated test equipment. Unlike many competitive amplifiers, the AD8510/ AD8512/AD8513 maintain their fast settling performance even with substantial capacitive loads. Unlike many older JFET amplifiers, the AD8510/AD8512/AD8513 do not suffer from output phase reversal when input voltages exceed the maximum common-mode voltage range. Fast slew rate and great stability with capacitive loads make the AD8510/AD8512/AD8513 a perfect fit for high performance filters. Low input bias currents, low offset, and low noise result in a wide dynamic range of photodiode amplifier circuits. Low noise and distortion, high output current, and excellent speed make the AD8510/AD8512/AD8513 great choices for audio applications. The AD8510/AD8512 are both available in 8-lead narrow SOIC_N and 8-lead MSOP packages. MSOP-packaged parts are only available in tape and reel. The AD8513 is available in 14-lead SOIC_N and TSSOP packages. The AD8510/AD8512/AD8513 are specified over the −40°C to +125°C extended industrial temperature range. Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved. AD8510/AD8512/AD8513 TABLE OF CONTENTS Features .............................................................................................. 1 Output Phase Reversal ............................................................... 13 Applications ....................................................................................... 1 Total Harmonic Distortion (THD) + Noise .............................. 13 Pin Configurations ........................................................................... 1 Total Noise Including Source Resistors ................................... 13 General Description ......................................................................... 1 Settling Time ............................................................................... 14 Revision History ............................................................................... 2 Overload Recovery Time .......................................................... 14 Specifications..................................................................................... 3 Capacitive Load Drive ............................................................... 14 Electrical Characteristics ............................................................. 4 Open-Loop Gain and Phase Response .................................... 15 Absolute Maximum Ratings............................................................ 6 Precision Rectifiers..................................................................... 16 ESD Caution .................................................................................. 6 I-V Conversion Applications .................................................... 17 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 19 General Application Information ................................................. 13 Ordering Guide .......................................................................... 20 Input Overvoltage Protection ................................................... 13 REVISION HISTORY 2/09—Rev. H to Rev. I Changes to Figure 25 ...................................................................... 10 Changes to Ordering Guide .......................................................... 20 10/07—Rev. G to Rev. H Changes to Crosstalk Section........................................................ 18 Added Figure 58.............................................................................. 18 6/07—Rev. F to Rev. G Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Table 1 and Table 2 ....................................................... 3 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 6/06—Rev. E to Rev. F Changes to Figure 23 ........................................................................ 9 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 6/04—Rev. D to Rev. E Changes to Format ............................................................. Universal Changes to Specifications ................................................................ 3 Updated Outline Dimensions ....................................................... 19 10/03—Rev. C to Rev. D Added AD8513 Model ....................................................... Universal Changes to Specifications ................................................................ 3 Added Figure 36 through Figure 40 ............................................. 10 Added Figure 55 and Figure 57..................................................... 17 Changes to Ordering Guide .......................................................... 20 9/03—Rev. B to Rev. C Changes to Ordering Guide ............................................................4 Updated Figure 2 ............................................................................ 10 Changes to Input Overvoltage Protection Section .................... 10 Changes to Figure 10 and Figure 11............................................. 12 Changes to Photodiode Circuits Section .................................... 13 Changes to Figure 13 and Figure 14............................................. 13 Deleted Precision Current Monitoring Section ......................... 14 Updated Outline Dimensions ....................................................... 15 3/03—Rev. A to Rev. B Updated Figure 5 ............................................................................ 11 Updated Outline Dimensions ....................................................... 15 8/02—Rev. 0 to Rev. A Added AD8510 Model ....................................................... Universal Added Pin Configurations ...............................................................1 Changes to Specifications .................................................................2 Changes to Ordering Guide .............................................................4 Changes to TPC 2 and TPC 3 ..........................................................5 Added TPC 10 and TPC 12 ..............................................................6 Replaced TPC 20 ...............................................................................8 Replaced TPC 27 ...............................................................................9 Changes to General Application Information Section .............. 10 Changes to Figure 5 ........................................................................ 11 Changes to I-V Conversion Applications Section ..................... 13 Changes to Figure 13 and Figure 14............................................. 13 Changes to Figure 17...................................................................... 14 Rev. I | Page 2 of 20 AD8510/AD8512/AD8513 SPECIFICATIONS @ VS = ±5 V, VCM = 0 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage (B Grade) 1 Symbol Conditions Min VOS Typ Max Unit 0.08 0.4 0.8 0.9 1.8 75 0.7 7.5 50 0.3 0.5 mV mV mV mV pA nA nA pA nA nA −40°C < TA < +125°C Offset Voltage (A Grade) VOS 0.1 −40°C < TA < +125°C Input Bias Current IB 21 −40°C < TA < +85°C −40°C < TA < +125°C Input Offset Current IOS 5 −40°C < TA < +85°C −40°C < TA < +125°C Input Capacitance Differential Common Mode Input Voltage Range Common-Mode Rejection Ratio Large-Signal Voltage Gain Offset Voltage Drift (B Grade)1 Offset Voltage Drift (A Grade) OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier AD8510/AD8512/AD8513 AD8510/AD8512 AD8513 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Settling Time Total Harmonic Distortion (THD) + Noise Phase Margin NOISE PERFORMANCE Voltage Noise Density Peak-to-Peak Voltage Noise 1 12.5 11.5 CMRR AVO ΔVOS/ΔT ΔVOS/ΔT VCM = −2.0 V to +2.5 V RL = 2 kΩ, VO = −3 V to +3 V VOH VOL VOH VOL VOH VOL IOUT RL = 10 kΩ RL = 10 kΩ, −40°C < TA < +125°C RL = 2 kΩ RL = 2 kΩ, −40°C < TA < +125°C RL = 600 Ω RL = 600 Ω, −40°C < TA < +125°C PSRR ISY VS = ±4.5 V to ±18 V SR GBP tS THD + N φM en en p-p −2.0 86 65 4.1 +2.5 100 107 0.9 1.7 ±40 4.3 −4.9 4.2 −4.9 4.1 −4.8 ±54 86 130 3.9 3.7 5 12 −4.7 −4.5 −4.2 pF pF V dB V/mV μV/°C μV/°C V V V V V V mA dB VO = 0 V −40°C < TA < +125°C −40°C < TA < +125°C 2.0 RL = 2 kΩ 20 8 0.4 0.0005 44.5 V/μs MHz μs % Degrees 34 12 8.0 7.6 2.4 nV/√Hz nV/√Hz nV/√Hz nV/√Hz μV p-p To 0.1%, 0 V to 4 V step, G = +1 1 kHz, G = +1, RL = 2 kΩ f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz 0.1 Hz to 10 Hz bandwidth AD8510/AD8512 only. Rev. I | Page 3 of 20 2.3 2.5 2.75 10 5.2 mA mA mA AD8510/AD8512/AD8513 ELECTRICAL CHARACTERISTICS @ VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage (B Grade) 1 Symbol Conditions Min VOS Typ Max Unit 0.08 0.4 0.8 mV mV 0.1 1.0 1.8 80 0.7 10 75 0.3 0.5 mV mV pA nA nA pA nA nA +13.0 pF pF V dB V/mV 5 12 μV/°C μV/°C −40°C < TA < +125°C Offset Voltage (A Grade) VOS −40°C < TA < +125°C Input Bias Current IB 25 −40°C < TA < +85°C −40°C < TA < +125°C Input Offset Current IOS 6 −40°C < TA < +85°C −40°C < TA < +125°C Input Capacitance Differential Common Mode Input Voltage Range Common-Mode Rejection Ratio Large-Signal Voltage Gain Offset Voltage Drift (B Grade)1 Offset Voltage Drift (A Grade) OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier AD8510/AD8512/AD8513 AD8510/AD8512 AD8513 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Settling Time Total Harmonic Distortion (THD) + Noise Phase Margin 12.5 11.5 CMRR AVO VCM = −12.5 V to +12.5 V RL = 2 kΩ, VCM = 0 V, VO = −13.5 V to +13.5 V −13.5 86 115 ΔVOS/ΔT ΔVOS/ΔT VOH VOL VOH VOL VOH VOL 1.0 1.7 RL = 10 kΩ RL = 10 kΩ, −40°C < TA < +125°C RL = 2 kΩ RL = 2 kΩ, −40°C < TA < +125°C RL = 600 Ω RL = 600 Ω, −40°C < TA < +125°C RL = 600 Ω RL = 600 Ω, −40°C < TA < +125°C +14.0 +13.8 +13.5 +11.4 SR GBP tS THD + N φM +14.2 −14.9 +14.1 –14.8 +13.9 −14.3 IOUT PSRR ISY 108 196 −14.6 −14.5 −13.8 −12.1 ±70 VS = ±4.5 V to ±18 V 86 dB VO = 0 V −40°C < TA < +125°C −40°C < TA < +125°C 2.2 RL = 2 kΩ 20 8 0.5 0.9 0.0005 52 To 0.1%, 0 V to 10 V step, G = +1 To 0.01%, 0 V to 10 V step, G = +1 1 kHz, G = +1, RL = 2 kΩ Rev. I | Page 4 of 20 V V V V V V V V mA 2.5 2.6 3.0 mA mA mA V/μs MHz μs μs % Degrees AD8510/AD8512/AD8513 Parameter NOISE PERFORMANCE Voltage Noise Density Peak-to-Peak Voltage Noise 1 Symbol Conditions en f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz 0.1 Hz to 10 Hz bandwidth en p-p AD8510/AD8512 only. Rev. I | Page 5 of 20 Min Typ 34 12 8.0 7.6 2.4 Max Unit 10 nV/√Hz nV/√Hz nV/√Hz nV/√Hz μV p-p 5.2 AD8510/AD8512/AD8513 ABSOLUTE MAXIMUM RATINGS Table 4. Thermal Resistance Table 3. Parameter Supply Voltage Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 10 sec) Electrostatic Discharge (Human Body Model) Rating ±18 V ±VS Observe derating curves −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C 2000 V Package Type 8-Lead MSOP (RM) 8-Lead SOIC_N (R) 14-Lead SOIC_N (R) 14-Lead TSSOP (RU) 1 θJA1 210 158 120 180 θJC 45 43 36 35 Unit °C/W °C/W °C/W °C/W θJA is specified for worst-case conditions, that is, θJA is specified for device soldered in circuit board for surface-mount packages. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. I | Page 6 of 20 AD8510/AD8512/AD8513 TYPICAL PERFORMANCE CHARACTERISTICS 120 INPUT BIAS CURRENT (pA) 100 80 60 40 10k 1k 100 10 02729-007 20 0 VSY = ±5V, ±15V –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 1 –40 0.5 INPUT OFFSET VOLTAGE (mV) Figure 7. Input Offset Voltage Distribution 02729-010 NUMBER OF AMPLIFIERS 100k VSY = ±15V TA = 25°C –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 10. Input Bias Current vs. Temperature 30 1000 VSY = ±15V B GRADE 20 15 10 02729-008 5 0 0 1 2 3 TCVOS (µV/°C) 4 5 100 ±15V 10 ±5V 1 0.1 –40 6 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 11. Input Offset Current vs. Temperature Figure 8. AD8510/AD8512 TCVOS Distribution 40 30 VSY = ±15V A GRADE TA = 25°C 35 INPUT BIAS CURRENT (pA) 25 15 10 5 0 0 1 2 3 TCVOS (µV/°C) 4 5 30 25 20 15 10 5 0 6 Figure 9. AD8510/AD8512 TCVOS Distribution 02729-012 20 02729-009 NUMBER OF AMPLIFIERS 02729-011 INPUT OFFSET CURRENT (pA) NUMBER OF AMPLIFIERS 25 8 13 18 23 SUPPLY VOLTAGE (V+ – V– ) 28 Figure 12. Input Bias Current vs. Supply Voltage Rev. I | Page 7 of 20 30 AD8510/AD8512/AD8513 2.8 TA = 25°C 1.9 1.8 SUPPLY CURRENT (mA) 2.4 1.7 1.6 1.5 1.4 1.3 2.2 2.0 1.8 1.6 18 23 SUPPLY VOLTAGE (V+ – V–) 13 28 1.0 30 8 Figure 13. AD8512 Supply Current per Amplifier vs. Supply Voltage 10 GAIN (dB) OUTPUT VOLTAGE (V) 50 12 8 180 135 20 90 10 45 02729-014 30 40 50 LOAD CURRENT (mA) 60 70 –10 –45 –20 –90 –30 10k 80 2.25 2.25 SUPPLY CURRENT (mA) 2.50 ±15V 1.75 ±5V 1.50 1M FREQUENCY (Hz) –135 50M 10M ±15V 2.00 ±5V 1.75 1.50 1.25 1.25 02729-015 SUPPLY CURRENT PER AMPLIFIER (mA) 2.50 1.00 –40 –25 100k Figure 17. Open-Loop Gain and Phase vs. Frequency Figure 14. AD8510/AD8512 Output Voltage vs. Load Current 2.00 0 0 2 20 225 40 VSY = ±5V VOH 10 270 30 4 0 315 VSY = ±15V RL = 2.5kΩ CSCOPE = 20pF ΦM = 52° 60 VOH VOL 33 70 VSY = ±15V 14 6 28 Figure 16. AD8510 Supply Current vs. Supply Voltage 16 VOL 18 23 SUPPLY VOLTAGE (V+ – V–) 13 PHASE (Degrees) 8 –10 5 20 65 35 50 TEMPERATURE (°C) 80 95 1.00 –40 –25 110 125 02729-018 1.0 1.2 –10 5 20 65 35 50 TEMPERATURE (°C) 80 95 110 125 Figure 18. AD8510 Supply Current vs. Temperature Figure 15. AD8512 Supply Current per Amplifier vs. Temperature Rev. I | Page 8 of 20 02729-017 1.1 02729-016 1.4 1.2 0 TA = 25°C 2.6 02729-013 SUPPLY CURRENT PER AMPLIFIER (mA) 2.0 AD8510/AD8512/AD8513 300 70 VSY = ±15V, ±5V 60 240 OUTPUT IMPEDANCE (Ω) AV = 100 30 20 0 –10 AV = 1 180 150 AV = 1 120 AV = 100 90 60 –20 –30 1k 210 10k 100k 1M FREQUENCY (Hz) 10M AV = 10 02729-022 10 AV = 10 02729-019 CLOSED-LOOP GAIN (dB) 50 40 VSY = ±15V VIN = 50mV 270 30 0 100 50M Figure 19. Closed-Loop Gain vs. Frequency 1k 10k 1M 100k FREQUENCY (Hz) 1k VSY = ±5V TO ±15V 100 80 60 40 02729-020 20 1k 10k 100k 1M FREQUENCY (Hz) 10M 100 10 1 100M 02729-023 VOLTAGE NOISE DENSITY (nV/ Hz) VSY = ±15V CMRR (dB) 100M Figure 22. Output Impedance vs. Frequency 120 0 100 10M 1 10 100 1k 10k FREQUENCY (Hz) Figure 23. Voltage Noise Density vs. Frequency Figure 20. CMRR vs. Frequency 120 VSY = ±15V VSY = ±5V, ±15V 100 VOLTAGE (1µV/DIV) 80 40 +PSRR 0 –20 100 02729-024 20 02729-021 PSRR (dB) –PSRR 60 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M TIME (1s/DIV) Figure 21. PSRR vs. Frequency Figure 24. 0.1 Hz to 10 Hz Input Voltage Noise Rev. I | Page 9 of 20 AD8510/AD8512/AD8513 280 90 VSY = ±5V TO ±15V SMALL-SIGNAL OVERSHOOT (%) 140 105 70 35 60 50 20 2 3 4 5 6 7 8 9 10 0 10 10 1 FREQUENCY (Hz) Figure 25. Voltage Noise Density vs. Frequency 10k 100 1k LOAD CAPACITANCE (pF) Figure 28. Small-Signal Overshoot vs. Load Capacitance 70 VSY = ±15V RL = 2kΩ CL = 100pF AV = 1 315 VSY = ±5V RL = 2.5kΩ CSCOPE = 20pF ΦM = 44.5° 60 VOLTAGE (5V/DIV) OPEN-LOOP GAIN (dB) 50 225 40 180 30 135 20 90 10 45 0 0 –10 02729-026 270 PHASE (Degrees) 1 –OS 30 –45 –20 –90 –30 10k 1M 100k TIME (1µs/DIV) 10M –135 50M FREQUENCY (Hz) Figure 26. Large-Signal Transient Response Figure 29. Open-Loop Gain and Phase vs. Frequency 120 VSY = ±5V VSY = ±15V RL = 2kΩ CL = 100pF AV = 1 100 CMRR (dB) VOLTAGE (50mV/DIV) 80 60 40 0 100 TIME (100ns/DIV) Figure 27. Small-Signal Transient Response 02729-030 02729-027 20 1k 10k 100k 1M FREQUENCY (Hz) Figure 30. CMRR vs. Frequency Rev. I | Page 10 of 20 10M 100M 02729-029 0 +OS 40 02729-028 175 70 02729-025 VOLTAGE NOISE DENSITY (nV Hz) 210 0 VSY = ±15V RL = 2kΩ 80 245 AD8510/AD8512/AD8513 300 VSY = ±5V VIN = 50mV 270 VSY = ±5V RL = 2kΩ CL = 100pF AV = 1 VOLTAGE (50mV/DIV) AV = 1 180 150 120 AV = 100 60 AV = 10 30 0 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 02729-034 90 02729-031 OUTPUT IMPEDANCE (Ω) 240 210 100M TIME (100ns/DIV) Figure 34. Small-Signal Transient Response Figure 31. Output Impedance vs. Frequency 100 VSY = ±5V VSY = ±5V RL = 2kΩ 80 70 60 +OS 50 –OS 40 30 20 02729-035 02729-032 VOLTAGE (1µV/DIV) SMALL-SIGNAL OVERSHOOT (%) 90 10 0 TIME (1s/DIV) Figure 32. 0.1 Hz to 10 Hz Input Voltage Noise 1 10 100 1k LOAD CAPACITANCE (pF) 10k Figure 35. Small-Signal Overshoot vs. Load Capacitance 100 VS = ±15V 90 VSY = ±5V RL = 2kΩ CL = 100pF AV = 1 VOLTAGE (2V/DIV) NUMBER OF AMPLIFIERS 80 70 60 50 40 30 02729-036 20 02729-033 10 0 0 1 2 3 4 TCVOS (µV/°C) TIME (1µs/DIV) Figure 33. Large-Signal Transient Response Figure 36. AD8513 TCVOS Distribution Rev. I | Page 11 of 20 5 6 AD8510/AD8512/AD8513 120 16 VS = ±5V OUTPUT VOLTAGE (V) NUMBER OF AMPLIFIERS VOH 80 60 40 12 10 8 6 VOH 20 0 1 2 3 4 5 0 6 02729-039 2 02729-037 0 0 30 20 10 TCVOS (µV/°C) 40 50 60 70 80 LOAD CURRENT (mA) Figure 37. AD8513 TCVOS Distribution Figure 39. AD8513 Output Voltage vs. Load Current 3.0 2.4 SUPPLY CURRENT PER AMPLIFIER (mA) TA = 25°C 2.3 2.2 2.1 2.0 1.9 1.8 02729-038 1.7 1.6 8 13 18 23 28 2.5 2.0 ±5V 1.5 1.0 0.5 0 –40 33 ±15V 02729-040 2.5 SUPPLY CURRENT PER AMPLIFIER (mA) VSY = ±5V VOL 4 1.5 VSY = ±15V VOL 14 100 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) SUPPLY VOLTAGE (V+ – V–) Figure 38. AD8513 Supply Current per Amplifier vs. Supply Voltage Figure 40. AD8513 Supply Current per Amplifier vs. Temperature Rev. I | Page 12 of 20 AD8510/AD8512/AD8513 GENERAL APPLICATION INFORMATION 0.01 INPUT OVERVOLTAGE PROTECTION VSY = ±5V RL = 100kΩ BW = 22kHz RS 0.001 ≤ 5 mA With a very low offset current of <0.5 nA up to 125°C, higher resistor values can be used in series with the inputs. A 5 kΩ resistor protects the inputs from voltages as high as 25 V beyond the supplies and adds less than 10 μV to the offset. 0.0001 20 02729-056 VIN − VS DISTORTION (%) The AD8510/AD8512/AD8513 have internal protective circuitry that allows voltages as high as 0.7 V beyond the supplies to be applied at the input of either terminal without causing damage. For higher input voltages, a series resistor is necessary to limit the input current. The resistor value can be determined from the formula 100 1k FREQUENCY (Hz) 10k 20k Figure 42. THD + N vs. Frequency OUTPUT PHASE REVERSAL TOTAL NOISE INCLUDING SOURCE RESISTORS Phase reversal is a change of polarity in the transfer function of the amplifier. This can occur when the voltage applied at the input of an amplifier exceeds the maximum common-mode voltage. The low input current noise and input bias current of the AD8510/AD8512/AD8513 make them the ideal amplifiers for circuits with substantial input source resistance. Input offset voltage increases by less than 15 nV per 500 Ω of source resistance at room temperature. The total noise density of the circuit is Phase reversal can cause permanent damage to the device and can result in system lockups. The AD8510/AD8512/AD8513 do not exhibit phase reversal when input voltages are beyond the supplies. where: en is the input voltage noise density of the parts. in is the input current noise density of the parts. RS is the source resistance at the noninverting terminal. k is Boltzmann’s constant (1.38 × 10–23 J/K). T is the ambient temperature in Kelvin (T = 273 + °C). VSY = ±5V AV = 1 RL = 10kΩ VOUT For RS < 3.9 kΩ, en dominates and enTOTAL ≈ en. The current noise of the AD8510/AD8512/AD8513 is so low that its total density does not become a significant term unless RS is greater than 165 MΩ, an impractical value for most applications. VIN 02729-057 VOLTAGE (2V/DIV) e nTOTAL = e n 2 + (i n R S )2 + 4kTR S The total equivalent rms noise over a specific bandwidth is expressed as TIME (20µs/DIV) enTOTAL = enTOTAL BW Figure 41. No Phase Reversal TOTAL HARMONIC DISTORTION (THD) + NOISE where BW is the bandwidth in hertz. The AD8510/AD8512/AD8513 have low THD and excellent gain linearity, making these amplifiers great choices for precision circuits with high closed-loop gain and for audio application circuits. Figure 42 shows that the AD8510/AD8512/AD8513 have approximately 0.0005% of total distortion when configured in positive unity gain (the worst case) and driving a 100 kΩ load. Note that the previous analysis is valid for frequencies larger than 150 Hz and assumes flat noise above 10 kHz. For lower frequencies, flicker noise (1/f) must be considered. Rev. I | Page 13 of 20 AD8510/AD8512/AD8513 SETTLING TIME OUTPUT +15V 0V VOLTAGE INPUT Settling time is the time it takes the output of the amplifier to reach and remain within a percentage of its final value after a pulse is applied at the input. The AD8510/AD8512/AD8513 settle to within 0.01% in less than 900 ns with a step of 0 V to 10 V in unity gain. This makes each of these parts an excellent choice as a buffer at the output of DACs whose settling time is typically less than 1 μs. 0V –200mV 02729-054 In addition to the fast settling time and fast slew rate, low offset voltage drift and input offset current maintain the full accuracy of 12-bit converters over the entire operating temperature range. VSY = ±15V AV = –100 RL = 10kΩ TIME (2µs/DIV) OVERLOAD RECOVERY TIME Overload recovery, also known as overdrive recovery, is the time it takes the output of an amplifier to recover to its linear region from a saturated condition. This recovery time is particularly important in applications where the amplifier must amplify small signals in the presence of large transient voltages. 0V VSY = ±15V VIN = 200mV AV = –100 RL = 10kΩ –15V VOLTAGE OUTPUT Figure 43 shows the positive overload recovery of the AD8510/ AD8512/AD8513. The output recovers in approximately 200 ns from a saturated condition. Figure 44. Negative Overload Recovery CAPACITIVE LOAD DRIVE The AD8510/AD8512/AD8513 are unconditionally stable at all gains in inverting and noninverting configurations. Each device is capable of driving a capacitive load of up to 1000 pF without oscillation in unity gain using the worst-case configuration. However, as with most amplifiers, driving larger capacitive loads in a unity gain configuration may cause excessive overshoot and ringing, or even oscillation. A simple snubber network significantly reduces the amount of overshoot and ringing. The advantage of this configuration is that the output swing of the amplifier is not reduced, because RS is outside the feedback loop. 2 7 AD8510 200mV 3 VOUT 6 4 RS TIME (2µs/DIV) CS Figure 43. Positive Overload Recovery V– The negative overdrive recovery time shown in Figure 44 is less than 200 ns. In addition to the fast recovery time, the AD8510/AD8512/ AD8513 show excellent symmetry of the positive and negative recovery times. This is an important feature for transient signal rectification because the output signal is kept equally undistorted throughout any given period. Rev. I | Page 14 of 20 Figure 45. Snubber Network Configuration CL 02729-055 0V 02729-053 INPUT V+ 200mV AD8510/AD8512/AD8513 Figure 46 shows a scope plot of the output of the AD8510/AD8512/ AD8513 in response to a 400 mV pulse. The circuit is configured in positive unity gain (worst case) with a load experience of 500 pF. VSY = ±15V CL = 500pF RL =10kΩ OPEN-LOOP GAIN AND PHASE RESPONSE In addition to their impressive low noise, low offset voltage, and offset current, the AD8510/AD8512/AD8513 have excellent loop gain and phase response even when driving large resistive and capacitive loads. VOLTAGE (200mV/DIV) Compared with Competitor A (see Figure 49) under the same conditions, with a 2.5 kΩ load at the output, the AD8510/AD8512/ AD8513 have more than 8 MHz of bandwidth and a phase margin of more than 52°. When the snubber circuit is used, the overshoot is reduced from 55% to less than 3% with the same load capacitance. Ringing is virtually eliminated, as shown in Figure 47. 50 VOLTAGE (200mV/DIV) 70 60 GAIN (dB) VSY = ±15V RL = 10kΩ CL = 500pF RS = 100Ω CS = 1nF 315 VSY = ±15V RL = 2.5kΩ CL = 0pF 270 225 40 180 30 135 20 90 10 45 0 0 PHASE (Degrees) TIME (1µs/DIV) Figure 46. Capacitive Load Drive Without Snubber –10 –45 –20 –90 –30 10k 100k 1M FREQUENCY (Hz) 10M –135 50M 02729-043 02729-041 Competitor A, on the other hand, has only 4.5 MHz of bandwidth and 28° of phase margin under the same test conditions. Even with a 1 nF capacitive load in parallel with the 2 kΩ load at the output, the AD8510/AD8512/AD8513 show much better response than Competitor A, whose phase margin is degraded to less than 0, indicating oscillation. 70 60 Figure 47. Capacitive Load with Snubber Network Table 5. Optimum Values for Capacitive Loads RS (Ω) 100 70 60 GAIN (dB) 50 Optimum values for RS and CS depend on the load capacitance and input stray capacitance and are determined empirically. Table 5 shows a few values that can be used as starting points. CLOAD 500 pF 2 nF 5 nF 315 VSY = ±15V RL = 2.5kΩ CL = 0pF CS 1 nF 100 pF 300 pF 225 40 180 30 135 20 90 10 45 0 0 –10 –45 –20 –90 –30 10k 100k 1M FREQUENCY (Hz) 10M Figure 49. Frequency Response of Competitor A Rev. I | Page 15 of 20 270 PHASE (Degrees) TIME (1µs/DIV) –135 50M 02729-044 02729-042 Figure 48. Frequency Response of the AD8510/AD8512/AD8513 AD8510/AD8512/AD8513 PRECISION RECTIFIERS VOLTAGE (1V/DIV) Rectifying circuits are used in a multitude of applications. One of the most popular uses is in the design of regulated power supplies, where a rectifier circuit is used to convert an input sinusoid to a unipolar output voltage. 02729-046 However, there are some potential problems with amplifiers used in this manner. When the input voltage (VIN) is negative, the output is zero, and the magnitude of VIN is doubled at the inputs of the op amp. If this voltage exceeds the power supply voltage, it may permanently damage some amplifiers. In addition, the op amp must come out of saturation when VIN is negative. This delays the output signal because the amplifier requires time to enter its linear region. TIME (1ms/DIV) Although the AD8510/AD8512/AD8513 have a very fast overdrive recovery time, which makes them great choices for the rectification of transient signals, the symmetry of the positive and negative recovery times is also important to keep the output signal undistorted. R3 10kΩ 02729-047 R2 10kΩ VOLTAGE (1V/DIV) Figure 50 shows the test circuit of the rectifier. The first stage of the circuit is a half-wave rectifier. When the sine wave applied at the input is positive, the output follows the input response. During the negative cycle of the input, the output tries to swing negative to follow the input, but the power supply restrains it to zero. In a similar fashion, the second stage is a follower during the positive cycle of the sine wave and an inverter during the negative cycle. Figure 51. Half-Wave Rectifier Signal (OUT A in Figure 50) TIME (1ms/DIV) Figure 52. Full-Wave Rectifier Signal (OUT B in Figure 50) 10V VIN 3V p-p 6 3 R1 1kΩ 1/2 AD8512 2 4 2/2 AD8512 8 1 8 5 7 OUT B (FULL WAVE) 4 02729-045 10V OUT A (HALF WAVE) Figure 50. Half-Wave and Full-Wave Rectifiers Rev. I | Page 16 of 20 AD8510/AD8512/AD8513 I-V CONVERSION APPLICATIONS Photodiode Circuits Common applications for I-V conversion include photodiode circuits where the amplifier is used to convert a current emitted by a diode placed at the positive input terminal into an output voltage. The AD8510/AD8512/AD8513’s low input bias current, wide bandwidth, and low noise make them each an excellent choice for various photodiode applications, including fax machines, fiber optic controls, motion sensors, and bar code readers. The circuit shown in Figure 53 uses a silicon diode with zero bias voltage. This is known as a photovoltaic mode; this configuration limits the overall noise and is suitable for instrumentation applications. A typical value for Rd is 1000 MΩ. Because Rd >> R2, the circuit behavior is not impacted by the effect of the junction resistance. The maximum signal bandwidth is f MAX = ft 2πR2Ct where ft is the unity gain frequency of the amplifier. Cf can be calculated by Cf = Ct 2πR2 ft where ft is the unity gain frequency of the op amp, and it achieves a phase margin, φM, of approximately 45°. A higher phase margin can be obtained by increasing the value of Cf. Setting Cf to twice the previous value yields approximately φM = 65° and a maximal flat frequency response, but it reduces the maximum signal bandwidth by 50%. Cf R2 Using the previous parameters with a Cf ≈ 1 pF, the signal bandwidth is approximately 2.6 MHz. VEE Signal Transmission Applications 4 Rd Ct 3 One popular signal transmission method uses pulse-width modulation. High data rates may require a fast comparator rather than an op amp. However, the need for sharp, undistorted signals may favor using a linear amplifier. 6 7 VCC Figure 53. Equivalent Preamplifier Photodiode Circuit A larger signal bandwidth can be attained at the expense of additional output noise. The total input capacitance (Ct) consists of the sum of the diode capacitance (typically 3 pF to 4 pF) and the amplifier’s input capacitance (12 pF), which includes external parasitic capacitance. Ct creates a pole in the frequency response that can lead to an unstable system. To ensure stability and optimize the bandwidth of the signal, a capacitor is placed in the feedback loop of the circuit shown in Figure 53. It creates a zero and yields a bandwidth whose corner frequency is 1/(2π(R2Cf)). The value of R2 can be determined by the ratio The AD8510/AD8512/AD8513 make excellent voltage comparators. In addition to a high slew rate, the AD8510/ AD8512/AD8513 have a very fast saturation recovery time. In the absence of feedback, the amplifiers are in open-loop mode (very high gain). In this mode of operation, they spend much of their time in saturation. The circuit shown in Figure 54 was used to compare two signals of different frequencies, namely a 100 Hz sine wave and a 1 kHz triangular wave. Figure 55 shows a scope plot of the resulting output waveforms. A pull-up resistor (typically 5 kΩ) can be connected from the output to VCC if the output voltage needs to reach the positive rail. The trade-off is that power consumption is higher. +15V V/ID where: V is the desired output voltage of the op amp. ID is the diode current. 3 2 For example, if ID is 100 μA and a 10 V output voltage is desired, R2 should be 100 kΩ. Rd (see Figure 53) is a junction resistance that drops typically by a factor of 2 for every 10°C increase in temperature. Rev. I | Page 17 of 20 V1 7 VOUT 4 –15V V2 6 02729-049 AD8510 02729-048 2 Figure 54. Pulse-Width Modulator AD8510/AD8512/AD8513 02729-050 VOLTAGE (5V/DIV) The AD8510 single has two additional active terminals that are not present on the AD8512 dual or AD8513 quad parts. These pins are labeled “null” and are used for fine adjustment of the input offset voltage. Although the guaranteed maximum offset voltage at room temperature is 400 μV and over the −40°C to +125°C range is 800 mV maximum, this offset voltage can be reduced by adding a potentiometer to the null pins as shown in Figure 58. With the 20 kΩ potentiometer shown, the adjustment range is approximately ±3.5 mV. The potentiometer parallels low value resistors in the drain circuit of the JFET differential input pair and allows unbalancing of the drain currents to change the offset voltage. If offset adjustment is not required, these pins should be left unconnected. TIME (2ms/DIV) Figure 55. Pulse-Width Modulation Crosstalk Crosstalk, also known as channel separation, is a measure of signal feedthrough from one channel to another on the same IC. The AD8512/AD8513 have a channel separation of better than −90 dB for frequencies up to 10 kHz and of better than −50 dB for frequencies up to 10 MHz. Figure 57 shows the typical channel separation behavior between Amplifier A (driving amplifier) and each of the following: Amplifier B, Amplifier C, and Amplifier D. VOUT 2.2kΩ 20kΩ +VS 18V p-p 8 1 6 7 3 VIN – 5 5kΩ VOUT CROSSTALK = 20 log 10V IN 5kΩ –VS + Figure 56. Crosstalk Test Circuit 5 AD8510 3 4 7 6 OUTPUT VOS TRIM RANGE IS TYPICALLY ±3.5mV V– Figure 58. Optional Offset Nulling Circuit –20 –40 –60 CH B CH D –80 CH C –100 –120 –140 02729-051 CHANNEL SEPARATION (dB) 2 INPUT 4 0 –160 100 V+ 1 02729-052 2 1k 100k 10k FREQUENCY (Hz) 1M 10M Figure 57. Channel Separation Rev. I | Page 18 of 20 02729-058 20kΩ Caution should be used when adding adjusting potentiometers to any op amp with this capability for several reasons. First, there is gain from these nodes to the output; therefore, capacitive coupling from noisy traces to these nodes will inject noise into the signal path. Second, the temperature coefficient of the potentiometer will not match the temperature coefficient of the internal resistors, so the offset voltage drift with temperature will be slightly affected. Third, this provision is for adjusting the offset voltage of the op amp, not for adjusting the offset of the overall system. Although it is tempting to decrease the value of the potentiometer to attain more range, this will adversely affect the dc and ac parameters. Instead, increase the potentiometer to 50 kΩ to decrease the range if needed. AD8510/AD8512/AD8513 OUTLINE DIMENSIONS 5.10 5.00 4.90 5.00 (0.1968) 4.80 (0.1890) 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 14 0.50 (0.0196) 0.25 (0.0099) 8 4.50 4.40 4.30 6.40 BSC 45° 1 8° 0° 7 PIN 1 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.65 BSC 1.05 1.00 0.80 1.20 MAX 0.15 0.05 012407-A 8 4.00 (0.1574) 3.80 (0.1497) 0.30 0.19 0.20 0.09 SEATING COPLANARITY PLANE 0.10 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 59. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 8.75 (0.3445) 8.55 (0.3366) 5.15 4.90 4.65 4.00 (0.1575) 3.80 (0.1496) 4 8 14 1 7 6.20 (0.2441) 5.80 (0.2283) PIN 1 0.25 (0.0098) 0.10 (0.0039) 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8° 0° 0.80 0.60 0.40 COPLANARITY 0.10 SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 62. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Figure 60. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. I | Page 19 of 20 45° 8° 0° 060606-A 1.27 (0.0500) BSC 0.65 BSC 0.95 0.85 0.75 AD8510/AD8512/AD8513 ORDERING GUIDE Model AD8510ARMZ-REEL 1 AD8510ARMZ1 AD8510AR AD8510ARZ1 AD8510ARZ-REEL1 AD8510ARZ-REEL71 AD8510BR AD8510BR-REEL AD8510BRZ1 AD8510BRZ-REEL1 AD8510BRZ-REEL71 AD8512ARMZ-REEL1 AD8512ARMZ1 AD8512AR AD8512AR-REEL AD8512AR-REEL7 AD8512ARZ1 AD8512ARZ-REEL1 AD8512ARZ-REEL71 AD8512BR AD8512BR-REEL AD8512BR-REEL7 AD8512BRZ1 AD8512BRZ-REEL1 AD8512BRZ-REEL71 AD8513AR AD8513AR-REEL AD8513AR-REEL7 AD8513ARZ1 AD8513ARZ-REEL1 AD8513ARZ-REEL71 AD8513ARU AD8513ARU-REEL AD8513ARUZ1 AD8513ARUZ-REEL1 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02729-0-2/09(I) Rev. I | Page 20 of 20 Package Option RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-14 R-14 R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14 Branding B7A# B7A# B8A# B8A#