STV0190 DUAL 40 MSPS 6-BIT ANALOG TO DIGITAL CONVERTER .. .. . . ADVANCE DATA RESOLUTION 6-BIT MAX. SAMPLING FREQUENCY : 40 MSPS TTL DATA OUTPUTS BUILT-IN SAMPLING AND HOLD CIRCUIT DUAL ADC ON CHIP TO IMPROVE CHANNEL MATCHING APPLICATIONS QPSK DEMODULATION IN A SATELLITE DECODER SO28 (Plastic Micropackage) DESCRIPTION The STV0190 is a dual 40 MSPS 6-bit Analog to Digital converter. It is dedicated to QPSK demodulation in Satellite receiver. The Flash architecture combined with interpolation technic gives the best trade off between power consumption and maximum conversion speed. ORDER CODE : STV0190 VCCO 1 28 D5B OGND 2 27 D4B AGND 3 26 D3B VTO P 4 25 D2B VINA 5 24 D1B VMIDA 6 23 D0B VMIDB 7 22 D5A VINB 8 21 D4A VBOT 9 20 D3A VCCA 10 19 D2A DGND 11 18 D1A VCCD 12 17 D0A CLKIN 13 16 CLKOUT OGND 14 15 VCCO May 1996 This is advance information on a new product no w in development or undergoing evaluation. Details are subject to change without notice. 0190-01.EPS PIN CONNECTIONS 1/7 STV0190 PIN CONFIGURATION Symbol Function Output Buffer Supply Voltage Channel A + B 1 VCCO 2 OGND Output Buffer Ground Channel A + B 3 AGND Analog Ground 4 VTOP Top Reference Voltage 5 VINA Analog Input Channel A 6 VMIDA Reference Voltage DC Coupling Channel A 7 VMIDB Reference Voltage DC Coupling Channel B 8 VINB Analog Input Channel B Bottom Reference Voltage 9 VBOT 10 VCCA 11 DGND Analog Supply Voltage Digital Ground Digital Supply Voltage 12 VCCD 13 CLKIN Clock Input 14 OGND Output Buffer Ground Channel A + B Output Buffer Supply Voltage Channel A + B 15 VCCO 16 CLKOUT 17 to 22 D0A to D5A D0 (LSB) to D5 (MSB) Outputs Channel A 23 to 28 D0B to D5B D0 (LSB) to D5 (MSB) Outputs Channel B 2/7 Clock Output 0190-01.TBL Pin N° STV0190 BLOCK DIAGRAM VCCA VCCD 10 12 VCCO 1 15 S TV0190 VTOP 4 22 D5A 21 D4A VINA 5 TTL OUTP UT LATCHES ADC A 20 D3A 19 D2A 18 D1A 17 D0A VMIDA 6 28 D5B 27 D4B VINB 8 TTL OUTP UT LATCHES ADC B 26 D3B 25 D2B 24 D1B 23 D0B 16 CLKOUT CLOCK DRIVER VMIDB 7 13 CLKIN 3 11 AGND DGND 2 0190-02.EPS VBOT 9 14 OGND 3/7 STV0190 Symbol Toper Parameter Value Unit Analog Supply Voltage 3.1, 3.45 V Digital Supply Voltage 3.1, 3.45 Operating Temperature V o 0, +70 C 0190-02.TBL ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCC = 3.3V, T amb = 0 to 70oC, Full scale 10MHz, 1.5VPP input, 40MSPS, CL = 20pF, unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. 1 1.5 Max. Unit ANALOG INPUT RIN Differential Reference Voltage VTOP - VBOT Variation of Channel A to Channel B (FS) 0.5 LSB VPP 8 mV Input Resistance 20 kΩ Input Bandwidth 3dB 20 MHz DIGITAL OUTPUTS High Logic Voltage 2.4 VCC V Low Logic Voltage 0 0.4 V High Logic Current -4 4 mA mA Low Logic Current Logic Format Analog Input most positive input 63 62 .... 33 32 31 30 .... 1 0 least positive input tPD Output Timing See Figure 1 tV Output Timing See Figure 1 tSKEW Data Output Skew TSK (all outputs, settled within 20%) See Figure 1 tAPER Aperture Delay relative to Data Clock See Figure 1 tR, tF Data Output Rise and Fall Time Digital Output 111111 111110 ............ 100001 100000 011111 011110 ............ 000001 000000 9 ns 1 ns 5 ns 1 ns 4 ns V VIH High Input Voltage 2.0 VCC VIL Low Input Voltage 0 0.8 V IIH High Input Current TBD µA IIL tCL 4/7 Low Input Current TBD Clock Duty Cycle 40 Clock Period See Figure 1 24 µA 60 % ns 0190-03.TBL CLOCK INPUT STV0190 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit CLOCK OUTPUT VOH High Ouput Voltage 2.4 VCC V VOL Low Output Voltage 0 0.4 V IOH High Output Current -4 IOL Low Output Current tCL Clock Duty Cycle 40 Clock Period 24 mA 4 mA 60 % ns REFERENCE LADDER Top Voltage VCC - 0.5 VCC + 0.5 Bottom Voltage DC Bias Restoration Error ZVTOP/VBOT Open input digital output should be 32/64 011111 V V 33/64 100000 Input Impedance 90 Ω Isolation A/B 37 dB CROSSTALK DC ACCURACY Integral non Lin. -0.5 +0.5 LSB Diff. Non Lin. -0.5 +0.5 LSB AC ACCURACY (fIN = 10MHz, FS = 40 MSPS, VIN = 95% FSCALE) THD 5 bits 33 dB THD First 5 Harmony 33 Integral non Lin. -1 A/D Amplifier Response Mismatching dB +1 LSB 0.2 dB 0190-04.TBL Effective Number of Bit SNR Figure 1 : Timing Diagram N N+2 ANALO G S IGNAL N+1 tCL tAPER CLOCK OUT S IGNAL DIGITAL S IGNAL tV Da ta for N Da ta for N+1 Da ta for N+2 0190-03.EPS tP D tS KEW Note : This diagram shows a delay of one clock cycle. Additionnal integer multiple delay periods are acceptable. Output data must be valid on the rising edge of the clock out signal. 5/7 STV0190 TYPICAL APPLICATION VCCA VCCD 100 Ω 100nF VCCO 10µF 100nF 10 VTOP 10µF 10µF 1 12 100nF 15 0.1 µF 4 VMIDA 0.1 µF 0V 6 0V VINA 5 TTL OUTP UT LATCHES ADC A 22 D5A 21 D4A 20 D3A 19 D2A 18 D1A 17 D0A 28 D5B 27 D4B 26 D3B 25 D2B 24 D1B 23 D0B 16 CLKOUT 13 CLKIN VBOT 0V VINB 7 0.1 µF 100 Ω 0.1 µF 9 VMIDB 0V 8 TTL OUTP UT LATCHES ADC B CLOCK DRIVER S TV0190 6/7 11 AGND DG ND 2 14 O GND 0190-04.EPS 3 STV0190 PM-SO28.EPS PACKAGE MECHANICAL DATA 28 PINS - PLASTIC MICROPACKAGE (SO) Dimensions Millimeters Typ. 0.1 0.35 0.23 Max. 2.65 0.3 0.49 0.32 Min. Inches Typ. 0.004 0.014 0.009 0.5 Max. 0.104 0.012 0.019 0.013 0.020 o 45 (Typ.) 17.7 10 18.1 10.65 0.697 0.394 1.27 16.51 7.4 0.4 0.713 0.419 0.050 0.65 7.6 1.27 0.291 0.016 0.299 0.050 SO28TBL A a1 b b1 C c1 D E e e3 F L S Min. o 8 (Max.) Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to the I2C Standard Specifications as defined by Philips. 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