SiI 150A ® PanelLink Digital Transmitter July 2000 General Description Features As the universal transmitter, SiI 150A uses PanelLink Digital technology to support displays ranging from VGA to SXGA (25-112 MHz). The SiI 150A transmitter supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode, and also features an inter-pair skew tolerance up to 1 full input clock cycle. An advanced on-chip jitter filter is also added to extend tolerance to VGA clock jitter. Since all PanelLink products are designed on scaleable CMOS architecture to support future performance requirements while maintaining the same logical interface, system designers can be assured that the interface will be fixed through a number of technology and performance generations. PanelLink Digital technology simplifies PC design by resolving many of the system level issues associated with high-speed digital design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. • • • • • • SiI 150A Pin Diagram CONFIG. PINS RESERVED RESERVED RESERVED VCC GND AGND TXC- TXC+ AVCC AGND AVCC TX0- TX0+ AGND TX1- TX1+ AVCC TX2- TX2+ AGND DIO23 DIO22 DIO21 PD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 25 PIXS DIO19 52 24 EDGE DIO18 53 23 RESERVED DIO17 54 22 RESERVED DIO16 55 21 RESERVED VCC 56 20 RESERVED GND 57 19 PGND1 DIO15 58 18 PVCC1 DIE[23:0] DIO[23:0] DE CTL1 CTL2 CTL3 IVCC 16 DIE0 EDGE PIXS DIE2 DIO10 63 SiI150A 13 DIE3 DIO9 64 1 0 0- P i n T Q F P 12 DIE4 (Top View) Revision C 92 93 94 95 96 97 98 99 100 DIE20 DIE19 DIE18 DIE17 DIE16 IVCC DIE15 DIE14 INPUT CLOCK CONTROLS DIE21 DIE13 91 1 DIE22 75 90 DIE12 DIO0 DIE23 2 89 74 GND DIE11 DIO1 88 3 VCC 73 87 DIE10 DIO2 RESERVED 4 86 72 PGND2 DIE9 DIO3 85 5 PVCC2 71 84 DIE8 DIO4 CTL1 6 83 70 CTL2 GND DIO5 82 7 CTL3 69 81 VCC DIO6 IVCC 8 80 68 IDCK DIE7 DIO7 79 9 GND 67 78 DIE6 GND DE DIE5 10 76 11 77 65 66 VSYNC DIO8 IVCC GPI PLL Encoder 0 Tx0+ Tx0 Tx0- Data Capture C T L 1 Logic IDCK Encoder 1 Tx1+ Tx1 Tx1- DATA Jitter Filter Encoder 2 Tx2+ Tx2 Tx2- TxC+ PLL TxC TxC- EVEN 8-bits GREEN DIE1 14 EVEN 8-bits BLUE 17 15 VSYNC CTL3 60 62 DATA HSYNC CTL2 59 61 24 DATA DIO13 DIO11 24 HSYNC VSYNC DIO14 DIO12 Swing Control EXT_SWING PLL DIO20 HSYNC ODD 8-bits RED ODD 8-bits GREEN EXT_SWING Functional Block Diagram DIFFERENTIAL SIGNAL ODD 8-bits BLUE Scaleable Bandwidth: 25-112 MHz (VGA to SXGA) Low Power: 3.3V core operation & power-down mode High Skew Tolerance: 1 full input clock cycle (9ns at 108 MHz) Flexible panel interface: single or dual pixel in at up to 24-bits Cable Distance Support: over 5m with twisted-pair, fiber-optics ready Compliant with DVI 1.0 (DVI is backwards TM compatible with VESA® P&D and DFP) EVEN 8-bits RED Subject to Change without Notice Silicon Image, Inc. SiI 150A SiI/DS-0006-C Absolute Maximum Conditions Note: Permanent device damage may occur if absolute maximum conditions are exceeded. Functional operation should be restricted to the conditions described under Normal Operating Conditions. Symbol Parameter Min Typ Max Units VCC Supply Voltage 3.3V -0.3 4.0 V VI Input Voltage -0.3 VCC+ 0.3 V VO Output Voltage -0.3 VCC+ 0.3 V TA Ambient Temperature (with power applied) -25 105 °C TSTG Storage Temperature -40 125 °C PPD Package Power Dissipation 1 W Normal Operating Conditions Symbol VCC VCCN TA Parameter Supply Voltage Supply Voltage Noise Ambient Temperature (with power applied) Min 3.00 Typ 3.3 0 25 Max 3.6 100 70 Units V mVP-P °C DC Digital I/O Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions Min VIH High-level Input Voltage 2 VIL Low-level Input Voltage VOH High-level Output Voltage 2.4 VOL Low-level Output Voltage VCINL Input Clamp Voltage1 ICL = -18mA VCIPL Input Clamp Voltage1 ICL = 18mA VCONL Output Clamp Voltage1 ICL = -18mA VCOPL Output Clamp Voltage1 ICL = 18mA IIL Input Leakage Current -10 Note: 1 Typ Max 0.8 0.4 GND -0.8 IVCC + 0.8 GND -0.8 OVCC + 0.8 10 Units V V V V V V V V µA Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions for a pulse of greater than 3 ns or one third of the clock cycle. DC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions VOD Differential Voltage RLOAD = 50 Ω Single ended peak to peak amplitude REXT_SWING = 510 Ω REXT_SWING = 680 Ω VDOH Differential High-level Output Voltage1 IDOS Differential Output Short Circuit Current1 VOUT = 0 V IPD Power-down Current2 ICCT Transmitter Supply Current IDCK = 112 MHz, 1-pixel/clock mode, REXT_SWING = 510Ω, IVCC = VCC, Typical Pattern3 IDCK = 112 MHz, 1-pixel/clock mode, REXT_SWING = 510Ω, IVCC = VCC, Worst Case Pattern4 Note: 1 Guaranteed by design. 2 Assumes all inputs to the transmitter are not toggling. 3 The Typical Pattern contains a gray scale area, checkerboard area, and text. 4 Black and white checkerboard pattern, each checker is one pixel wide. Revision C 2 Min Typ Max Units 510 310 550 370 AVCC 590 430 70 5 9 80 mV mV V µA mA mA 80 90 mA Subject to Change without Notice Silicon Image, Inc. SiI 150A SiI/DS-0006-C AC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter TCIP IDCK Period, 1 Pixel/Clock FCIP IDCK Frequency, 1 Pixel/Clock TCIP IDCK Period, 2 Pixels/Clock FCIP IDCK Frequency, 2 Pixels/Clock TCIH IDCK High Time at 112MHz TCIL IDCK Low Time at 112MHz TIJIT Worst Case IDCK Clock Jitter2,3 TSIDF Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to IDCK falling edge THIDF Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from IDCK falling edge TSIDR Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to IDCK rising edge THIDR Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from IDCK rising edge TDDF VSYNC, HSYNC, and CTL[3:1] Delay from DE falling edge1 TDDR VSYNC, HSYNC, and CTL[3:1] Delay to DE rising edge1 THDE DE high time1 TLDE DE low time1 SLHT Small Swing Low-to-High Transition Time SHLT Small Swing High-to-Low Transition Time Notes: 1 2 3 Conditions Min 8.93 20 17.8 10 4 4 Typ Max 50 112 100 56 EDGE = 0 1 Units ns MHz ns MHz ns ns ns ns EDGE = 0 3 ns EDGE = 1 1 ns EDGE = 1 3 ns TCIP TCIP ns ns ns ns 2 8191TCIP CLOAD = 5pF RLOAD = 50Ω REXT_SWING = 510Ω CLOAD = 5pF RLOAD = 50Ω REXT_SWING = 510Ω 128TCIP 0.25 0.3 0.35 ns 0.25 0.3 0.35 ns Guaranteed by design. Jitter can be estimated by 1) triggering a digital scope at the rising of input clock and 2) measuring the peak to peak time spread of the rising edge of the input clock 1µs after the trigger. Actual jitter tolerance may be higher depending on the frequency of the jitter. Timing Diagrams T CIP T CIH 2.0 V 2.0 V 2.0 V 0.8 V 0.8 V T CIL Figure 1. Clock Cycle/High/Low Times SLHT SHLT 8 0 % V OD 2 0 % V OD Figure 2. Small Swing Transition Times Revision C 3 Subject to Change without Notice Silicon Image, Inc. SiI 150A SiI/DS-0006-C Input Timing 50 % IDCK+/IDCK- 50 % T HIDF T SIDF D[23:0], DE, HSYNC,VSYNC, CTL[3:1] 50 % 50 % T SIDR T HIDR Figure 3. Input Data Setup/Hold Times to IDCK DE DE 0.8 V 0.8 V TDDF TDDR VSYNC, HSYNC, CTL[3:1] VSYNC, HSYNC, CTL[3:1] 0.8 V 0.8 V Figure 4. VSYNC, HSYNC, and CTL[3:1] Delay Times from DE 2.0 V DE T HDE 2.0 V 0.8 V 0.8 V T LDE Figure 5. DE High/Low Times Input Pin Description Pin Name DIE23DIE0 Pin # See SiI 150A Pin Diagram Type In DIO23 – DIO0 See SiI 150A Pin Diagram In IDCK 80 In DE 78 In HSYNC VSYNC CTL1 CTL2 CTL3 76 77 84 83 82 In In In In In Revision C Description Even Input Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode or to the first 24-bit pixel data for 2-pixels/clock mode. Input data is synchronized to input data clock (IDCK). Data can be latched on the rising or the falling edge of IDCK depending on whether EDGE is high or low, respectively. Refer to the TFT and DSTN Signal Mapping application notes (SiI-AN-0008-A and SiI-AN-0007-A, respectively) which tabulate the relationship between the input data to the transmitter and output data from the receiver. Input Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode. In 1-pixel/clock mode, these inputs are a don’t care. Recommendation is to tie them low for lower power consumption. Input data is synchronized to input data clock (IDCK). Data can be latched on the rising or the falling edge of IDCK depending on whether EDGE is high or low, respectively. Refer to the TFT and DSTN Signal Mapping application notes (SiI-AN-0008-A and SiI-AN-0007-A, respectively) which tabulate the relationship between the input data to the transmitter and output data from the receiver. Input Data Clock. Input data and control signals can be valid either on the falling or the rising edge of IDCK as selected by the EDGE pin. Input Data Enable. This signal qualifies the active data area. DE is always required by the transmitter and must be high during active display time and low during blanking time. Horizontal Sync input control signal. Vertical Sync input control signal. General input control signal 1. General input control signal 2. General input control signal 3. 4 Subject to Change without Notice Silicon Image, Inc. SiI 150A SiI/DS-0006-C Configuration Pin Description Pin Name EDGE Pin # 24 Type In PIXS 25 In Description Data/Control Latching Edge. A low level indicates that all input signals (DIE/DIO[23:0], HSYNC, VSYNC, DE, and CTL[3:1]) are latched on the falling edge of IDCK, while a high level (3.3V) indicates that all input signals are latched on the rising edge of IDCK. Pixel Select. A low level indicates one pixel (up to 24-bits) per clock mode using DIE[23:0]. A high level (3.3V) indicates two pixels (up to 48-bits) per clock mode using DIE[23:0] for the first pixel and DIO[23:0] for the second pixel. Power Management Pin Description Pin Name PD Pin # 26 Type In Description Power Down (active low). A high level (3.3V) indicates normal operation and a low level (GND) indicates power down mode. During power down mode, all data (DIE/DIO[23:0]), data enable (DE), clock (IDCK) and control signals (HSYNC, VSYNC, CTL[3:1]), input buffers are disabled, all output buffers are tri-stated, and all internal circuitry is powered down. Differential Signal Data Pin Description Pin Name TX0+ TX0TX1+ TX1TX2+ TX2TXC+ TXCEXT_SWING Pin # 40 39 43 42 46 45 35 34 32 Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Description TMDS Low Voltage Differential Signal output data pairs. TMDS Low Voltage Differential Signal output data pairs. Voltage Swing Adjust. A resistor should tie this pin to AVCC. The amplitude of the voltage swing is determined by this resistance. For remote display applications, 510Ω is recommended. For notebook computers, 680Ω is recommended. Reserved Pin Description Pin Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Pin # 20 21 22 23 27 28 29 87 Type In In In In In In In In Description Reserved for future use. Must be tied HIGH for normal operation. Reserved for future use. Must be tied LOW for normal operation. Reserved for future use. Must be tied HIGH for normal operation. Reserved for future use. Must be tied HIGH for normal operation. Reserved for future use. Must be tied HIGH for normal operation. Reserved for future use. Must be tied HIGH for normal operation. Reserved for future use. Must be tied HIGH for normal operation. Reserved for future use. Must be tied HIGH for normal operation. Power and Ground Pin Description Pin Name VCC GND IVCC AVCC AGND PVCC1 PVCC2 PGND1 Pin # 8,30,56,88 7,31,57,67,79,89 17,66,81,98 36,38,44 33,37,41,47 18 85 19 Type Power Ground Power Power Ground Power Power Ground PGND2 86 Ground Description Digital Core VCC, must be set to 3.3V. Digital GND. Input VCC, must be set to 3.3V. Analog VCC, must be set to 3.3V. Analog GND. PLL Analog VCC, must be set to 3.3V. PLL Analog VCC, must be set to 3.3V. PLL Analog GND. PGND1 should not connected to the GROUND plane. They plane. PLL Analog GND. PGND1 should not connected to the GROUND plane. They plane. be directly connected to PGND2 before being should be connected individually to the GROUND be directly connected to PGND2 before being should be connected individually to the GROUND Application Information To obtain the most updated Application Notes and other useful information for your design application, please visit the Silicon Image web site at www.siimage.com, or contact your local Silicon Image sales office. Revision C 5 Subject to Change without Notice Silicon Image, Inc. SiI 150A SiI/DS-0006-C Package Dimensions 100-pin TQFP Package Dimensions JEDEC Code MS-026 AED Lead Length 1.00mm Lead Width 0.20mm 100-pin Plastic TQFP Package Height 1.20mm max. SiI150ACT100 LNNNNN.NLLL XXYY X.XX Footprint 16.00mm Device # Lot # Date Code # SiI Rev. # Body Size 14.00mm 3DQHO/LQN ® 12.00mm Lead Pitch 0.50mm Body Thickness 1.05 mm max. Clearance 0.15mm max. 12.00mm Body Size 14.00mm Footprint 16.00mm Ordering Information Part Number SiI150ACT100 Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the express written permission of Silicon Image, Inc. Trademark Acknowledgment Silicon Image, the Silicon Image logo, PanelLink and the PanelLink logo are trademarks or registered trademarks of Silicon Image, Inc. All other trademarks are the property of their respective holders. Disclaimer This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. © 2000 Silicon Image, Inc. 7/00 SiI/DS-0006-C Silicon Image, Inc. 1060 E. Arques Ave Sunnyvale, CA 94086 USA Revision C Tel: 408-616-4000 Fax: 408-830-9530 E-Mail: [email protected] www.siimage.com Web: www.panellink.com 6 Subject to Change without Notice