INTEL AS87C196CB20

87C196CB 20 MHz Advanced 16-Bit
CHMOS Microcontroller with Integrated
CAN 2.0
Automotive
Production Datasheet
Product Features
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1.
–40°C to +125°C Ambient
High Performance CHMOS 16-Bit CPU
Up to 56 Kbytes of On-Chip EPROM
Up to 1.5 Kbyte of On-Chip Register RAM
Up to 512 Bytes of Additional RAM
(Code RAM)
Register-Register Architecture
8 Channel/10-Bit A/D with Sample/Hold
38 Prioritized Interrupts
Up to Seven 8-Bit (56) I/O Ports
Full Duplex Serial I/O Port with Dedicated
Baud Rate Generator
Interprocessor Communication Slave Port
Oscillator Fail Detection Circuitry
15 Message Objects of 8 Bytes Data
Length
Up to 16 Mbyte Linear Address Space
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High Speed Peripheral Transaction Server
(PTS)
Two Dedicated 16-Bit High-Speed
Compare Registers
10 High Speed Capture/Compare (EPA)
Full Duplex Synchronous Serial I/O Port
(SSIO)
Two Flexible 16-Bit Timer Counters
Flexible 8-/16-Bit External Bus
(Programmable)
Programmable Bus (HLD/HLDA)
1.4 µs 16 x 16 Multiply
2.4 µs 32/16 Divide
20 MHz Operation1
Supports CAN (Controller Area Network)
Specification 2.0
16 MHz standard; 20 MHz is speed premium.
Notice: This document contains information on products in full production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
Order No: 272405-007
August 2004
87C196CB - Automotive
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
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intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 87C196CB - Automotive may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
PO Box 5937
Denver CO 80217-9808
call 1-800-548-4725
Copyright © Intel Corporation 1997, 2004
*Third-party brands and names are the property of their respective owners.
ii
Production Datasheet
87C196CB - Automotive
Contents
1.0
Introduction ................................................................................................................... 1
2.0
Block Diagram...............................................................................................................2
3.0
Process Information ...................................................................................................... 3
4.0
Pin Descriptions ............................................................................................................6
5.0
Electrical Characteristics............................................................................................. 10
5.1
5.2
5.3
5.4
6.0
DC Characteristics ........................................................................................ 10
5.1.1 87C196CB - Automotive Additional Bus Timing Modes ................... 12
5.1.1.1 MODE 3............................................................................... 12
5.1.1.2 MODE 0............................................................................... 12
AC Characteristics......................................................................................... 12
5.2.1 Test Conditions ................................................................................ 12
5.2.2 87C196CB - Automotive Timings ..................................................... 15
5.2.3 87C196CB Timings .......................................................................... 16
5.2.4 87C196CB - Automotive Timings ..................................................... 17
5.2.5 87C196CB - Automotive AC Characteristics - Slave Port ................ 18
5.2.6 Explanation of AC Symbols.............................................................. 22
EPROM Specifications .................................................................................. 23
5.3.1 AC EPROM Programming Characteristics....................................... 23
5.3.2 EPROM Programming Waveforms .................................................. 24
AC Characteristics - Serial Port - Shift Register Mode.................................. 26
5.4.1 A/D Characteristics........................................................................... 27
5.4.1.1 A/D Converter Specification ................................................ 27
Datasheet Revision History......................................................................................... 30
Production Datasheet
iii
87C196CB - Automotive
Figures
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20
21
87C196CB - Automotive Block Diagram ..........................................................2
The 87C196CB - Automotive Family Nomenclature ........................................3
84-Pin PLCC x87C196CB Diagram .................................................................4
100-Pin QFP x87C196CB Diagram .................................................................5
Chip Configuration Registers ...........................................................................9
87C196CB ICC vs Frequency .........................................................................11
87C196CB - Automotive System Bus Timing ................................................15
87C196CB - Automotive Ready Timings (One Wait State)............................16
87C196CB Buswidth Timings ........................................................................16
87C196CB HOLD#/HOLDA# Timings............................................................17
Slave Port Waveform - (SLPL = 0).................................................................18
Slave Port Waveform - (SLPL = 1).................................................................19
Synchronous Serial Port ................................................................................20
External Clock Drive Waveforms ...................................................................21
Input/Output Test Conditions .........................................................................21
Float Test Conditions .....................................................................................22
Slave Programming Mode Data Program Mode with Single Program Pulse .24
Slave Programming Mode in Word Dump or Data Verify Mode
with Auto Increment .......................................................................................24
Slave Programming Mode Timing in Data Program Mode
with Repeated Program Pulse and Auto Increment .......................................25
Waveform - Serial Port - Shift Register Mode ................................................26
AD_TIME 1FAFH:Byte ...................................................................................27
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Device Overview ..............................................................................................1
Thermal Characteristics ...................................................................................3
Pin Descriptions ...............................................................................................6
87C196CB Memory Map..................................................................................8
DC Characteristics (Under Listed Operating Conditions)...............................10
AC Characteristics (Over Specified Operating Conditions)............................12
AC Characteristics (Over Specified Operating Conditions)............................14
8xC196CB HOLD#/HOLDA# Timings (Over Specified Operation Conditions)17
Slave Port Timing - (SLPL = 0, 1, 2, 3) ..........................................................18
Slave Port Timing - (SLPL = 1, 2, 3) ..............................................................19
Normal Master/Slave Operation .....................................................................20
Handshake Operation ....................................................................................20
External Clock Drive.......................................................................................21
Explanation of AC Symbols............................................................................22
AC EPROM Programming Characteristics.....................................................23
DC EPROM Programming Characteristics ....................................................23
Serial Port Timing - Shift Register Mode ........................................................26
10-Bit Mode A/D Operating Conditions ..........................................................27
10-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1) ....28
8-Bit Mode A/D Operating Conditions ............................................................28
8-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1) ......29
19
Tables
iv
Production Datasheet
87C196CB - Automotive
1.0
Introduction
The 87C196CB - Automotive is a member of the MCS® 96 microcontroller family. This device is
based upon the MCS 96 Kx/Jx microcontroller product families with enhancements ideal for
automotive and industrial applications. The 87C196CB - Automotive is the first device in the Kx
family to support networking through the integration of the CAN 2.0 (Controller Area Network)
peripheral on-chip. The 87C196CB offers the highest memory density of the MCS 96
microcontroller family, with 56K of on-chip EPROM, 1.5K of on-chip register RAM, and 512
bytes of additional RAM (Code RAM). In addition, the 87C196CB provides up to 16 Mbyte of
Linear Address Space.
Table 1. Device Overview
Device
Pins/
Package
EPROM
Reg
RAM
Code
RAM
I/O
EPA
SIO
SSIO
CAN
A/D
Addr
Space
87C196CB
84-Pin
PLCC
56K
1.5K
512b
56
10
Y
Y
Y
8
1 Mbyte
87C196CB
100-Pin
QFP
56K
1.5K
512b
60
10
Y
Y
Y
8
16 Mbyte
Production Datasheet
1
87C196CB - Automotive
2.0
Block Diagram
The MCS 96 microcontroller family members are all high-performance microcontrollers with a
16-bit CPU. The 87C196CB is composed of the high-speed (20 MHz) macrocore with up to
16 Mbyte linear address space, 56 Kbytes of program EPROM, up to 1.5 Kbytes of register RAM,
and up to 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this
RAM space. It supports the high-speed, serial communications protocol CAN 2.0, with 15 message
objects of 8 bytes data length, an 8-channel, 10-bit / 3 LSB analog to digital converter with
programmable S/H times, and conversion times < 15 µs at 20 MHz. It has an
asynchronous/synchronous serial I/O port (SIO) with a dedicated 16-bit baud rate generator, an
additional synchronous serial I/O port (SSIO) with full duplex master/slave transceivers, a flexible
timer/counter structure with prescaler, cascading, and quadrature capabilities. There are ten
modularized, multiplexed, high-speed I/O for capture and compare (called Event Processor Array)
with 200 ns resolution and double buffered inputs, and a sophisticated prioritized interrupt
structure with programmable Peripheral Transaction Server (PTS) implementing several channel
modes, including single/burst block transfers from any memory location to any memory location, a
PWM and PWM toggle mode to be used in conjunction with the EPA, and an A/D scan mode.
Figure 1. 87C196CB - Automotive Block Diagram
VREF
ANGND
A/D
Converter
1.5K
Byte
Register
File
S/H
16
CPU
ALU
Interrupt
Controller
Microcode
Engine
Peripheral
Transaction
Server
56K On-chip
EPROM
(optional)
512 Bytes
Internal RAM
Memory
Controller
8
Queue
MUX
16
Port 0
A/D
Port 0
Sync
Serial
Port and
Baud Gen
Port 3
AD0-7
Port 4
AD8-15
Watchdog
Timer
Event
Processor
Array
Serial
Port
Port 6
Port 1
Port 2
Port 6
SSIO
Port 1
EPA
Port 2 /
Hold Control
Timer 1
Timer 2
Port 5
Control
Signals
Baud
Rate
Gen
EPORT
A16-23
CAN 2.0
RXCAN
TXCAN
A4606-01
2
Production Datasheet
87C196CB - Automotive
3.0
Process Information
These devices are manufactured on P629.5, a CHMOS III-E process. Additional process and
reliability information is available in Intel's Components Quality and Reliability Handbook, Order
Number 210997.
All thermal impedance data is approximate for static air conditions at 1 W of power dissipation.
Values change depending on operation conditions and application. See the Intel Packaging
Handbook (order number 240800) for a description of Intel's thermal impedance test methodology.
Figure 2. The 87C196CB - Automotive Family Nomenclature
xA xX 8 7 C 1 9 6 C B 20
Frequency Designation:
20 = 20 MHz
No Mark = 16 MHz
Product Designation
Product Family
CHMOS Technology
Program Memory Options:
7 = EPROM, OTP
Package Type Options:
N
x = PLCC (plastic leaded chip carrier)
S
x = QFP (Quad Flatpack)
Temperature and Burn-in Options:
A
x = -40˚C to +125˚C
ambient with
Intel Standard Burn-in
A4610-01
Table 2. Thermal Characteristics
Device and Package
xx87C196CB
(84-Lead PLCC Package)
ΘJA
ΘJC
35°C/W
11°C/W
NOTES:
1. ΘJA = Thermal resistance between junction and the surrounding environment (ambient) measurements are
taken 1 ft. away from case in air flow environment.
ΘJV = Thermal resistance between junction and package face (case).
2. All values of ΘJA and ΘJC may fluctuate depending on the environment (with or without airflow, and how
much airflow)
3. and device power dissipation at temperature of operation. Typical variations are ± 2°C/W.
4. Values listed are at a maximum power dissipation of 1 W.
5. To address the fact that many of the package prefix variables have changed, all package prefix variables in
this document are now indicated with an "x".
Production Datasheet
3
87C196CB - Automotive
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1
84
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P5.2 / WR#
P5.5 /BHE#
P5.3 / RD#
VPP
P5.0 / ALE
P5.1 / INST
P5.6 / READY
P5.4 / SLPINT
EP3.3 / A19
VCC
VSS1
VSS
RXCAN
TXCAN
XTAL1
XTAL2
P6.7 / SD1
P6.6 / SC1
P6.5 / SD0
P6.4 / SC0
VCC
Figure 3. 84-Pin PLCC xx87C196CB Diagram
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20
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25
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30
31
32
AN87C196CB
xx
84-Lead PLCC
View of component as
mounted on PC board
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65
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62
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60
59
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56
55
54
PLLEN
P6.3 / T1DIR
P6.2 / T1CLK
P6.1 / EPA9
P6.0 / EPA8
P1.0 / EPA0
P1.1 / EPA1
P1.2 / EPA2
P1.3 / EPA3
P1.4 / EPA4
P1.5 / EPA5
P1.6 / EPA6
P1.7 / EPA7
VSS1
VCC
VREF
AGND
P0.7 / ACH7
P0.6 / ACH6
P0.5 / ACH5
P0.4 / ACH4
P3.0 / AD0
RESET#
NMI
EA#
VSS1
VCC
VSS
P2.0 / TXD
P2.1 / RXD
P2.2 / EXTINT
P2.3 / INTB#
P2.4 / INTINTOUT#
P2.5 / HLD#
P2.6 / HLDA#
P2.7 / CLKOUT
VCC
VSS1
P0.0 / ACH0
P0.1 / ACH1
P0.2 / ACH2
P0.3 / ACH3
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
P5.7 / BUSW
EP3.1 / A17
EP3.0 / A16
P4.7 / AD15
P4.6 / AD14
P4.5 / AD13
P4.4 / AD12
P4.3 / AD11
P4.2 / AD10
P4.1 / AD9
P4.0 / AD8
VSS1
VCC
P3.7 / AD7
P3.6 / AD6
P3.5 / AD5
P3.4 / AD4
P3.3 / AD3
P3.2 / AD2
P3.1 / AD1
EP3.2 / A18
A4548-01
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Production Datasheet
87C196CB - Automotive
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81
AD18 / EPORT.2
AD1 / P3.1
AD2 / P3.2
AD3 / P3.3
AD4 / P3.4
AD5 / P3.5
AD6 / P3.6
AD7 / P3.7
VCC
VSS1
AD8 / P4.0
AD9 / P4.1
AD10 / P4.2
AD11 / P4.3
AD12 / P4.4
AD13 / P4.5
AD14 / P4.6
AD15 / P4.7
A16 / EPORT.0
A17 / EPROT.1
Figure 4. 100-Pin QFP xx87C196CB Diagram
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2
3
4
5
6
7
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9
10
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25
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27
28
29
30
xx
AS87C196CB
View of component as
mounted on PC board
80
79
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51
P5.7 / BUSWIDTH
P5.2 / WR# / WRL#
P5.5 / BHE# / WRH#
P5.3 / RD#
A20 / EPORT.4
A21 / EPORT.5
A22 / EPORT.6
VPP
A23 / EPORT.7
P5.0 / ADV# / ALE
P5.1 / INST / SLPCS#
P5.6 / READY
P5.4 / SLPINT
A19 / EPORT.3
NC
VCC
NC
VSS1
VSS
NC
RXCAN
TXCAN
XTAL1
XTAL2
NC
P6.7 / SD1
P6.6 / SC1
P6.5 / SD0
P6.4 / SC0
VCC
P0.5 / ACH5
P0.6 / ACH6
P0.7 / ACH7
ANGND
VREF
VCC
VSS1
P1.7 / EPA7
P1.6 / EPA6
P1.5 / EPA5
P1.4 / EPA4
P1.3 / EPA3
P1.2 / EPA2 / T2DIR
P1.1 / EPA1
P1.0 / EPA0 / T2CLK
P6.0 / EPA8 / COMP0
P6.1 / EPA9 / COMP1
P6.2 / T1CLK
P6.3 / T1DIR
PLLEN
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
AD0 / P3.0
RESET#
NMI
EA#
VSS1
NC
VCC
NC
VSS
NC
NC
NC
NC
P2.0 / TXD
P2.1 / RXD
P2.2 / EXTINT
P2.3 / BREQ#
NC
P2.4 / INTOUT#
P2.5 / HOLD#
P2.6 / HLDA# / ONCE#
P2.7 / CLKOUT
VCC
VSS1
P0.0 / ACH0
P0.1 / ACH1
P0.2 / ACH2
P0.3 / ACH3
P0.4 / ACH4
A6076-01
Production Datasheet
5
87C196CB - Automotive
4.0
Pin Descriptions
Table 3. Pin Descriptions (Sheet 1 of 2)
Name
6
Description
VCC
Main supply voltage (+5 V).
VSS, VSS1
Digital circuit ground (0 V). There are seven VSS pins, all of which MUST be connected to
a single ground plane.
VREF
Reference for the A/D converter (+5 V). VREF is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
VPP
Programming voltage for the EPROM parts. It should be +12.5 V for programming. It is also
the timing pin for the return from powerdown circuit. Connect this pin with a 1 µF capacitor to
VSS and a 1 MΩ resistor to VCC. If this function is not used, VPP may be tied to VCC.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as VSS.
XTAL1
Input of the oscillator inverter and the internal clock generator.
XTAL2
Output of the oscillator inverter.
RESET#
Reset input to the chip. Input low for at least 16 state times resets the chip. The
subsequent low-to-high transition resynchronizes CLKOUT and commences a 10-state
time sequence in which the PSW is cleared, bytes are read from 2018H, 201AH and
201CH (if enabled) loading the CCBs, and a jump to location 2080H is executed. Input
high for normal operation. RESET# has an internal pullup.
NMI
A positive transition causes a non-maskable interrupt vector through memory location
203EH. If not used, this pin should be tied to VSS. May be used by Intel Evaluation boards.
EA#
Input for memory select (External Access). EA# equal to a high causes memory
accesses to locations 0FF2000H through 0FFFFFH to be directed to on-chip
EPROM/ROM. EA# equal to a low causes accesses to these locations to be directed to
off- chip memory. EA# = +12.5 V causes execution to begin in the Programming Mode.
EA# latched at reset.
PLLEN
Selects between PLL mode or PLL bypass mode. This pin must be either tied high or low.
PLLEN pin = 0, bypass PLL mode. PLLEN pin = 1, places a 4x PLL at the input of the
crystal oscillator. Allows for a low frequency crystal to drive the device
(i.e., 5 MHz = 20 MHz operation).
P6.4-6.7/SSIO
Dual-function I/O ports that have a system function as Synchronous Serial I/O. Two pins
are clocks and two pins are data, providing full duplex capability. Also, LSIO when not
used as SSIO.
P6.3/T1DIR
Dual-function I/O pin. Primary function is that of a bidirectional I/O pin, however, it may
also be used as a TIMER1 Direction input. The TIMER1 increments when this pin is high
and decrements when this pin is low.
P6.2/T1CLK
Dual-function I/O pin. Primary function is that of a bidirectional I/O pin, however may also
be used as a TIMER1 Clock input. The TIMER1 increments or decrements on both
positive and negative edges of this pin.
P6.0-6.1/EPA8-9
Dual-function I/O port pins. Primary function is that of bidirectional I/O. System function is
that of High Speed capture and compare.
P5.7/BUSWIDTH
Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin
dynamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low, an
8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is “0” and
CCR1 bit 2 is “1”, all bus cycles are 8-bit, if CCR bit 1 is “1” and CCR1 bit 2 is “0”, all bus
cycles are 16-bit. CCR bit 1 = “0” and CCR1 bit 2 = “0” is illegal. Also an LSIO pin when
not used as BUSWIDTH.
P5.6/READY
Ready input to lengthen external memory cycles, for interfacing with slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner.
If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait
state mode until the next positive transition in CLKOUT occurs with READY high. When
external memory is not used, READY has no effect. The max number of wait states inserted
into the bus cycle is controlled by the CCR/CCR1. Also an LSIO if READY is not selected.
Production Datasheet
87C196CB - Automotive
Table 3. Pin Descriptions (Sheet 2 of 2)
Name
Description
P5.5/BHE#/WRH#
Byte High Enable or Write High output, as selected by the CCR. BHE# = 0 selects the
bank of memory that is connected to the high byte of the data bus. A0 = 0 selects the
bank of memory that is connected to the low byte. Thus accesses to a 16-bit wide
memory can be to the low byte only (A0 = 0, BHE# = 1), to the high byte only (A0 = 1,
BHE# = 0) or both bytes (A0 = 0, BHE# = 0). If the WRH# function is selected, the pin
goes low if the bus cycle is writing to an odd memory location. BHE#/WRH# is only valid
during 16-bit external. Also an LSIO pin when not BHE/WRH#.
P5.4/SLPINT
Dual-function I/O pin. As a bidirectional port pin or as a system function. The system
function is a Slave Port Interrupt Output Pin.
P5.3/RD#
Read signal output to external memory. RD# is active only during external memory reads
or LSIO when not used as RD#.
P5.2/WR#/WRL#
Write and Write Low output to external memory, as selected by the CCR, WR# goes low
for every external write, while WRL# goes low only for external writes where an even
byte is being written. WR#/WRL# is active during external memory writes. Also an LSIO
pin when not used as WR#/WRL#.
P5.1/INST
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is active only during external memory
fetches, during internal EPROM fetches INST is held low. Also LSIO when not INST.
P5.0/ALE/ADV#
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV#, it goes inactive (high) at the end of the bus cycle. ADV# can be used as a chip
select for external memory. ALE/ADV# is active only during external memory accesses.
Also LSIO when not used as ALE.
PORT3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
P2.7/CLKOUT
Output of the internal clock generator. The frequency is the oscillator frequency.
CLKOUT has a 50% duty cycle. Also LSIO pin when not used as CLKOUT.
P2.6/HLDA#
Bus Hold Acknowledge. Active-low output indicates that the bus controller has
relinquished control of the bus. Occurs in response to an external device asserting the
HLD# signal. Also LSIO when not used as HLDA#.
P2.5/HLD#
Bus Hold. Active-low signal indicates that an external device is requesting control of the
bus. Also LSIO when not used as HLD#.
P2.4/INTOUT#
Interrupt Output. This active-low output indicates that a pending interrupt requires use of
the external bus. Also LSIO when not used as INTOUT#.
P2.3/BREQ#
Bus Request. This active-low output signal is asserted during a HOLD cycle when the bus
controller has a pending external memory cycle. Also LSIO when not used as BREQ#.
P2.2/EXTINT
A positive transition on this pin causes a maskable interrupt vector through memory
location 203CH. Also LSIO when not used as EXTINT.
P2.1/RXD
Receive data input pin for the Serial I/O port. Also LSIO if not used as RXD.
P2.0/TXD
Transmit data output pin for the Serial I/O port. Also LSIO if not used as TXD.
PORT 1/EPA0–7
Dual-function I/O port pins. Primary function is that of bidirectional I/O. System function is
that of High Speed capture and compare. EPA0 and EPA2 have another function of
T2CLK and T2DIR of the TIMER2 timer/counter.
PORT 0/ACH0–7
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter. These pins are also used as inputs to
EPROM parts to select the Programming Mode.
EPORT
8-bit bidirectional standard and I/O Port. These bits are shared with the extended
address bus, A16–A19 for CB PLCC, A16–A23 for CB QFP. Pin function is selected on a
per pin basis.
TXCAN
Push-pull output to the CAN bus line.
RXCAN
High impedance input-only from the CAN bus line.
Production Datasheet
7
87C196CB - Automotive
Table 4. 87C196CB Memory Map
Address
Description
Notes
FFFFFFH
FF2080H
Program Memory - Internal EPROM or External Memory (Determined by EA#
Pin)
FF207FH
FF2000H
Special Purpose Memory - Internal EPROM or External Memory (Determined
by EA# Pin)
FF1FFFH
FF0600H
External Memory
FF05FFH
FF0400H
Internal RAM (Identically Mapped into 00400H–005FFH)
FF03FFH
FF0100H
External Memory
FF00FFH
FF0000H
Reserved for ICE
FEFFFFH
0F0000H
Overlaid Memory (External)-Accesses into Memory Ranges 0F0000H to
FEFFFFH will Overlay Page 15 (0FH) for CB QFP package-External Memory.
0EFFFFH
010000H
900 Kbytes External Memory
00FFFFH
002080H
External Memory or Remapped OTPROM (Program Memory)
00207FH
002000H
External Memory or Remapped OTPROM (Special Purpose Memory)
001FFFH
001FE0H
Memory Mapped Special Function Registers (SFR's)
001FDFH
001F00H
Internal Peripheral Special Function Registers (SFR's)
001EFFH
001E00H
Internal CAN Peripheral Memory
001DFFH
001C00H
Internal Register RAM
001BFFH
000600H
External Memory
0005FFH
000400H
Internal RAM (Code RAM) (Address with Indirect or Indexed Modes)
0003FFH
000100H
Register RAM – Upper Register File (Address with Indirect or Indexed Modes or
through Windows.)
(2)
0000FFH
000018H
Register RAM – Lower Register File. (Address with Direct, Indirect, or Indexed
Modes.)
(2)
000017H
000000H
CPU SFR's
(5)
(1)
(1,3)
(5)
(5)
(4)
NOTES:
1. These areas are mapped internal EPROM if the REMAP bit (CCB2.2) is set and EA# = 5 V. Otherwise they
are external memory.
2. Code executed in locations 0000H to 003FFH is forced external.
3. Reserved memory locations must contain 0FFH unless noted.
4. Reserved SFR bit locations must be written with 0.
5. Refer to 8XC196CB Supplement to 8xC196NT User's Manual for SFR, CAN and Paging Descriptions.
8
Production Datasheet
87C196CB - Automotive
Figure 5. Chip Configuration Registers
CCB (2018H : Byte)
CCB1 (201AH : Byte)
0
PD
=
“1” Enables Powerdown
0
CCR2
=
“1” Fetch CCB2
1
BW0
=
See Table
1
IRC2
=
See Table
2
WR
=
“1” = WR#/BHE - “0” = WRL#/WRH# 2
BW1
=
See Table
3
ALE
=
“1” = ALE - “0” = ADV
3
WDE
=
“0” = Always Enabled
4
IRC0
=
1
=
Reserved Must Be “1”
5
IRC1
=
5
0
=
Reserved Must Be “0”
6
LOC0
=
6
MEMSEL0
=
See Table
7
LOC1
=
} See Table
} See Table
4
7
MEMSEL1
=
See Table
CCB2 (201CH : Byte)
LOC1
LOC0
0
0
0
1
1
1
0
0
=
Reserved Must Be “0”
1
MODE16
=
2
REMAP
=
3
1
=
Select 16-Bit or 24-Bit Mode
“0”–Select EPROM/CODERAM in Segment 0FFH only
“1”–Select Both Segment 0FFH and Segment 00H
Reserved Must Be “1”
4
1
=
Reserved Must Be “1”
5
1
=
Reserved Must Be “1”
6
1
=
Reserved Must Be “1”
7
1
=
Reserved Must Be “1”
}
Function
IRC2
IRC1
IRC0
Read and Write Protected
0
0
0
Zero Wait States
Write Protected Only
1
0
0
1 Wait State
0
Read Protected Only
1
0
1
2 Wait States
1
No Protection
1
1
0
3 Wait States
1
1
1
INFINITE
MSEL1
MSEL0
0
0
0
1
1
1
Mode 0
(1-Wait KR):
“CB” Bus Timing Mode
Max Wait States
BW1
BW0
Bus Width
Mode 0 (1-Wait KR)
0
0
ILLEGAL
Reserved
0
1
16-Bit Only
0
Reserved
1
0
8-Bit Only
1
Mode 3 (KR)
1
1
BW Pin Controlled
Designed to be similar to the 87C196KR bus timing with 1 automatic wait state.
See AC Timings section for actual timings data.
Mode 3 (KR):
Designed to be similar to the 87C196KR bus timing.
See AC Timings section for actual timings data.
Production Datasheet
9
87C196CB - Automotive
5.0
Electrical Characteristics
NOTICE: This is a production data sheet. The specifications are subject to change without notice. Verify with
your local Intel sales office that you have the latest
datasheet before finalizing a design.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
–60°C to +150°C
Voltage from VPP or EA# to
VSS or ANGND ........................... –0.5 V to +13.0 V
*WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause
permanent damage. These are stress ratings
only. Operation beyond the “Operating
Conditions” is not recommended and extended
exposure beyond the “Operating Conditions”
may affect device reliability.
Voltage from any other pin to
VSS or ANGND ........................... –0.5 V to +7.0 V
This includes VPP on ROM and CPU devices.
Power Dissipation............................. 1.0 W
OPERATING CONDITIONS
TA (Ambient Temperature Under Bias)–40°C to +125°C
VCC (Digital Supply Voltage)
4.75 V to 5.25 V
VREF (Analog Supply Voltage)
4.75 V to 5.25 V
FOSC (Oscillator Frequency .............. 4 MHz to 20 MHz
NOTE: ANGND and VSS should be nominally at the same
potential.
5.1
DC Characteristics
Table 5. DC Characteristics (Under Listed Operating Conditions) (Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Units
Test
Conditions
100
mA
XTAL1 = 20 MHz
VCC = VPP = VREF= 5.25 V
(While Device in Reset)
ICC
VCC Supply Current
(–40°C to +125°C Ambient)
IREF
A/D Reference Supply
Current
5
mA
IIDLE
Idle Mode Current
35
mA
XTAL1 = 20 MHz
VCC = VPP = VREF = 5.25 V
IPD
Powerdown Mode Current
µA
VCC = VPP = VREF = 5.52 V
(Notes 5,8)
VIL
Input Low Voltage (All Pins)
VIH
Input High Voltage
VOL
Output Low Voltage
(Outputs Configured as
Complementary)
VOH
Output High Voltage (Output
Configured as
Complementary)
ILI
Input Leakage Current
(Standard Inputs)
50
–0.5
0.3 VCC
V
For PORT0 (Note 7)
0.7 VCC
VCC + 0.5
V
For PORT0 (Note 7)
0.3
0.45
1.5
V
IOL = 200 µA (Note 3)
IOL = 3.2 mA
IOL = 7 mA
V
IOH = –200 µA (Note 3)
IOH = –3.2 mA
IOH = –7 mA
µA
VSS < VIN < VCC
VCC – 0.3
VCC – 0.7
VCC – 1.5
±10
NOTES:
1.All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to not being
weakly pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SLPINT
(P5.4) and HLDA# (P2.6).
2.Standard Input pins include XTAL1, EA#, RESET# and Port 1/2/5/6 when setup as inputs.
3.All Bidirectional I/O pins when configured as Outputs (Push/Pull).
4.Device is Static and should operate below 1 Hz, but only tested down to 4 MHz.
5.Typicals are based on limited number of samples and are not guaranteed. The values listed are at room
temperature and VREF = VCC = 5 V.
6.Violating these specifications in reset may cause the device to enter test mode (P5.4 and P2.6).
7.When P0 is used as analog inputs, refer to A/D specifications for this characteristic.
8.For temperatures < 100°C typical is 10 µA.
10
Production Datasheet
87C196CB - Automotive
Table 5. DC Characteristics (Under Listed Operating Conditions) (Sheet 2 of 2)
Symbol
Parameter
Min
ILI1
Input Leaka‘ge Current
(Port 0)
VOH1
SLPINT (P5.4) and
HLDA# (P2.6) Output High
Voltage in RESET#
VOH2
Output High Voltage in
RESET#
CS
Pin Capacitance
(Any Pin to VSS)
RRST
Reset Pullup Resistor
RWPU
Weak Pullup Resistance
Typ
Test
Conditions
Max
Units
±1
µA
VSS < VIN < VREF
2
V
IOH = 0.8 mA (Note 6)
VCC – 1
V
IOH = –15 µA (Note 1)
pF
FTEST = 1 MHz (Note 5)
10
65 K
180 K
150 K
Ω
Ω
(Note 5)
NOTES:
1.All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to not being
weakly pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SLPINT
(P5.4) and HLDA# (P2.6).
2.Standard Input pins include XTAL1, EA#, RESET# and Port 1/2/5/6 when setup as inputs.
3.All Bidirectional I/O pins when configured as Outputs (Push/Pull).
4.Device is Static and should operate below 1 Hz, but only tested down to 4 MHz.
5.Typicals are based on limited number of samples and are not guaranteed. The values listed are at room
temperature and VREF = VCC = 5 V.
6.Violating these specifications in reset may cause the device to enter test mode (P5.4 and P2.6).
7.When P0 is used as analog inputs, refer to A/D specifications for this characteristic.
8.For temperatures < 100°C typical is 10 µA.
Figure 6. 87C196CB ICC vs Frequency
100
Active ICC Max = 100 mA
90
Active ICC = 83 mA
80
ICC = [mA]
70
60
50
40
Idle Max = 35 mA
30
Idle ICC = 28 mA
20
10
0
2
8
14
20
A5863-01
Production Datasheet
11
87C196CB - Automotive
5.1.1
87C196CB - Automotive Additional Bus Timing Modes
The 87C196CB - Automotive device has two bus timing modes for external memory interfacing.
5.1.1.1
MODE 3
Mode 3 is the standard timing mode. Use this mode for systems that emulate the 87C196KR bus
timings.
5.1.1.2
MODE 0
Mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus
cycles.
5.2
AC Characteristics
5.2.1
Test Conditions
• Capacitive load on all pins = 100 pF
• Rise and Fall Times = 10 ns
Table 6. AC Characteristics (Over Specified Operating Conditions) (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
The 87C196CB - Automotive Will Meet These Specifications
FXTAL
Frequency on XTAL1
4
20
MHz (1)
TOSC
TXHCH
XTAL1 Period (1/FXTAL)
50
250
ns
XTAL1 High to CLKOUT High or Low
20
110
ns
TOFD
Clock Failure to Reset Pulled Low
4
40
µs (6)
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
TCLLH
2TOSC
ns (2)
TOSC–10
TOSC+15
ns
CLKOUT Low to ALE/ADV High
–15
10
ns
TLLCH
ALE/ADV# Low to CLKOUT High
–20
15
ns
TLHLH
ALE/ADV# Cycle Time
TLHLL
ALE/ADV# High Time
TOSC–10
TAVLL
Address Valid to ALE Low
TOSC–15
ns
TLLAX
Address Hold after ALE/ADV# Low
TOSC–40
ns
4TOSC
ns (2,5)
TOSC+10
ns
NOTES:
1.Testing performed at 4 MHz, however, the device is static by design and typically operates below 1 Hz.
2.Typical specifications, not guaranteed.
3.Assuming back-to-back bus cycles.
4.8-bit bus only.
5.If wait states are used, add 2TOSC x n = number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2TOSC to specification.
6.TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is
enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit
enables oscillator fail detection.
12
Production Datasheet
87C196CB - Automotive
Table 6. AC Characteristics (Over Specified Operating Conditions) (Sheet 2 of 2)
Symbol
Parameter
TLLRL
ALE/ADV# Low to RD# Low
TRLCL
RD Low to CLKOUT Low
TRLRH
RD# Low Period
TRHLH
RD# High to ALE/ADV# High
TRLAZ
RD# Low to Address Float
Min
Max
TOSC–30
–8
ns
20
TOSC–10
TOSC
Units
ns
ns (5)
TOSC+25
ns (3)
5
ns
TOSC–10
TLLWL
ALE/ADV# Low to WR# Low
ns
TCLWL
CLKOUT Low to WR# Low
–5
TQVWH
Data Valid before WR# High
TOSC–23
TCHWH
CLKOUT High to WR# High
–10
TWLWH
WR# Low Period
TOSC–20
ns (5)
TWHQX
Data Hold after WR# High
TOSC–25
ns
TWHLH
WR# High to ALE/ADV# High
TOSC–10
TWHBX
BHE#, INST Hold after WR# High
TOSC–10
ns
TWHAX
AD8-15 Hold after WR# High
TOSC–30
ns (4)
TRHBX
BHE#, INST Hold after RD# High
TOSC–10
ns
TRHAX
AD8-15 Hold after RD# High
TOSC–30
ns (4)
25
ns
ns
15
TOSC+15
ns
ns (3)
NOTES:
1.Testing performed at 4 MHz, however, the device is static by design and typically operates below 1 Hz.
2.Typical specifications, not guaranteed.
3.Assuming back-to-back bus cycles.
4.8-bit bus only.
5.If wait states are used, add 2TOSC x n = number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2TOSC to specification.
6.TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is
enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit
enables oscillator fail detection.
Production Datasheet
13
87C196CB - Automotive
Table 7. AC Characteristics (Over Specified Operating Conditions)
Symbol
Parameter
Min
Max
Units
The System Must Meet These Specifications to work with the 87C196CB - Automotive
TAVYV
Address Valid to READY Setup
2 TOSC–75
ns (3)
TLLYV
ALE Low to READY Setup
2 TOSC–70
ns (3)
TYLYH
Non Ready Time
TCLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to BUSWIDTH Setup
TLLGV
ALE Low to BUSWIDTH Setup
TCLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
3TOSC–55
ns (2)
TRLDV
RD# Active to Input Data Valid
TOSC–30
ns (2)
TCLDV
CLKOUT Low to Input Data Valid
TOSC–50
ns
TRHDZ
End of RD# to Input Data Float
TOSC
ns
TRHDX
Data Hold after RD# High
No Upper Limit
0
ns
TOSC–30
ns (1)
2 TOSC–75
ns (2,3)
TOSC–60
ns (2,3)
ns
0
0
ns
NOTES:
1.If Maximum is exceeded, additional wait states will occur.
2.If wait states are used, add 2 TOSC x n, where n = number of wait states.
3.If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2
TOSC to the specification.
14
Production Datasheet
87C196CB - Automotive
5.2.2
87C196CB - Automotive Timings
Figure 7. 87C196CB - Automotive System Bus Timing
TOSC
XTAL1
TCLCL
TXHCH
CLKOUT
TCLLH
TLLCH
TLHLH
ALE / ADV#
TLHLL
TLLRL
TRLRH
TRLDV
TRHLH
RD#
TRHDZ
TRLAZ
TAVLL
BUS
READ
TRHDX
TLLAX
Data In
Address Out A0 – A15
TAVDV
TLLWL
TWLWH
WR#
TQVWH
BUS
WRITE
Address Out
TWHQX
Data Out
TWHBX or TRHBX
BHE#, INST
BHE, INST Valid
TWHAX or TRHAX
AD8–AD15
Address Out AD8–AD15 Valid 8-Bit Bus Mode
If mode 0 operation is selected, add 2 TOSC to this time.
A5874-01
Production Datasheet
15
87C196CB - Automotive
Figure 8. 87C196CB - Automotive Ready Timings (One Wait State)
TOSC
XTAL1
TXHCH
CLKOUT
TCLLH
TLLCH
TCLYX
TCLCL
(max)
ALE
TCLYX
TLLYV
(min)
READY
TAVYV
TRLRH + 2 TOSC
RD#
TAVDV + 2 TOSC
BUS READ
TRHDX
Address Out
Data In
TWLWH + 2 TOSC
WR#
TQVWH + 2 TOSC
BUS WRITE
Data Out
Address Out
If mode 0 selected, one wait state is always added. If additional wait states are required,
add 2 TOSC to these specifications.
A5876-01
5.2.3
87C196CB Timings
Figure 9. 87C196CB Buswidth Timings
TOSC
XTAL1
CLKOUT
ALE
TLLGV
BUS WIDTH
TCLGX
Valid
Valid
TAVGV
BUS WRITE
Address Out
Data Out
Address Out
If mode 0 selected, add 2 TOSC to these specifications.
A5875-01
16
Production Datasheet
87C196CB - Automotive
5.2.4
87C196CB - Automotive Timings
Table 8. 8xC196CB HOLD#/HOLDA# Timings (Over Specified Operation Conditions)
Symbol
Parameter
Min
Max
Units
THVCH
HOLD Setup Time
65
TCLHAL
CLKOUT Low to HLDA Low
–15
15
ns (1)
ns
TCLBRL
CLKOUT Low to BREQ Low
–15
15
ns
TAZHAL
HLDA Low to Address Float
20
ns
TBZHAL
HLDA Low to BHE#, INST, RD#, WR# Weakly Driven
25
ns
TCLHAH
CLKOUT Low to HLDA High
–15
15
ns
TCLBRH
CLKOUT Low to BREQ High
–25
25
ns
THAHAX
HLDA High to Address No Longer Float
–15
THAHBV
HLDA High to BHE#, INST, RD#, WR# Valid
–10
ns
15
ns
NOTE:
1. To guarantee recognition at next clock.
Figure 10. 87C196CB HOLD#/HOLDA# Timings
TOSC
CLKOUT
THVCH
THVCH
HOLD#
Hold Latency
TCLHAL
TCLHAH
HOLDA#
TCLBRL
TCLBRH
BREQ#
THALAZ
THAHAX
THALBZ
THAHAX
BUS
BHE#, INST,
RD#, WR#
TCHLH
ALE
A5848-01
Production Datasheet
17
87C196CB - Automotive
5.2.5
87C196CB - Automotive AC Characteristics - Slave Port
Figure 11. Slave Port Waveform - (SLPL = 0)
CS
TSRHAV
ALE / A1
TSRLRH
RD
TSRLDV
TSRHDZ
P3
TSDVWH
TSAVWL
TSWLWH
TSWHQX
WR
A5847-01
Table 9. Slave Port Timing - (SLPL = 0, 1, 2, 3)
Symbol
Parameter
Min
Max
Units
TSAVWL
Address Valid to WR# Low
50
ns
TSRHAV
RD# High to Address Valid
TSRLRH
RD# Low Period
60
ns
TOSC
ns
TSWLWH
WR# Low Period
TOSC
ns
TSRLDV
RD# Low to Output Data Valid
TSDVWH
Input Data Setup to WR# High
20
ns
TSWHQX
WR# High to Data Invalid
30
ns
TSRHDZ
RD# High to Data Float
15
ns
60
ns
NOTE:
1. Test Conditions:
• FOSC = 20 MHz
• TOSC = 60 ns
• Rise/Fall Time = 10 ns
• Capacitive Pin Load = 100 pF
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory
tests.
18
Production Datasheet
87C196CB - Automotive
Figure 12. Slave Port Waveform - (SLPL = 1)
TSELLL
TSRHEH
CS
ALE
TSLLRL
TSRLRH
RD
TSRHDZ
TSRLDV
P3
TSDVWH
TSAVLL
TSLLAX
TSWHQX
TSWLWH
WR
A5846-01
Table 10. Slave Port Timing - (SLPL = 1, 2, 3)
Symbol
Parameter
Min
Max
Units
TSELLL
CS# Low to ALE Low
20
ns
TSRHEH
RD# or WR# High to CS# High
TSLLRL
ALE Low to RD# Low
60
ns
TOSC
ns
TSRLRH
RD# Low Period
TOSC
ns
TSWLWH
WR# Low Period
TOSC
ns
TSAVLL
Address Valid to ALE Low
20
ns
TSLLAX
ALE Low to Address Invalid
20
ns
TSRLDV
RD# Low to Output Data Valid
TSDVWH
Input Data Setup to WR# High
20
ns
TSWHQX
WR# High to Data Invalid
30
ns
TSRHDZ
RD# High to Data Float
15
ns
60
ns
NOTE:
1. Test Conditions:
• FOSC = 20 MHz
• TOSC = 60 ns
• Rise/Fall Time = 10 ns
• Capacitive Pin Load = 100 pF
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory
tests.
Production Datasheet
19
87C196CB - Automotive
Table 11. Normal Master/Slave Operation
Symbol
Parameter
Min (1)
Max
Units
TCHCH
Clock Period
TCLCH
Clock Low Time/Clock High Time
4t
ns
2t–10
ns
TCLDV
Clock Falling to Data Out Valid (Master)
0.5t
1.5t + 20
ns
TCLDV1
Clock Falling to Data Out Valid (Slave)
0.5t
1.5t + 50
ns
TDVCH
Data In Setup to Clock Rising Edge
10
ns
TCHDX
Clock Rising Edge to Data In Invalid
t + 15
ns
NOTE:
1. t = 1 state time (100 ns @ 20 MHz).
2. Timings are guaranteed by design.
Table 12. Handshake Operation
Symbol
Parameter
Min (1)
Max
Units
TCHCH
Clock Period
TCLCH
Clock Low Time/Clock High Time
4t
ns
2t–10
ns (2)
TCLDV
Clock Falling to Data Out Valid (Master)
0.5t
1.5t + 20
ns
TCLDV1
Clock Falling to Data Out Valid (Slave)
0.5t
1.5t + 20
ns
TDVCH
Data In Setup to Clock Rising Edge
10
ns
TCHDX
Clock Rising Edge to Data In Invalid
t + 15
ns
NOTE:
1. t = 1 state time (100 ns @ 20 MHz).
2. This specification refers to input clocks during slave operation. During master operation, the device outputs
a nominal 50% duty cycle clock.
Figure 13. Synchronous Serial Port
1
SCx
(normal
transfers)
2
3
4
5
6
7
8
TCLCH
TCLCL
STE Bit
SDx (out)
MSB
D6
D4
D5
D3
D2
D0
D1
TD1DV
SDx (in)
valid
valid
valid
valid
valid
valid
valid
valid
TDVCX
SCx
(handshaking
transfers)
1
TCXDX
2
3
TCXDV
4
TDXCX
5
6
7
8
Slave Receiver Pulls SCx low
A4512-01
20
Production Datasheet
87C196CB - Automotive
Table 13. External Clock Drive
Symbol
Parameter
Min (1)
Max
Units
1/TXLXL
Oscillator Frequency
4
20
MHz
TXLXL
Oscillator Period (TOSC)
50
250
ns
TXHXX
High TIme
0.35 TOSC
0.65 TOSC
ns
TXLXX
Low Time
0.35 TOSC
0.65 TOSC
ns
TXLXH
Rise TIme
10
ns
TXHXL
Fall Time
10
ns
Figure 14. External Clock Drive Waveforms
TXHXX
0.7 VCC + 0.5 V
0.7 VCC + 0.5 V
TXHXL
TXLXH
TXLXX
0.3 VCC – 0.5 V
0.7 VCC + 0.5 V
0.3 VCC – 0.5 V
TXLXL
A5842-01
Figure 15. Input/Output Test Conditions
OUTPUTS
INPUTS
3.5 V
2.0 V
Test Points
0.45 V
0.8 V
Note:
AC testing inputs are driven at 3.5 V for a logic “ 1” and 0.45 V for a logic
“ 0” . Timing measurements are made at 2.0 V for a logic “ 1” and 0.8 V for
a logic “ 0”.
A5843-01
Production Datasheet
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87C196CB - Automotive
Figure 16. Float Test Conditions
VOH – 0.15 V
VLOAD + 0.15 V
Timing Reference
Points
VLOAD
VLOAD – 0.15 V
VOL + 0.15 V
Note:
For timing purposes, a port pin is no longer floating when a 150 mV change from load
voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL
level occurs with IOL/IOH ≤ 15 mA.
A5844-01
5.2.6
Explanation of AC Symbols
Each symbol is two pairs of letters prefixed by “T” for time. The characters in a pair indicate a
signal and its condition, respectively. Symbols represent the time between the two signal/condition
points.
Table 14. Explanation of AC Symbols
Conditions
Signals
H – High
A – Address
HA – HLDA#
L – Low
B – BHE#
L – ALE/ADV#
V – Valid
BR – BREQ#
Q – Data Out
X – No Longer Valid
C – CLKOUT
R – RD#
Z – Floating
D – DATA
W – WR#/WRH#/WRI#
G – Buswidth
X – XTAL1
H – HOLD#
Y – READY
5.3
EPROM Specifications
5.3.1
AC EPROM Programming Characteristics
Operating Conditions:
• Load Capacitance = 150 pF
• VCC = 5.0 V ± 0.25 V
• VSS = 0 V
• TC = 25°C ± 5°C
• ANGND = 0 V
• EA# = 12.5 V ± 0.25 V
• VREF = 5.0 V ± 0.25 V
• VPP = 12.5 V ± 0.25 V
• FOSC = 5.0 MHz
Table 15. AC EPROM Programming Characteristics (Sheet 1 of 2)
Symbol
22
Parameter
Min
Max
Units
TAVLL
Address Setup Time
0
TOSC
TLLAX
Address Hold Time
100
TOSC
TDVPL
Data Setup Time
0
TOSC
Production Datasheet
87C196CB - Automotive
Table 15. AC EPROM Programming Characteristics (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
TPLDX
Data Hold Time
400
TOSC
TLLLH
PALE# Pulse Width
50
TOSC
TPLPH
PROG# Pulse Width (2)
100
TOSC
TLHPL
PALE# High to PROG# Low
220
TOSC
TPHLL
PROG# High to Next PALE# Low
220
TOSC
TPHDX
Word Dump Hold Time
TPHPL
PROG# High to Next PROG# Low
220
TOSC
TLHPL
PALE# High to PROG# Low
220
TOSC
TPLDV
PROG# Low to Word Dump Valid
TSHLL
RESET# High to First PALE# Low
TPHIL
PROG# High to AINC# Low
TILIH
AINC# Pulse Width
TILVH
PVER Hold after AINC# Low
50
TOSC
TILPL
AINC# Low to PROG# Low
170
TOSC
TPHVL
PROG# High to PVER# Valid
50
TOSC
100
TOSC
1100
TOSC
0
TOSC
240
TOSC
220
TOSC
NOTES:
1.Run time programming is done with FOSC = 6 MHz to 10 MHz, VCC, VPD, VREF = 5 V ±0.25 V,
TC = 25°C ±5°C and VPP = 12.5 V ± 0.25 V. For run-time programming over a full operating range, contact
factory.
2.Programming Specifications are not tested, but guaranteed by design.
3.This specification is for the word dump mode. For programming pulses use 300 TOSC + 100 µs.
Table 16. DC EPROM Programming Characteristics
Symbol
IPP
Parameter
VPP Programming Supply Current
Min
Max
200
Units
mA
NOTE: VPP must be within 1 V of VCC while VCC < 4.5 V. VPP must not have a low impedance path to ground
or VSS while VCC > 4.5 V.
Production Datasheet
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87C196CB - Automotive
5.3.2
EPROM Programming Waveforms
Figure 17. Slave Programming Mode Data Program Mode with Single Program Pulse
RESET#
TAVLL
PORTS 3/4
TDVPL
Address/Command
TSHLL
Data
TLLAX
Address/Command
TPLDX
PALE#
P2.1
TLLLH
TLHPL
TPLPH
TPHLL
PROG#
P2.2
TPHVL
PVER#
P2.0
Valid
TLLVH
A5838-01
Figure 18. Slave Programming Mode in Word Dump or Data Verify Mode with Auto Increment
RESET#
ADDR
PORTS 3/4
Address/Command
TSHLL
TPLDV
ADDR + 2
Ver Bits/WD Dump
Ver Bits/WD Dump
TPHDX
TPLDV
TPHDX
PALE#
P2.1
PROG#
P2.2
TILPL
TPHPL
PVER#
P2.0
A5839-01
24
Production Datasheet
87C196CB - Automotive
Figure 19. Slave Programming Mode Timing in Data Program Mode with Repeated Program
Pulse and Auto Increment
RESET#
PORTS 3/4
Address/Command
Data
PALE#
P2.1
Data
TPHPL
PROG#
P2.2
P1
TILPL
P2
TILVH
PVER#
P2.0
Valid For P1
Valid
For P2
TILIH
AINC#
P2.4
TPHIL
A5840-01
5.4
AC Characteristics - Serial Port - Shift Register Mode
Operating Conditions:
•
•
•
•
TA = –40°C +125°C
VSS = 0.0 V
VCC = 5.0 V ±5%
Load Capacitance = 100 pF
Table 17. Serial Port Timing - Shift Register Mode
Symbol
Parameter
Min
Max
8 TOSC
Units
TXLXL
Serial Port Clock Period
TXLXH
Serial Port Clock Falling Edge to Rising Edge
TQVXH
Output Data Setup to Clock Rising Edge
3 TOSC
ns
TXHQX
Output Data Hold after Clock Rising Edge
2 TOSC – 50
ns
TXHQV
Next Output Data Valid after Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
2 TOSC + 200
TXHDX
Input Data Hold after Clock Rising Edge
0
TXHQZ
Last Clock Rising to Output Float
4 TOSC – 50
ns
4 TOSC + 50
2 TOSC + 50
ns
ns
ns
ns
5TOSC
ns
NOTE:
1.Parameters not tested.
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87C196CB - Automotive
Figure 20. Waveform - Serial Port - Shift Register Mode
TXLXL
TXDx
TQVXH
RXDx
(Out)
TXLXH
0
1
2
Valid
TXHQZ
TXHQX
4
3
TDVXH
RXDx
(In)
TXHQV
7
6
5
TXHDX
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A5841-01
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Production Datasheet
87C196CB - Automotive
5.4.1
A/D Characteristics
The sample and conversion time of the A/D converter in the 8-bit or 10-bit modes is programmed
by loading a byte into the AD_TIME Special Function Register. This allows optimizing the A/D
operation for specific applications. The AD_TIME register is functional for all possible values, but
the accuracy of the A/D converter is only guaranteed for the times specified in the operating
conditions table.
The value loaded into AD_TIME bits 5, 6, 7 determines the sample time, SAMP. The value loaded
into AD_TIME bits 0, 1, 2, 3 and 4 determines the bit conversion time, CONV. These bits, as well
as the equation for calculating the total conversion time, T, are shown in Figure 21.
Figure 21. AD_TIME 1FAFH:Byte
7
6
5
Sample Time
4
(SAMP)
4n + 1 state times
n = 1 to 7
3
2
1
Bit Conversion Time
0
(CONV)
n + 1 state times
n = 2 to 31
Equation: T = (SAMP) + Bx (CONV) + 2.5
T = total conversion time (states)
B = number of bits conversion (8 or 10)
n = programmed register value
The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of
VREF. VREF must be close to VCC since it supplies both the resistor ladder and the analog portion of
the converter and input port pins. There is also an AD_TEST SFR that allows for conversion on
ANGND and VREF as well as adjusting the zero offset. The absolute error listed is without doing
any adjustments.
5.4.1.1
A/D Converter Specification
The specifications given assume adherence to the operating conditions section of this data sheet.
Testing is performed with VREF = 5.12 V and 20 MHz operating frequency. After a conversion is
started, the device is placed in IDLE mode until the conversion is complete.
Table 18. 10-Bit Mode A/D Operating Conditions
Symbol
Parameter
Min
Max
Units
TA
Ambient Temperature
–40
+125
°C
VCC
Digital Supply Voltage
4.75
5.25
V
VREF
Analog Supply Voltage
4.75
5.25
V (1)
TSAM
Sample Time
2
TCONV
Conversion Time
15
18
µs (2)
FOSC
Oscillator Frequency
4
20
MHz
µs (2)
NOTES:
1. VREF must be within+0.5 V of VCC.
2.The value of AD_TIME is selected to meet these specifications.
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87C196CB - Automotive
Table 19. 10-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1)
Parameter
Typical (2,3)
Resolution
Absolute Error
Min
Max
Units (4)
1024
10
1024
10
Levels
Bits
0
±3
LSBs
Full-scale Error
0.25 ± 0.5
LSBs
Zero Offset Error
0.25 ± 0.5
LSBs
1±2
Non-Linearity
Differential Non-Linearity
±3
LSBs
> – 0.75
+ 0.75
LSBs
Channel-to-Channel Matching
± 0.1
0
±1
LSBs
Repeatability
± 0.25
0
Temperature Coefficients:
Offset
Fullscale
Differential Non-Linearity
0.009
Off Isolation
– 60
Notes
LSBs
(2)
LSB/C
(2)
dB
(2,5,6)
Feedthrough
– 60
dB
(2,5)
VCC Power Supply Rejection
– 60
dB
(2,5)
(8)
Input Resistance
±1
DC Input Leakage
Voltage on Analog Input Pin
Sampling Capacitor
750
1.2 K
Ω
–3
3
µA
ANGND –0.5
VREF + 0.25
V
3
(7)
pF
NOTES:
1. All conversions performed with processor in IDLE mode.
2. These values are expected for most parts at 25°C but are not tested or guaranteed.
3. These values are not tested in production and are based on theoretical estimates and/or laboratory test.
4. An “LSB”, as used here, has a value of approximately 5 mV
5.DC to 100 KHz
6.Multiplexer Break-Before-Make Guaranteed.
7.Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
8.Resistance from device pin, through internal MUX, to sample capacitor.
Table 20. 8-Bit Mode A/D Operating Conditions
Symbol
Parameter
Max
Units
TA
Ambient Temperature
–40
+125
°C
VCC
Digital Supply Voltage
4.75
5.25
V
VREF
Analog Supply Voltage
4.75
5.25
V (1)
TSAM
Sample Time
2
TCONV
Conversion Time
12
15
µs (2)
FOSC
Oscillator Frequency
4
20
MHz
NOTES:
1. VREF must be within+0.5 V of VCC.
2.The value of AD_TIME is selected to meet these specifications.
28
Min
Production Datasheet
µs (2)
87C196CB - Automotive
Table 21. 8-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1)
Parameter
Typical (2,3)
Resolution
Absolute Error
Min
Max
Units (4)
256
8
256
8
Levels
Bits
0
±1
LSBs
Full-scale Error
± 0.5
LSBs
Zero Offset Error
± 0.5
LSBs
Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability
± 0.25
Temperature Coefficients:
Offset
Fullscale
Differential Non-Linearity
0.003
Off Isolation
0
±1
LSBs
– 0.5
+ 0.5
LSBs
0
±1
LSBs
0
– 60
Notes
LSBs
(2)
LSB/C
(2)
dB
(2,5,6)
Feedthrough
– 60
dB
(2,5)
VCC Power Supply Rejection
– 60
dB
(2,5)
(8)
Input Resistance
DC Input Leakage
±1
Voltage on Analog Input Pin
Sampling Capacitor
3
750
1.2 K
Ω
– 1.5
1.5
µA
ANGND –0.5
VREF + 0.25
V
(7)
pF
NOTES:
1. All conversions performed with processor in IDLE mode.
2. These values are expected for most parts at 25°C but are not tested or guaranteed.
3. These values are not tested in production and are based on theoretical estimates and/or laboratory test.
4. An “LSB”, as used here, has a value of approximately 5 mV
5.DC to 100 KHz
6.Multiplexer Break-Before-Make Guaranteed.
7.Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
8.Resistance from device pin, through internal MUX, to sample capacitor.
Production Datasheet
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87C196CB - Automotive
6.0
Datasheet Revision History
This is the -007 revision of the 87C196CB - Automotive datasheet. The following differences exist
between the -008 and the -007 revision.
1. To address the fact that many of the package prefix variables have changed, all package prefix
variables in this document are now indicated with an "x".
This is the -006 revision of the 87C196CB - Automotive datasheet. The following differences exist
between the -005 and the -006 revision.
1. Figure 4: Added - “P5.3/” to Pin 77. Removed “P5.3/” from Pin 76.
2. Table 4 - VOH1: Changed - Max value (was 2, now blank) to Min value (was blank, now 2).
This is the -005 revision of the 87C196CB - Automotive datasheet. The following differences exist
between the -004 and the -005 revision.
1. Converted to new template.
2. Corrected grammar.
3. Moved first page talbe and text paragraph to Introduction section.
4. Changed operating supply voltage specifications from 10% to 5%.
5. Removed all references to 87C196CA from data sheet.
6. Changed from “Advance Information” to “Production” data sheet.
This is the -003 revision of the 87C196CB - Automotive data sheet. The following differences exist
between the -002 version and the -003 revision.
1. The data sheet has been revised to ADVANCE from PRELIMINARY, indicating the
specifications have been verified through electrical tests.
2. The 87C196CB 100-ld QFP package and device pinout has been added to the data sheet.
3. The 87C196CB 100-ld QFP device supports up the 16 Mbyte of linear address space.
4. The package thermal characteristics for the PLCC packages was added to the data sheet, for
the CB ΘJA = 35.0°C/W, ΘJC = 11.0°C/W. For the CA, ΘJA = 36.5°C/W and ΘJA = 10.0°C/W.
5. The AN87C196CB pin package diagram was corrected to show EA# as opposed to EA.
6. The REMAP bit function for CCB2 was corrected. Setting this bit to 0 selects
EPROM/CODERAM in segment 0FFH only. Setting this bit to 1 selects both segment 0FFH
and segment 00H.
7. TRLAZ has been changed to 5 ns from 20 ns.
8. TWLWH for the CA has been changed to TOSC –20 from TOSC –30.
9. TCLGX has been changed to 0 ns min, from TOSC –46 max.
10. . Timing specifications for the SSIO are now added. These timings are currently guaranteed by
design.
11. . Added frequency designation to family nomenclature Figure 2.
This is the -002 revision of the 87C196CA data sheet. The following difference exist between the
-001 version and the -002 revision.
1. This data sheet now includes the specifications for the 87C196CB as well as the 87C196CA.
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87C196CB - Automotive
2. ABSOLUTE MAXIMUM RATINGS have been added.
3. Maximum Frequency has been increased to 20 MHz.
4. Maximum ICC has been increased from 75 mA to 100 mA for the CB, 90 mA for the CA.
5. Idle Mode current has been increased to 35 mA from 30 mA for the CB, 40 mA for the CA.
6. Input leakage current for Port 0 (ILI1) was decreased to 1.5 µA from 2.0 µA for the CA.
7. The electrical characteristics for the CAN module were removed. The electrical characteristics
for TXCAN and RXCAN are identical to standard port pins.
8. TOSC (1/freq) was modified to reflect 20 Mhz timings.
9. TOFD (Oscillator Fail Detect Specification) for clock failure to RESET pin pulled low, was
added to the data sheet (4 µs min, 40 µs max)
10. TWHQX has been increased to TOSC –25 ns min from TOSC –30 ns min.
11. TRXDX has been replaced by TRHDX. TRLAZ has been increased to 20 ns max from 5 ns max.
12. I PP programming supply current has been increased to 200 mA from 100 mA.
13. TCONV Conversion time for 10 bit A/D conversions has been decreased to reflect 20 Mhz
operation.
14. RRST was added for the 87C196CA, min = 6 KΩ/max = 65 KΩ.
15. TCLLH–min/max parameters switched to accurately reflect this timing parameter.
16. TRLCL–Separate timings for the 87C196CA vs 87C196CB. TRLCL for the CB is min –8 ns,
max +20 ns. For the CA, TRLCL min +4 ns/max +30 ns.
17. TRLRH changed to TOSC –10 ns from TOSC –5 ns.
18. TAVGV added for the 87C196CB.
19. TLLGV added for the 87C196CB.
20. TCLGX added for the 87C196CB.
21. TRLDV–Separate timings for 87C196CB.TRLDV max = TOSC –30 ns. For the 87C196CA,
TRLDV max = TOSC – 22 ns.
22. HOLD/HOLDA timings added for the 87C196CB.
23. Slave Port Timings added for the 87C196CB.
24. Separate specifications for TPLPH for the 87C196CB, TPLPH, min = 100 TOSC. For the
87C196CA, TPLPH min = 50 TOSC.
25. Separate specifications for TPLDV for the 87C196CB, TPLDV min = 100 TOSC for the
87C196CA, TPLDV min = 50 TOSC.
26. 8-Bit mode A/D characteristics added.
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