LT1786F SMBus Programmable CCFL Switching Regulator FEATURES ■ ■ ■ ■ ■ ■ ■ Wide Battery Input Range: 4.5V to 30V Grounded Lamp or Floating Lamp Configurations Open Lamp Protection Precision 100µA Full-Scale DAC Programming Current 2-Wire SMBus Interface Two Selectable SMBus Addresses DAC Setting Is Retained in Shutdown U APPLICATIONS ■ ■ ■ Notebook and Palmtop Computers Portable Instruments Personal Digital Assistants U DESCRIPTION The LT ®1786F is a fixed frequency, current mode, switching regulator that provides the control function for Cold Cathode Fluorescent Lighting (CCFL). The IC includes an efficient high current switch, an oscillator, output drive logic, control circuitry and a micropower 6-bit 100µA fullscale current output DAC. The DAC provides simple “bits- to-lamp-current control” and communicates using the 2-wire SMBus serial interface. The LT1786F acts as an SMBus slave device using one of two selectable SMBus addresses set by the address pin ADR. On Power-up, the DAC output current assumes midrange or zero scale, depending on the logic state of the ADR pin.The entire IC can be shut down through the SMBSUS pin or by setting the SHDN bit = 1 in the SMBus command byte. Digital data for the DAC output current is retained internally and the supply current drops to 40µA for standby operation. The active low SHDN pin disables the CCFL control circuitry, but keeps the DAC alive. Supply current in this operating mode drops to 150µA. The LT1786F control circuitry operates from a logic supply voltage of 3.3V or 5V. The IC also has a battery supply pin that operates from 4.5V to 30V. The LT1786F draws 6mA typical quiescent current. A 200kHz switching frequency minimizes magnetic component size. Current mode switching techniques with cycle-by-cycle limiting gives high reliability and simple loop frequency compensation. The LT1786F is available in a 16-pin narrow SO package. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATION 90% Efficient Floating CCFL with 2-Wire SMBus Control of Lamp Current CCFL BACKLIGHT APPLICATION CIRCUITS CONTAINED IN THIS DATA SHEET ARE COVERED BY U.S. PATENT NUMBER 5408162 AND OTHER PATENTS PENDING D1 BAT85 1 2 3 C7, 1µF 4 5 SHUTDOWN 6 7 8 CCFL PGND CCFL VSW ICCFL BULB 16 SHDN IOUT 3 SMBSUS SCL ADR SDA R2 220k + C4 2.2µF 3V ≤ VCC ≤ 6.5V 10 9 2 + 12 11 6 L2 = COILTRONICS CTX100-4 *DO NOT SUBSTITUTE COMPONENTS L1 15 14 BAT LT1786F 13 CCFL VC ROYER VCC 10 C2 27pF 3kV C5 1000pF DIO AGND L1 = COILTRONICS CTX210605 LAMP 4 COILTRONICS (561) 241-7876 5 + C3B 2.2µF 35V C3A 2.2µF 35V BAT 8V TO 28V R1 750Ω C1* 0.068µF R3 100k Q2* TO SMBus HOST ALUMINUM ELECTROLYTIC IS RECOMMENDED FOR C3A AND C3B. MAKE 3CB ESR ≥ 0.5Ω TO PREVENT DAMAGE TO THE LT1786F HIGH-SIDE SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON C1 MUST BE A LOW LOSS CAPACITOR, C1 = WIMA MKI OR MKP-20 = PANASONIC ECH-U 1 Q1* L2 100µH D1 1N5818 1786F TA01 0µA TO 50µA ICCFL CURRENT GIVES 0mA TO 6mA LAMP CURRENT FOR A TYPICAL DISPLAY. FOR ADDITIONAL CCFL/LCD CONTRAST APPLICATION CIRCUITS, REFER TO THE LT1182/83/84/84F DATA SHEET Q1, Q2 = ZETEX ZTX849 OR ROHM 2SC5001 1 LT1786F W U U W W W VCC ........................................................................... 7V BAT, Royer, BULB .................................................. 30V CCFL VSW ............................................................... 60V Shutdown ................................................................. 6V ICCFL Input Current .............................................. 10mA DIO Input Current (Peak, < 100ms).................... 100mA Digital Inputs .............................. – 0.3V to (VCC + 0.3V) Digital Outputs ............................ – 0.3V to (VCC + 0.3V) DAC Output Voltage ..................... – 15V to (VCC + 0.3V) Junction Temperature (Note 1) ............................ 100°C Operating Ambient Temperature Range ..... 0°C to 70°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION TOP VIEW CCFL PGND 1 ICCFL 2 DIO 3 CCFL VC 4 15 BULB 14 BAT LT1786FCS 13 ROYER AGND 5 12 VCC SHDN 6 11 IOUT SMBSUS 7 10 SCL ADR 8 ORDER PART NUMBER 16 CCFL VSW 9 SDA S PACKAGE 16-LEAD PLASTIC SO TJMAX = 100°C, θJA = 100°C/W Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = SHUTDOWN = SMBSUS = SCL = SDA = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open, DIO = IOUT = GND, CCFL VC = 0.5V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS IQ Supply Current 3V ≤ VCC ≤ 6.5V, IOUT = 0µA ● 6 9.5 mA ISUS SMBSUS Supply Current SMBSUS = 0V or Command Code Bit 7 = 1, CCFL VC = Open (Note 2) ● 40 100 µA ISHDN SHUTDOWN Supply Current SHUTDOWN = 0V, CCFL VC = Open (Note 2) ● 150 300 µA SHUTDOWN Input Bias Current SHUTDOWN = 0V, CCFL VC = Open 5 10 µA SHUTDOWN Threshold Voltage f DC(MAX) BV Switching Frequency Maximum Switch Duty Cycle Measured at CCFL VSW, ISW = 50mA, ICCFL = 100µA, CCFL VC = Open MIN Measured at CCFL VSW Switch Leakage Current VSW = 12V, Measured at CCFL VSW VSW = 30V, Measured at CCFL VSW ICCFL Summing Voltage 3V ≤ VCC ≤ 6.5V UNITS 0.45 0.85 1.2 V ● 175 160 200 200 225 240 kHz kHz ● 80 75 85 85 % % 60 70 V ● 2 MAX ● Measured at CCFL VSW Switch Breakdown Voltage TYP 20 40 µA µA 0.465 0.465 0.505 0.555 V V 5 15 mV –5 5 15 µA 0.425 0.385 ∆ICCFL Summing Voltage for ∆Input Programming Current ICCFL = 0µA to 100µA CCFL VC Offset Sink Current CCFL VC = 1.5V, Positive Current Measured into Pin ∆CCFL VC Source Current for ∆ICCFL Programming Current ICCFL = 25µA, 50µA, 75µA, 100µA, CCFL VC = 1.5V ● 4.70 4.95 5.20 µA/µA CCFL VC to DIO Current Servo Ratio DIO = 5mA out of Pin, Measure I(VC) at CCFL VC = 1.5V ● 94 99 104 µA/mA CCFL VC Low Clamp Voltage VBAT – VBULB = BULB Protect Servo Voltage ● CCFL VC High Clamp Voltage ICCFL = 100µA ● CCFL VC Switching Threshold CCFL VSW DC = 0% CCFL High-Side Sense Servo Current ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V 0.1 0.3 V 1.7 2.1 2.4 V ● 0.6 0.95 1.3 V ● 0.93 1.00 1.07 A LT1786F ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = SHUTDOWN = SMBSUS = SCL = SDA = 3.3V, BAT = Royer = BULB = 12V, I CCFL = CCFL VSW = Open, DIO = IOUT = GND, CCFL VC = 0.5V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN CCFL High-Side Sense Servo Current Line Regulation BAT = 5V to 30V, ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V TYP MAX UNIT 0.1 0.16 %/V CCFL High-Side Sense Supply Current Current Measured into BAT and Royer Pins ● 50 100 150 µA BULB Protect Servo Voltage ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V, Servo Voltage Measured between BAT and BULB Pins ● 6.5 7.0 7.5 V BULB Input Bias Current ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V 5 9 µA ILIM CCFL Switch Current Limit Duty Cycle = 50% Duty Cycle = 75% (Note 3) ● ● 1.9 1.6 3.0 2.6 A A VSAT CCFL Switch On Resistance CCFL ISW = 1A ● 0.6 1.0 Ω ∆IQ ∆ISW Supply Current Increase During CCFL Switch On Time CCFL ISW = 1A 20 30 mA/A 1.25 0.9 DAC Resolution DAC Full-Scale Current 6 V(IOUT) = 0.465V ● DAC Zero Scale Current V(IOUT) = 0.465V 98 96 100 100 µA µA ±200 nA ● ±0.1 ±1 LSB 0.2 2 LSB ±1 µA ● DAC Differential Nonlinearity Bits 102 104 DAC Supply Voltage Rejection 3V ≤ VCC ≤ 6.5V, IOUT = Full Scale, V(IOUT) = 0.465V ● IIN Logic Input Current 0V ≤ VIN ≤ VCC ● VIH High Level Input Voltage ADR SMBSUS SCL, SDA ● ● ● VIL Low Level Input Voltage SMBSUS, ADR SCL, SDA ● ● 0.8 0.6 V V VOL Low Level Output Voltage IOUT = 3mA, SDA Only IOUT = 1.6mA, SMBSUS = 0V, Measured at SHDN Pin ● ● 0.4 0.4 V V 100 kHz VCC – 0.3 2.4 1.4 V V V SMBus Timing (Notes 4, 5) fSMB SMB Operating Frequency ● 10 tBUF Bus Free Time Between Stop and Start Condition ● 4.7 µs tHD:STA Hold Time After (Repeated) Start Condition ● 4.0 µs tSU:STA Repeated Start Condition Setup Time ● 4.7 µs tSU:STO Stop Condition Setup Time ● 4.0 µs tHD:DAT Data Hold Time ● 300 ns tSU:DAT Data Setup Time ● 250 ns tLOW Clock Low Period ● 4.7 tHIGH Clock High Period ● 4.0 tf Clock/Data Fall Time tr Clock/Data Rise Time The ● denotes specifications which apply over the specified operating temperature range. Note 1: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LT1786FCS: TJ = TA + (PD)(100°C/W) Note 2: Does not include switch leakage. µs 50 µs ● 300 ns ● 1000 ns Note 3: For duty cycles (DC) between 50% and 80%, minimum guaranteed switch current is given by ILIM = 1.4(1.393 – DC) for the LT1786F due to internal slope compensation circuitry. Note 4: Timings for all signals are referenced to VIH and VIL signals. Note 5: These parameters are guaranteed by design and are not tested in production. Refer to the Timing Diagrams for additional information. 3 LT1786F U W TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Temperature 8 8O 7 70 6 60 5 4 300 SMBSUS = 0V VCC = 5V 50 40 3 30 2 20 1 10 VCC = 3V –5 5 1.1 1 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 60 1.0 0.9 0.8 0.7 220 210 200 190 180 170 160 –75 –50 –25 95 93 ICCFL SUMMING VOLTAGE (V) 87 85 83 81 79 77 75 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G07 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G05 1786 G06 ICCFL Summing Voltage vs Temperature 89 25 50 75 100 125 150 TEMPERATURE (°C) Frequency vs Temperature 0.6 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) Maximum Duty Cycle vs Temperature 91 –5 230 1786 G04 CCFL MAXIMUM DUTY CYCLE (%) 90 240 ICCFL Summing Voltage Load Regulation 0.53 0.52 0.51 0.50 0.49 0.48 0.47 0.46 0.45 0.44 0.43 0.42 0.41 0.40 0.39 0.38 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G08 ∆ICCFL SUMMING VOLTAGE (mV) VCC = 3V VCC = 3V 120 1786 G03 CCFL FREQUENCY (kHz) 1.2 SHDN THRESHOLD VOLTAGE (V) SHDN INPUT BIAS CURRENT (µA) 6 2 150 SHDN Threshold Voltage vs Temperature 4 VCC = 5V 180 1786 G02 SHDN Input Bias Current vs Temperature VCC = 5V 210 0 –55 –25 25 50 75 100 125 150 TEMPERATURE (°C) 1786 G01 3 240 30 0 –55 –25 0 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) SHDN = 0V 270 SHDN SUPPLY CURRENT (µA) 90 ISUS (µA) 100 9 SUPPLY CURRENT (mA) 10 4 SHDN Supply Current vs Temperature ISUS Current vs Temperature 5 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 T = –55°C T = 25°C T = 125°C 0 20 40 60 80 100 120 140 160 180 200 ICCFL PROGRAMMING CURRENT (µA) 1786 G09 LT1786F U W TYPICAL PERFORMANCE CHARACTERISTICS ∆CCFL VC Source Current for ∆ICCFL Programming Current vs Temperature VC Sink Offset Current vs Temperature CCFL VC = 1.0V 4 3 2 1 CCFL VC = 0.5V 0 –1 –2 –3 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 5.05 1.0 ICCFL = 100µA 5.00 4.95 ICCFL = 50µA ICCFL = 10µA 4.90 4.85 4.80 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G10 CCFL VC DIO CURRENT SERVO RATIO (µA/mA) NEGATIVE DIO VOLTAGE (V) 1.4 I(DIO) = 10mA 1.2 I(DIO) = 5mA 0.8 I(DIO) = 1mA 0.6 0.4 0.2 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 0.4 1786 G12 VC Low Clamp Voltage vs Temperature 0.30 102 101 100 I(DIO) = 10mA I(DIO) = 1mA 99 I(DIO) = 5mA 98 97 96 95 –75 – 50 –25 0.25 0.20 0.15 0.10 0.05 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G14 1786 G15 VC Switching Threshold vs Temperature 2.3 2.2 2.1 2.0 1.9 1.8 1.7 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G16 CCFL VC SWITCHING THRESHOLD VOLTAGE (V) VC High Clamp Voltage vs Temperature 2.4 I(DIO) = 1mA 0 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 103 1786 G13 CCFL VC HIGH CLAMP VOLTAGE (V) 0.6 VC to DIO Current Servo Ratio vs Temperature 1.6 I(DIO) = 5mA 1786 G11 Negative DIO Voltage vs Temperature 1.0 I(DIO) = 10mA 0.8 0.2 CCFL VC LOW CLAMP VOLTAGE (V) 6 5 1.2 POSITIVE DIO VOLTAGE (V) CCFL VC = 1.5V 5.10 BULB Protect Servo Voltage vs Temperature 7.5 1.3 BULB PROTECT SERVO VOLTAGE (V) 9 8 7 ∆CCFL VC SOURCE CURRENT FOR ∆ICCFL PROGRAMMING CURRENT (µA/µA) CCFL VC SINK OFFSET CURRENT (µA) 10 Positive DIO Voltage vs Temperature 1.2 1.1 1.0 0.9 0.8 0.7 0.6 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G17 7.4 7.3 7.2 7.1 ICCFL = 100µA 7.0 6.9 6.8 ICCFL = 50µA 6.7 6.6 ICCFL = 10µA 6.5 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G18 5 LT1786F U W TYPICAL PERFORMANCE CHARACTERISTICS High-Side Sense Supply Current vs Temperature 6 4 2 0 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 150 140 130 120 110 100 90 80 70 60 50 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 0.160 1.0 0.140 0.9 0.080 0.060 0.040 0.020 1.020 1.000 0.980 0.960 0.940 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G21 VSW Current Limit vs Duty Cycle 2.5 0.8 T = 25°C 0.7 T = 125°C 0.6 T = –5°C 0.5 0.4 0.3 0.2 2.0 T = 0°C T = 25°C 1.5 T = 125°C MINIMUM 1.0 0.5 0.1 0.000 –75 – 50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 0 0 0.3 0.9 1.2 0.6 SWITCH CURRENT (A) 1786 G22 0 10 20 30 40 50 60 DUTY CYCLE (%) 104 FULL-SCALE OUTPUT CURRENT (µA) 100 90 80 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 CCFL ISW (A) 1786 G25 V(IOUT) = 0.465V 103 102 101 100 99 98 97 96 –75 –50 –25 70 80 90 1786 G24 Full-Scale Output Current vs Temperature 110 FORCED BETA 0 1.5 1787 G23 Forced Beta vs ISW on VSW 6 1.040 VSW Sat Voltage vs Switch Current CCFL VSW SAT VOLTAGE (V) CCFL HIGH-SIDE SENSE LINE REGULATI0N (%V) High-Side Sense Null Current Line Regulation vs Temperature 0.100 1.060 1786 G20 1787 G19 0.120 CCFL HIGH-SIDE SENSE NULL CURRENT (A) 8 High-Side Sense Null Current vs Temperature CCFL VSW CURRENT LIMIT (A) BULB INPUT BIAS CURRENT (µA) 10 CCFL HIGH-SIDE SENSE SUPPLY CURRENT (µA) BULB Input Bias Current vs Temperature 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1786 G26 LT1786F U W TYPICAL PERFORMANCE CHARACTERISTICS INL vs Code 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) DNL vs Code 1.0 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 16 0 32 CODE 48 64 1786 G27 0 16 32 CODE 48 64 1786 G28 U U U PIN FUNCTIONS CCFL PGND (Pin 1): This pin is the emitter of an internal NPN power switch. CCFL switch current flows through this pin and permits internal, switch-current sensing. The regulator provides a separate analog ground and power ground to isolate high current ground paths from low current signal paths. Linear Technology recommends the use of star-ground layout techniques. ICCFL (Pin 2): This pin is the input to the CCFL lamp current programming circuit. This pin internally regulates to 465mV. The pin accepts a DC input current signal of 0µA to 100µA full scale from the DAC. This input signal is converted to a 0µA to 500µA source current at the CCFL VC pin. As input programming current increases, the regulated lamp current increases. DIO (Pin 3): This pin is the common connection between the cathode and anode of two internal diodes. The remaining terminals of the two diodes connect to ground. In a grounded-lamp configuration, DIO connects to the low voltage side of the lamp. Bidirectional lamp current flows in the DIO pin and thus the diodes conduct alternately on half cycles. Lamp current is controlled by monitoring onehalf of the average lamp current. The diode conducting on negative half cycles has one-tenth of its current diverted to the CCFL VC pin. This current nulls against the source current provided by the lamp-current programmer circuit. A single capacitor on the CCFL VC pin provides both stable loop compensation and an averaging function to the halfwave-rectified sinusoidal lamp current. Therefore, input programming current relates to one-half of average lamp current. This scheme reduces the number of loop compensation components and permits faster loop transient response in comparison to previously published circuits. If a floating lamp configuration is used, ground the DIO pin. CCFL VC (Pin 4): This pin is the output of the lamp current programmer circuit and the input of the current comparator for the CCFL regulator. Its uses include frequency compensation, lamp-current averaging for grounded-lamp circuits and current limiting. The voltage on the CCFL VC pin determines the current trip level for switch turn-off. During normal operation this pin sits at a voltage between 0.95V (zero switch current) and 2.1V (maximum switch current) with respect to analog ground (AGND). This pin has a high impedance output and permits external voltage clamping to adjust current limit. A single capacitor to ground provides stable loop compensation. This simplified loop compensation method permits the CCFL regulator to exhibit single-pole transient response behavior and virtually eliminates transformer output overshoot. 7 LT1786F U U U PIN FUNCTIONS AGND (Pin 5): This is the low current analog ground. It is the negative sense terminal for the internal 1.24V reference and the ICCFL summing voltage in the LT1786F. Connect low current signal paths that terminate to ground and frequency compensation components that terminate to ground directly to this pin for best regulation and performance. pin is tied to GND, the SMBus address is set to 58 (HEX) and the DAC IOUT powers up to zero scale. If the ADR pin is tied to VCC, the SMBus address is set to 5A (HEX) and the DAC IOUT powers up to half scale. If a different value is required for the DAC IOUT on power-up, use the SHDN pin to keep the CCFL regulator off until the required value has been programmed for the DAC via the SMBus. SHDN (Pin 6): Pulling this pin low causes regulator shutdown with quiescent current typically reduced to 150µA. In this condition, the DAC circuitry remains alive and the DAC IOUT level is maintained. If this pin is not used, use a pull-up resistor to force a logic high level (maximum of 6V). The pin can be floated and an internal current source will pull the pin to a logic high level. However, poor PCB layout techniques can permit switching noise to inject into this pin and cause erratic operation. LTC recommends the use of a pull-up resistor. If the SMBSUS pin is pulled low or Bit 7 = 1 in the Command Byte, complete IC shutdown is enabled. An internal open drain N-channel device turns on and pulls the SHDN pin low. The N-channel can sink up to 1.6mA. SDA (Pin 9): This is the SMBus bidirectional data input and digital output pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. SDA is a high impedance pin while data is shifted into the pin and an open-drain N-channel output during acknowledges. SDA requires a pull-up resistor or current source to VCC. SMBSUS (Pin 7): Pulling this pin low causes complete shutdown for the IC with quiescent current typically reduced to 40µA. In this SMBus suspend condition, the DAC retains its last output current setting and returns to this level when the logic low signal at this pin is removed. If this pin is not used, use a pull-up resistor to force a logic high level or tie it directly to VCC. Poor PCB layout techniques can permit switching noise to inject into this pin and cause erratic operation. A small value capacitor may be required to filter out this noise. Setting Bit 7 = 1 in the Command Byte also enables an SMBus suspend condition. Enabling an SMBus suspend condition turns on an internal open drain N-channel device which pulls the SHDN pin low. The N-channel device sinks up to 1.6mA at the SHDN pin. ADR (Pin 8): This is the SMBus address select pin. Tie this pin to either VCC or GND to select one of two SMBus addresses to which the LT1786F will respond. If the ADR 8 SCL (Pin 10): This is the SMBus clock input pin. Data is shifted into the SDA pin at the rising edges of the SCL clock during data transfer. SCL is a high impedance pin. SCL requires a pull-up resistor or current source to VCC. IOUT (Pin 11): This pin is the current output for the DAC and provides a full-scale output current of 100µA ±4µA over temperature. Initial accuracy is 100µA ±2µA.The pin can be biased from – 10V to (VCC – 1.3V). This pin is typically tied directly to the ICCFL pin and provides the programming current which sets the operating lamp current. The IOUT pin has very little bias voltage change when tied to the ICCFL pin as ICCFL is regulated. The programming current is sourced from the IOUT pin and sunk by the ICCFL pin. VCC (Pin 12): This is the supply pin for the LT1786F. The IC accepts an input voltage range of 3V minimum to 6.5V maximum with little change in quiescent current (zero switch current). An internal, low-dropout regulator provides a 2.4V supply for most of the internal circuitry. Supply current increases as switch current increases at a rate approximately 1/50 of switch current. This corresponds to a forced Beta of 50 for the power switch. The IC incorporates undervoltage lockout by sensing regulator dropout and locking out switching for input voltages below 2.5V. Hysteresis is not used to maximize the range of input voltage. The typical input voltage is a 3.3V or 5V logic supply. LT1786F U U U PIN FUNCTIONS ROYER (Pin 13): This pin connects to the center-tapped primary of the Royer converter and is used with the BAT pin in a floating-lamp configuration where lamp current is controlled by sensing Royer primary-side converter current. This pin is the inverting terminal of a high-side current sense amplifier. The typical quiescent current is 50µA into the pin. If the CCFL regulator is not used in a floating-lamp configuration, tie the Royer and BAT pins together. BAT (Pin 14): This pin connects to the battery or AC wall adapter voltage from which the CCFL Royer converter operates. This voltage is typically higher than the VCC supply voltage but can equal VCC if VCC is a 5V logic supply. The BAT voltage must be at least 2.1V greater than the internal 2.4V regulator or 4.5V. This pin provides biasing for the lamp-current programming block, is used with the Royer pin for floating-lamp configurations and connects to one input for the open-lamp protection circuitry. For floating-lamp configurations, this pin is the noninverting terminal of a high-side current sense amplifier. The typical quiescent current is 50µA into the pin. The BAT and Royer pins monitor the primary-side Royer converter current through an internal 0.1Ω topside current sense resistor. A 0A to 1A primary-side, center tap converter current is translated to an input signal range of 0mV to 100mV for the current sense amplifier. This input range translates to a 0µA to 500µA sink current at the CCFL VC pin that nulls against the source current provided by the programmer circuit. The BAT pin also connects to the topside of the internal clamp between the BAT and BULB pins that is used for open-lamp protection. BULB (Pin 15): This pin connects to the low side of a 7V threshold comparator between the BAT and BULB pins. This circuit sets the maximum voltage level across the primary side of the Royer converter under all operating conditions and limits the maximum secondary output under start-up conditions or open-lamp conditions. This eases transformer voltage rating requirements. Set the voltage limit to ensure lamp start-up with worst-case, lamp start voltages and cold temperature, system operating conditions. The BULB pin connects to the junction of an external divider network. The divider network connects from the center tap of the Royer transformer or the actual battery supply voltage to the topside of the current source “tail inductor.” A capacitor across the top of the divider network filters switching ripple and sets a time constant that determines how quickly the clamp activates. When the comparator activates, sink current is generated to pull the CCFL VC pin down. This action transfers the entire regulator loop from current mode operation into voltage mode operation. CCFL VSW (Pin 16): This pin is the collector of the internal NPN power switch for the CCFL regulator. The power switch provides a minimum of 1.25A. Maximum switch current is a function of duty cycle as internal slope compensation ensures stability with duty cycles greater than 50%. Using a driver loop to automatically adapt base drive current to the minimum required to keep the switch in a quasi-saturation state yields fast switching times and high efficiency operation. The ratio of switch current to driver current is about 50:1. 9 LT1786F W BLOCK DIAGRAM LT1786F SMBus Programmable CCFL Switching Regulator VCC BAT 14 12 SHDN 6 SHUTDOWN UNDERVOLTAGE LOCKOUT 2.4V REGULATOR ROYER 13 THERMAL SHUTDOWN CCFL VSW 16 200kHz OSC LOGIC R4 0.1Ω D2 6V ANTISAT + – gm COMP R3 1k 0µA TO 100µA FROM IOUT Q5 1× Q6 2× + Q4 5× CCFL Q11 – – GAIN = 4.4 Q8 1× Q7 9× Q10 2× Q9 3× V1 0.465V R1 0.125Ω CURRENT AMP Q3 2× + Q1 DRIVE D1 2 5 3 15 4 1 ICCFL AGND DIO BULB CCFL VC CCFL PGND SMBSUS 7 SD POWER-ON RESET SHUTDOWN SCL 10 SDA 9 SMBus INTERFACE 1 1 REGISTER A 3-BIT LATCH EN1 SD VOLTAGE REFERENCE REGISTER B 1-BIT LATCH EN2 RADJ SD SD 6 8 ADR 10 REGISTER C 6-BIT LATCH EN2 6 6-BIT CURRENT DAC 11 IOUT 1786 BD LT1786F WU W TI I G DIAGRA S Timing for SMBus Interface t BUF SDA t HD:STA t HD:STA tf tr SCL t LOW STOP t HIGH START t SU:STO t SU:STA t HD:DAT t SU:DAT 1786 TD01 START STOP Operating Sequence SMBus Write Byte Protocol, with SMBus Address = 0101101B, Command Byte = 0XXXXXXXB and Data Byte = 111111XXB VCC ADR GND SCL S 1 2 3 1 4 1 5 0 6 1 7 8 9 X X X X X X X 1 1 1 1 1 1 X X ACK 0 DATA BYTE ACK 1 SHDN 0 ACK SDA COMMAND BYTE WR SMBUS ADDRESS * P 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 IOUT 1786 S = START P = STOP * = OPTIONAL TD02 FULL-SCALE CURRENT ZERO-SCALE CURRENT U W U U APPLICATIONS INFORMATION Introduction Current generation portable computers and instruments use backlit Liquid Crystal Displays (LCDs). Cold Cathode Fluorescent Lamps (CCFLs) provide the highest available efficiency in back lighting the display. Providing the most light out for the least amount of input power is the most important goal. These lamps require high voltage AC to operate, mandating an efficient high voltage DC/AC converter. The lamps operate from DC, but migration effects damage the lamp and shorten its lifetime. Lamp drive should contain zero DC component. In addition to good efficiency, the converter should deliver the lamp drive in the form of a sine wave. This minimizes EMI and RF emissions. Such emissions can interfere with other devices and can also degrade overall operating efficiency. Sinusoidal CCFL drive maximizes current-to-light conversion in the lamp. The circuit should also permit lamp intensity control from zero to full brightness with no hysteresis or “pop-on.” The small size and battery-powered operation associated with LCD equipped apparatus dictate low component count and high efficiency for these circuits. Size constraints place severe limitations on circuit architecture and long battery life is a priority. Laptop and handheld portable computers offer an excellent example. The CCFL and its power supply can be responsible for almost 50% of the 11 LT1786F U W U U APPLICATIONS INFORMATION battery drain. Additionally, all components, including PC board and hardware, usually must fit within the LCD enclosure with a height restriction of 5mm to 10mm. The CCFL regulator drives an inductor that acts as a switched-mode current source for a current-driven Royerclass converter with efficiencies as high as 90%. The control loop forces the CCFL PWM to modulate the average inductor current to maintain constant current in the lamp. The constant current value, and thus lamp intensity, is programmable. This drive technique provides a wide range of intensity control. A unique lamp-current programming block permits either grounded lamp or floating lamp configurations. Grounded lamp circuits directly sense one-half of average lamp current. Floating lamp circuits directly sense the Royer’s primary-side converter current. Floating-lamp circuits provide symmetric differential drive to the lamp and reduce the parasitic loss from stray lampto-frame capacitance, extending illumination range. supply current to 150µA by shutting off the 2.4V regulator and locks out switching action for standby operation. The IC incorporates undervoltage lockout by sensing regulator dropout and locking out switching below about 2.5V. The regulator also provides thermal shutdown protection that locks out switching in the presence of excessive junction temperatures. A 200kHz oscillator is the basic clock for all internal timing. The oscillator turns on the output switch via its own logic and driver circuitry. Adaptive anti-sat circuitry detects the onset of saturation in the power switch and adjusts base drive current instantaneously to limit switch saturation. This minimizes driver dissipation and provides rapid turnoff of the switch. The CCFL power switch is guaranteed to provide a minimum of 1.25A in the LT1786F. The antisat circuitry provides a ratio of switch current to driver current of about 50:1. Digital Interface Block Diagram Operation The LT1786F is a fixed frequency, current mode switching regulator. A fixed frequency, current mode switcher controls switch duty cycle directly by switch current rather than by output voltage. Referring to the block diagram for the LT1786F, the switch turns ON at the start of each oscillator cycle. The switch turns OFF when switch current reaches a predetermined level. The control of output lamp current is obtained by using the output of a unique programming block to set current trip level. The current mode switching technique has several advantages. First, it provides excellent rejection of input voltage variations. Second, it reduces the 90° phase shift at mid-frequencies in the energy storage inductor. This simplifies closed-loop frequency compensation under widely varying input voltage or output load conditions. Finally, it allows simple pulse-by-pulse current limiting to provide maximum switch protection under output overload or short-circuit conditions. The LT1786F incorporates a low dropout internal regulator that provides a 2.4V supply for most of the internal circuitry. This low dropout design allows input voltage to vary from 3V to 6.5V with little change in quiescent current. An active low shutdown pin typically reduces total 12 The LT1786F communicates with an SMBus host using the standard 2-wire SMBus interface. The Timing Diagram shows the signals on the SMBus. The two bus lines SDA and SCL must be high when the bus is not in use. External pull-up resistors or current sources are required at these lines. The LT1786F is a receive-only (slave) device. The master must apply the following Write Byte protocol to communicate with the LT1786F: 1 7 1 S Slave Address WR 1 8 1 A Command Byte A 8 1 1 Data Byte A P S = Start Conditon, WR = Write Bit, A = Acknowledge Bit, P = Stop Condition The master initiates communication with the LT1786F with a START condition (see SMBus Operating Sequence) and a 7-bit address followed by the write bit = 0. The LT1786F acknowledges and the master delivers the command byte. The LT1786F acknowledges and latches the active bits of the command byte into register A (see Block Diagram) at the falling edge of the acknowledge pulse. The master sends the data byte and the LT1786F acknowledges the data byte. The data byte is latched into register C at the falling edge of the final acknowledge pulse and the DAC current output assumes the new 6-bit data LT1786F U U W U APPLICATIONS INFORMATION value (see Block Diagram). A STOP condition is optional. The command code and data byte are defined with the following format: Command Code 7 Data Byte 6 5 4 3 2 1 0 SHDN X X X X X X X 7 6 5 4 3 2 1 0 D5 D4 D3 D2 D1 D0 X X SHDN: 0 for normal operation, 1 for shutdown D5 to D0: DAC Data Byte Bits, D5 is the Most Significant Bit START and STOP Conditions At the beginning of any SMBus communication, the master must transmit a START condition by switching SDA from high to low while SCL is high. When a master has finished communicating with a slave device, a STOP condition is issued by switching SDA from low to high while SCL is high. The SMBus is then free for communication with another SMBus device. Early STOP Conditions The LT1786F recongnizes a STOP condition at any point in the SMBus communication sequence. If the STOP occurs prematurely before the data byte is acknowledged in the Write Byte protocol, the DAC output current value is not updated; otherwise internal register C is updated with the new data and the DAC output current changes correspondingly. The Slave Address The LT1786F responds to one of two 7-bit addresses. The first five bits have been factory programmed to 01011. The last two address bits are programmed by the user by tying the ADR pin to VCC or GND (see functional table) ADR SMBus ADDRESS DAC POWER-UP VALUE GND 0101101 Zero Scale VCC 0101100 Midscale 6-Bit Current Output DAC The 6-bit current output DAC is guaranteed monotonic and is digitally adjustable in 63 equal steps. On power-up, if ADR connects to VCC, the 6-bit internal register C (see Block Diagram) resets to 100000B and the DAC output is set to midrange. On power-up, if ADR connects to ground, register C resets to 000000B and the DAC output is set to zero. For the LT1786F, the current source output (IOUT) can be biased from – 10V to (VCC – 1.3V). Full-scale current is trimmed to ±2% at room temperature and ±4% over the commercial temperature range. Shutdown Three methods may be employed to shut down the LT1786F (see Block Diagram). The LT1786F enters SMBus suspend mode if a logic low level is applied to the SMBSUS pin or a logic high level is applied to Bit 7 in the Command Byte of the SMBus communication sequence. In SMBus suspend mode, supply current typically drops to 40µA and the last output current setting is internally retained. The DAC resumes this level upon its return to normal operation. Enabling an SMBus suspend condition also turns on an open-drain N-channel MOSFET which pulls the SHDN pin low. The N-channel device sinks up to 1.6mA at the SHDN pin and its logic low level is guaranteed to less than 0.4V. The LT1786F enters regulator shutdown mode if a logic low level is applied to the SHDN pin. In this mode, supply current typically drops to 150µA, the switching regulator circuitry is shut down and the DAC is kept alive. The DAC output current setting is maintained. This feature can be used to program the DAC to a desired output current level (other than the preset zero-scale or midscale level defined by the selected SMBus address) before allowing the CCFL regulator to turn on. 13 LT1786F U U W U APPLICATIONS INFORMATION LT1786F SMBus Lookup Tables SMBus Address Byte Table SMBus Command Byte Table ADR DECIMAL BINARY HEX IOUT POWER-UP VALUE DECIMAL BINARY HEX MODE GND 91 0101101 5A Zero Scale 0-127 0XXXXXXX 00-7F Normal VCC 88 0101100 58 Midscale 128-255 1XXXXXXX 80-FF Shutdown Bit 0 (LSB) in the SMBus Address is the Write Bit = 0 X = Don’t Care SMBus Data Byte Table DECIMAL BINARY HEX IOUT (µA) 0 000000XX 00-03 0.000 1 000001XX 04-07 2 000010XX 08-0B 3 000011XX 4 5 BINARY HEX IOUT (µA) 32 100000XX 80-83 50.794 1.587 33 100001XX 84-87 52.381 3.175 34 100010XX 88-8B 53.968 0C-0F 4.762 35 100011XX 8C-8F 55.556 000100XX 10-13 6.349 36 100100XX 90-93 57.143 000101XX 14-17 7.937 37 100101XX 94-97 58.730 6 000110XX 18-1B 9.524 38 100110XX 98-9B 60.317 7 000111XX 1C-1F 11.111 39 100111XX 9C-9F 61.905 8 001000XX 20-23 12.698 40 101000XX A0-A3 63.492 9 001001XX 24-27 14.286 41 101001XX A4-A7 65.079 10 001010XX 28-2B 15.873 42 101010XX A8-AB 66.667 11 001011XX 2C-2F 17.460 43 101011XX AC-AF 68.254 12 001100XX 30-33 19.048 44 101100XX B0-B3 69.841 13 001101XX 34-37 20.635 45 101101XX B4-B7 71.429 14 001110XX 38-3B 22.222 46 101110XX B8-BB 73.016 15 001111XX 3C-3F 23.810 47 101111XX BC-BF 74.603 16 010000XX 40-43 25.397 48 110000XX C0-C3 76.190 17 010001XX 44-47 26.984 49 110001XX C4-C7 77.778 18 010010XX 48-4B 28.571 50 110010XX C8-CB 79.365 19 010011XX 4C-4F 30.159 51 110011XX CC-CF 80.952 20 010100XX 50-53 31.746 52 110100XX D0-D3 82.540 21 010101XX 54-57 33.333 53 110101XX D4-D7 84.127 22 010110XX 58-5B 34.921 54 110110XX D8-DB 85.714 23 010111XX 5C-5F 36.508 55 110111XX DC-DF 87.302 24 011000XX 60-63 38.095 56 111000XX E0-E3 88.889 25 011001XX 64-67 39.683 57 111001XX E4-E7 90.476 26 011010XX 68-6B 41.270 58 111010XX E8-EB 92.063 27 011011XX 6C-6F 42.857 59 111011XX EC-EF 93.651 28 011100XX 70-73 44.444 60 111100XX F0-F3 95.238 29 011101XX 74-77 46.032 61 111101XX F4-F7 96.825 30 011110XX 78-7B 47.619 62 111110XX F8-FB 98.413 31 011111XX 7C-7F 49.206 63 111111XX FC-FF 100.000 X = Don’t Care, IOUT = Ideal Value 14 DECIMAL LT1786F U W U U APPLICATIONS INFORMATION Simplified Lamp Current Programming A programming block in the LT1786F controls lamp current, permitting either grounded lamp or floating lamp configurations. Grounded configurations control lamp current by directly controlling one-half of actual lamp current and converting it to a feedback signal to close a control loop. Floating configurations control lamp current by directly controlling the Royer’s primary-side converter current and generating a feedback signal to close a control loop. Previous backlighting solutions have used a traditional error amplifier in the control loop to regulate lamp current. This approach converted an RMS current into a DC voltage for the input of the error amplifier. This approach used several time constants in order to provide stable loop frequency compensation. This compensation scheme meant that the loop had to be fairly slow and that output overshoot with start-up or overload conditions had to be carefully evaluated in terms of transformer stress and breakdown voltage requirements. The LT1786F eliminates the error amplifier concept entirely and replaces it with a lamp current programming block. This block provides an easy-to-use interface to program lamp current. The programmer circuit also reduces the number of time constants in the control loop by combining the error signal conversion scheme and frequency compensation into a single capacitor. The control loop thus exhibits the response of a single pole system, allows for faster loop transient response and virtually eliminates overshoot under start-up or overload conditions. Lamp current is programmed at the input of the programmer block, the ICCFL pin. This pin is the input of a shunt regulator and accepts a DC input current signal of 0µA to 100µA from the DAC. This input signal is converted to a 0µA to 500µA source current at the CCFL VC pin. The programmer circuit is simply a current-to-current converter with a gain of five. The ICCFL pin is sensitive to capacitive loading and will oscillate with capacitance greater than 10pF. For example, loading the ICCFL pin with a 1× or 10× scope probe causes oscillation and erratic CCFL regulator operation because of the probe’s respective input capacitance. A current meter in series with the ICCFL pin will also produce oscillation due to its shunt capacitance. Use a decoupling resistor of several kilohms between the ICCFL pin and the IOUT pin if excessive trace stray capacitance exists. Normally, this resistor is not required. In some applications, the maximum programming current required at the ICCFL pin for a maximum lamp current will be less than the full-scale output current of the DAC, which is 100µA. The system designer can either limit the maximum programming current through software built into the system, or use a current splitter which shunts a percentage of the fullscale current from the ICCFL pin. A splitter circuit is illustrated in Figure 1. A divider string is used from a reference voltage to set up a voltage level equal to the ICCFL summing voltage, or 465mV. The main current flowing in the divider string should be chosen to swamp out the effects of the shunted current into the divider string. IOUT FULL-SCALE 100µA R1 V(ICCFL) 465mV V1 XI VREF I R2 I1 R3 V(ICCFL) (1 – X)I R4 I = 100µA 0<X<1 SELECT V1 WITHIN THE DAC IOUT COMPLIANCE RANGE (EX. V1 = 2V FOR VCC = 3.3V OR 5V) CHOOSE I1 >> (1 – X)I R1 = (V1 – 0.465)/[(X)(100µA)] R2 = (V1 – 0.465)/[(1 – X)(100µA)] R3 = (VREF – 0.465)/I1 R4 = 0.465R3/[(1 – X)(100µA)(R3) + (VREF – 0.465)] 1786 F01 Figure 1 Grounded Lamp Configuration In a grounded lamp configuration, the low voltage side of the lamp connects directly to the LT1786F DIO pin. This pin is the common connection between the cathode and anode of two internal diodes. In previous grounded lamp solutions, these diodes were discrete units and are now integrated onto the IC, saving cost and board space. Bidirectional lamp current flows in the DIO pin and thus, the diodes conduct alternately on half cycles. Lamp current is controlled by monitoring one-half of the average lamp current. The diode conducting on negative half cycles has one-tenth of its current diverted to the CCFL VC pin and nulls against the source current provided by the 15 LT1786F U W U U APPLICATIONS INFORMATION lamp current programmer circuit. The compensation capacitor on the CCFL VC pin provides stable loop compensation and an averaging function to the rectified sinusoidal lamp current. Therefore, input programming current relates to one-half of average lamp current. The transfer function between lamp current and input programming current must be empirically determined and is dependent on the particular lamp/display housing combination used. The lamp and display housing are a distributed loss structure due to parasitic lamp-to-frame capacitance. This means that the current flowing at the highvoltage side of the lamp is higher than what is flowing at the DIO pin side of the lamp. The input programming current is set to control lamp current at the high-voltage side of the lamp, even though the feedback signal is the lamp current at the bottom of the lamp. This ensures that the lamp is not overdriven which can degrade the lamp’s operating lifetime. Therefore, the full scale current of the DAC does not necessarily correspond to the current required to set maximum lamp current. Floating Lamp Configuration In a floating lamp configuration, the lamp is fully floating with no galvanic connection to ground. This allows the transformer to provide symmetric differential drive to the lamp. Balanced drive eliminates the field imbalance associated with parasitic lamp-to-frame capacitance and reduces “thermometering” (uneven lamp intensity along the lamp length) at low lamp currents. Carefully evaluate display designs in relation to the physical layout of the lamp, its leads and the construction of the display housing. Parasitic capacitance from any high voltage point to DC or AC ground creates paths for unwanted current flow. This parasitic current flow degrades electrical efficiency and losses up to 25% have been observed in practice. As an example, at a Royer operating frequency of 60kHz, 1pF of stray capacitance represents an impedance of 2.65MΩ. With an operating lamp voltage of 400V and an operating lamp current of 6mA, the parasitic current is 150µA. This additional current must be supplied by the transformer secondary. Layout techniques that increase parasitic capacitance include long high voltage lamp leads, reflective metal foil 16 around the lamp and displays supplied in metal enclosures. Losses for a good display are under 5%, whereas, losses for a bad display range from 5% to 25%. Lossy displays are the primary reason to use a floating lamp configuration. Providing symmetric, differential drive to the lamp reduces the total parasitic loss by one-half. Maintaining closed-loop control of lamp current in a floating lamp configuration necessitates deriving a feedback signal from the primary side of the Royer transformer. Previous solutions have used an external precision shunt and high-side sense amplifier configuration. This approach has been integrated onto the LT1786F for simplicity of design and ease of use. An internal 0.1Ω resistor monitors the Royer converter current and connects between the input terminals of a high-side sense amplifier. A 0 – 1 Amp Royer primary-side, center-tap current is translated to a 0µA to 500µA sink current at the CCFL VC pin to null against the source current provided by the lamp current programmer circuit. The compensation capacitor on the CCFL VC pin provides stable loop compensation and an averaging function to the error sink current. Therefore, input programming current is related to average Royer converter current. Floating lamp circuits operate similarly to grounded lamp circuits except for the derivation of the feedback signal. The transfer function between lamp current and input programming current must be empirically determined and is dependent upon a myriad of factors including lamp characteristics, display construction, transformer turns ratio and the tuning of the Royer oscillator. Once again, lamp current will be slightly higher at one end of the lamp and input programming current should be set for this higher level to ensure that the lamp is not overdriven. The internal 0.1Ω high-side sense resistor on the LT1786F is rated for a maximum DC current of 1A. This resistor can be damaged by extremely high surge currents at start-up. The Royer converter typically uses a few microfarads of bypass capacitance at the center tap of the transformer. This capacitor charges up when the system is first powered by the battery pack or an AC wall adapter. The amount of current delivered at start-up can be very large if the total impedance in this path is small and the voltage source has high current capability. Linear Technology recommends LT1786F U W U U APPLICATIONS INFORMATION the use of an aluminum electrolytic for the transformer center-tap bypass capacitor with an ESR greater than or equal to 0.5Ω. This lowers the peak surge currents to an acceptable level. In general, the wire and trace inductance in this path also help reduce the di/dt of the surge current. This issue only exists with floating lamp circuits as grounded lamp circuits do not make use of the high-side sense resistor. Input Capacitor Type Caution must be used in selecting the input capacitor type for switching regulators. Aluminum electrolytics are electrically rugged and the lowest cost, but are physically large to meet required ripple current ratings, and size constraints (especially height) may preclude their use. Ceramic capacitors are now available in larger values and their high ripple current and voltage rating make them ideal for input bypassing. Solid tantalum capacitors would be a good choice except for a history of occasional failure when subjected to large current surges during start-up. The input bypass capacitor of regulators can see these high surges when a battery or high capacitance source is connected. Some manufacturers have developed tantalum capacitor lines specially tested for surge capability (AVX TPS series for instance), but even these units may fail if the input voltage surge approaches the capacitor’s maximum voltage rating. AVX recommends derating the capacitor voltage by 2:1 for high surge applications. Applications Support Linear Technology invests an enormous amount of time, resources and technical expertise in understanding, designing and evaluating backlight/LCD contrast solutions for system designers. The design of an efficient and compact LCD backlight system is a study of compromise in a transduced electronic system. Every aspect of the design is interrelated and any design change requires complete re-evaluation for all other critical design parameters. Linear Technology has engineered one of the most complete test and evaluation setups for backlight designs and understands the issues and tradeoffs in achieving a compact, efficient and economical customer solution. Linear Technology welcomes the opportunity to discuss, design, evaluate and optimize any backlight/LCD contrast system with a customer. For further information on backlight/LCD contrast designs, consult the References. References 1. Williams, Jim. August 1992. Illumination Circuitry for Liquid Crystal Displays. Linear Technology Corporation, Application Note 49. 2. Williams, Jim. August 1993. Techniques for 92% Efficient LCD Illumination. Linear Technology Corporation, Application Note 55. 3. Bonte, Anthony. March 1995. LT1182 Floating CCFL with Dual Polarity Contrast. Linear Technology Corporation, Design Note 99. 4. Williams, Jim. April 1995. A Precision Wideband Current Probe for LCD Backlight Measurement. Linear Technology Corporation, Design Note 101. 5. LT1182/LT1183/LT1184/LT1184F Data Sheet. CCFL/ LCD Contrast Switching Regulators. April 1995. Linear Technology Corporation. 6. Williams, Jim. November 1995. A Fourth Generation of LCD Backlight Technology. Linear Technology Corporation, Application Note 65. 17 LT1786F U TYPICAL APPLICATION nating high voltage lead length. Additionally, although the lamp receives differential drive, with its attendant low parasitic losses, the feedback signal is ground referred. Thus, the stacked secondaries afford floating lamp operating efficiency with grounded mode current certainty and line regulation. Dual Transformer CCFL Power Supply Space constraints may dictate utilization of two small transformers instead of a single, larger unit. Although this approach is somewhat more expensive, it can solve space problems and offers other attractive advantages. Figure 2’s approach is essentially a “grounded lamp” LT1786Fbased circuit. The transistors drive two transformer primaries in parallel. The transformer secondaries, stacked in series, provide the output. The relatively small transformers, each supplying half the load power, may be located directly at the lamp terminals. Aside from the obvious space advantage (particularly height), this arrangement minimizes parasitic wiring losses by elimi- L1 is directly driven, with winding 4-5 furnishing feedback in the normal fashion. L3, “slaved” to L1’s and L3’s interconnects must be laid out for low inductance to maintain waveform purity. The traces should be as wide as possible (e.g., 1/8") and overlaid to cancel inductive effects. 27pF LAMP 10 6 6 10 L3 L1 3 2 1 + 4 5 3 WIDE TRACE 1 + 2.2µF 2.2µF SEE TEXT AND NOTES 220k 1000pF 2 4 NC 0.1µF* WIDE TRACE 0.1µF* 100k 750Ω Q1-Q2 ZDT1048 BAT54 +VBAT L2 MBRS130L 1 2 3 4 1µF SHUTDOWN 5 6 7 8 PGND VSW ICCFL BULB DIO VC 16 15 14 BAT LT1786F 13 ROYER AGND VIN SHDN IOUT SMBSUS SCL ADR SDA 12 11 + 2.2µF 16V VIN 5V 10 9 TO SMBus HOST L1, L3 = COILTRONICS CTX110605 OVERLAY INDICATED TRACES BETWEEN L1 AND L3 L2 = COILTRONICS CTX100-4 * = WIMA MKI OR MKP-20 = PANASONIC ECH-U COILTRONICS (561) 241-7876 Figure 2. Dual Transformers Save Space and Minimize parasitic Losses While Maintaining Current Accuracy and Line Regulation. Trade-Off Is Increased Cost 18 1786 F02 5 NC LT1786F U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 5 6 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) 8 0.004 – 0.010 (0.101 – 0.254) 0° – 8° TYP 0.016 – 0.050 0.406 – 1.270 7 0.050 (1.270) TYP S16 0695 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT1786F U TYPICAL APPLICATION 90% Efficient Grounded CCFL with 2-Wire SMBus Control of Lamp Current LAMP 10 C2 27pF 3kV 6 L1 3 2 C7 1µF 3 ICCFL DIO CCFL VSW BULB BAT BAT 8V TO 28V R1 750Ω 1% Q1 16 L2 100µH 15 D1 1N5818 14 1786F TA03 LT1786F 13 4 CCFL VC ROYER 5 SHUTDOWN CCFL PGND 5 C3 2.2µF 35V Q2 1 4 C1 0.068µF R3 100k 1% D1 BAT85 1 + R2 221k 1% C5 1000pF 2 6 7 8 AGND VCC SHDN IOUT SMBSUS SCL ADR SDA 12 11 + 3V < VCC < 6.5V C4 2.2µF 10 9 TO SMBus HOST C1 MUST BE A LOW LOSS CAPACITOR C1 = WIMA MKI OR MKP-20 PANASONIC ECH-U L1 = COILTRONICS CTX210605 L2 = COILTRONICS CTX100-4 (DO NOT SUBSTITUTE COMPONENTS COILTRONICS (561) 241-7876) Q1, Q2 = ZETEX ZTX849 OR ROHM 25C5001 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1172 Current Mode Switching Regulator for CCFL or LCD Contrast Control 1.25A, 100kHz LT1173 Micropower DC/DC Converter for LCD Contrast Control 1A, 24kHz, Hysteretic LT1182 Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control 1.25A, 0.625A, 200kHz LT1183 Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control 1.25A, 0.625A, 200kHz LT1184 Current Mode Switching Regulator for CCFL Control 1.25A, 200kHz LT1184F Current Mode Switching Regulator for CCFL Control 1.25A, 200kHz LT1186F DAC Programmable Current Mode Switching Regulator for CCFL Control 1.25A, 200kHz, SPI or Pulse Mode LT1316 Micropower DC/DC Converter for LCD Contrast Control Programmable Peak Current Limit LT1372 Current Mode Switching Regulator for CCFL or LCD Contrast Contol 1.5A, 500kHz 20 Linear Technology Corporation 1786f LT/TP 0898 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1998