LINER LTC1708-PG

LTC1708-PG
Dual Adjustable 5-Bit VID
High Efficiency, 2-Phase Current Mode
Synchronous Buck DC/DC Controller
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FEATURES
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DESCRIPTIO
The LTC®1708 is a dual adjustable 5-bit VID programmable step-down switching regulator controller that drives
all N-Channel power MOSFET stages. A constant frequency current mode architecture allows adjustment of
the frequency up to 300kHz. Power loss and noise due to
the ESR of the input capacitance are minimized by operating the two main controller output stages out of phase.
Out-of-Phase Controllers Reduce Input Capacitance
and Power Supply Induced Noise
OPTI-LOOP® Compensation Minimizes COUT
Power Good Output Monitors Both Outputs
5-Bit Mobile VID Control, VOUT: 0.9V to 2.0V
Dual N-Channel MOSFET Synchronous Drive
±1% Output Voltage Accuracy
DC Programmed Fixed Frequency 150kHz to 300kHz
Wide VIN Range: 3.5V to 36V Operation
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Soft-Start Current Ramping
Foldback Output Current Limiting
Latched Short-Circuit Shutdown with Defeat Option
Output Overvoltage Protection
Remote Output Voltage Sense
Low Shutdown Current: 20µA
5V and 3.3V Standby Regulators
Selectable Constant Frequency, Burst Mode® and
Continuous Operation
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The precision 0.8V reference is compatible with future microprocessor generations, and a wide
3.5V to 30V (36V maximum) input supply range that
encompasses all battery chemistries. A power good output indicates when the output voltages are within 7.5% of
their programmed value.
A RUN/SS pin for each controller provides both soft-start
and an optional timed, short-circuit shutdown. Other
protection features include: internal foldback current limiting and an output overvoltage crowbar. The forced
continuous control pin (FCB) can be used to inhibit Burst
Mode operation or to regulate a third, flyback output.
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APPLICATIO S
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Notebook and Palmtop Computers, PDAs
Portable Instruments
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
+
4.7µF
D3
VIN
L1
1µH
CB1 0.47µF
BOOST1
BOOST2
VID0 TO VID4
COUT1a +
10µF
6.3V
CERAMIC
COUT1
270µF
2V
SP
×4
CC1
1500pF
RC1
22k
M3b
BG2
SENSE2 +
SENSE1–
SENSE2 –
RSENSE2
0.01Ω
VOUT2
1.5V
4A
EAIN2
ITH2
RUN/SS1 SGND RUN/SS2
CSS1
0.1µF
D2
1000pF
PGOOD
ITH1
VIN
4.75V TO 28V
PGND
SENSE1+
1000pF
ATTNIN
CIN
10µF
50V
CERAMIC
×4
L2
2.2µH
SW2
BG1
5 VID BITS
VOUT1
0.925V TO
2.00V
14.1A
CB2 0.1µF
LTC1708-PG
M2
RSENSE1
0.003Ω
M3a
TG2
SW1
D1
D4
VIDVCC INTVCC
TG1
M1
1µF
CERAMIC
CSS2
0.1µF
CC2
220pF
RC2
15k
R3
20k
1%
R4
63.4k
1%
COUT
180µF
4V
SP
+
M1: IRF7811
M2: 1RF7809
M3a, M3b: FDS6982
L1: VISHAY 5050CE
ATTNOUT CONNECTED TO EAIN1
1628 F01
Figure 1. High Efficiency VID Controlled, 2-Output Step-Down Converter
1708f
1
LTC1708-PG
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage (VIN).........................36V to – 0.3V
Topside Driver Voltages
(BOOST1, BOOST2) ...................................42V to – 0.3V
Switch Voltage (SW1, SW2) .........................36V to – 5V
INTVCC, EXTVCC, RUN/SS1, RUN/SS2,
(BOOST1-SW1), (BOOST2-SW2), ...............7V to – 0.3V
SENSE1+, SENSE2 +, SENSE1–,
SENSE2 – Voltages ....................... (1.1)INTVCC to – 0.3V
FREQSET, STBYMD, FCB, VIDVCC, VID0-4,
PGOOD Voltages ..........................................7V to – 0.3V
ITH1, ITH2, EAIN1, EAIN2, ATTNIN,
ATTNOUT Voltages ...................................2.7V to – 0.3V
Peak Output Current <10µs (TG1, TG2, BG1, BG2) ... 3A
INTVCC Peak Output Current ................................ 50mA
Operating Ambient Temperature Range
(Note 2) ...................................................–40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
RUN/SS1
1
36 PGOOD
SENSE1 +
2
35 TG1
SENSE1 –
3
34 SW1
EAIN1
4
33 BOOST1
FREQSET
5
32 VIN
STBYMD
6
31 BG1
FCB
7
30 EXTVCC
ITH1
8
29 INTVCC
SGND
9
28 PGND
3.3VOUT 10
ITH2 11
EAIN2 12
SENSE2 –
13
LTC1708EG-PG
27 BG2
26 BOOST2
25 SW2
24 TG2
SENSE2 + 14
23 RUN/SS2
ATTNOUT 15
22 VIDVCC
ATTNIN 16
21 VID4
VID0 17
20 VID3
VID1 18
19 VID2
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 85°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.792
0.800
0.808
V
Main Control Loops
VEAIN1, 2
Regulated Feedback Voltage
at EAIN Pin
(Note 4); ITH1, 2 Voltage = 1.2V
IEAIN1, 2
Feedback Current
(Note 4)
–5
– 50
nA
VREFLNREG
Reference Voltage Line Regulation
VIN = 3.6V to 30V (Note 4)
0.002
0.02
%/V
VLOADREG
Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop; ITH1, 2 Voltage = 1.2V to 0.7V ●
Measured in Servo Loop; ITH1, 2 Voltage = 1.2V to 2.0V ●
0.1
– 0.1
0.5
– 0.5
%
%
1.3
●
gm1, 2
Transconductance Amplifier gm
ITH1, 2 = 1.2V; Sink/Source 5µA; (Note 4)
mmho
gmOL1, 2
Transconductance Amplifier GBW
ITH1, 2 = 1.2V; (gm • ZL, No Ext Load) (Note 4)
3
IQ
Input DC Supply Current
Normal Mode
Standby
Shutdown
(Note 5)
EXTVCC Tied to GND; VID Inputs Open Circuit
VRUN/SS1, 2 = 0V, VSTBYMD > 2V
VRUN/SS1, 2 = 0V, VSTBYMD = Open
850
125
20
35
0.760
0.800
0.840
V
– 0.3
– 0.18
– 0.1
µA
V
MHz
VFCB
Forced Continuous Threshold
IFCB
Forced Continuous Current
VFCB = 0.85V
VBINHIBIT
Burst Inhibit Threshold
Measured at FCB pin
4.3
4.8
UVLO
Undervoltage Lockout
VIN Ramping Down
3.5
4
●
µA
µA
µA
V
1708f
2
LTC1708-PG
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VOV
Output Overvoltage Threshold
Measured at EAIN1, 2
0.84
0.86
0.88
ISENSE
Sense Pins Total Source Current
(Each Channel); VSENSE1–, 2 – = VSENSE1+, 2+ = 0V
– 85
– 60
VSTBYMD MS
Master Shutdown Threshold
VSTBYMD Ramping Down
0.4
VSTBYMD KA
Keep-Alive Power On-Threshold
VSTBYMD Ramping Up, RUNSS1, 2 = 0V
DFMAX
Maximum Duty Factor
In Dropout
98
99.4
%
IRUN/SS1, 2
Soft-Start Charge Current
VRUN/SS1, 2 = 1.9V
0.5
1.2
µA
VRUN/SS1, VRUN/SS2 Rising
1.0
1.5
1.9
4.1
4.5
V
2
4
µA
1.6
5
µA
75
75
85
88
mV
mV
VRUN/SS1, 2 ON RUN/SS Pin ON Threshold
VRUN/SS1, 2 LT
RUN/SS Pin Latchoff Threshold
VRUN/SS1, VRUN/SS2 Rising from 3V
ISCL1, 2
RUN/SS Discharge Current
Soft Short Condition EAIN1, 2 = 0.5V;
VRUN/SS1, 2 = 4.5V
ISDLHO
Shutdown Latch Disable Current
EAIN1, 2 = 0.5V
VSENSE(MAX)
Maximum Current Sense Threshold
VEAIN1, 2 = 0.7V; VSENSE1, 2 = 5V
VEAIN1, 2 = 0.7V; VSENSE1, 2 = 5V
0.5
●
65
62
V
µA
0.6
1.5
UNITS
V
2
V
V
TG1, 2 tr
TG1, 2 tf
TG Transition Time:
Rise Time
Fall Time
CLOAD = 3300pF (Note 10)
CLOAD = 3300pF (Note 10)
50
50
90
90
ns
ns
BG1, 2 tr
BG1, 2 tf
BG Transition Time:
Rise Time
Fall Time
CLOAD = 3300pF (Note 10)
CLOAD = 3300pF (Note 10)
40
40
90
80
ns
ns
TG/BG t1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver (Note 10)
90
ns
BG/TG t2D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver (Note 10)
90
ns
tON(MIN)
Minimum On-Time
Tested with a Square Wave (Notes 6, 10)
160
200
ns
5.0
5.2
V
0.2
1.0
%
120
240
mV
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
6V < VIN < 30V, VEXTVCC = 4V
VLDO INT
INTVCC Load Regulation
ICC = 0 to 20mA, VEXTVCC = 4V
VLDO EXT
EXTVCC Voltage Drop
ICC = 20mA, VEXTVCC = 5V
VEXTVCC
EXTVCC Switchover Voltage
ICC = 20mA, EXTVCC Ramping Positive
VLDOHYS
EXTVCC Hysteresis
4.8
●
4.5
4.7
V
0.2
V
Oscillator
fOSC
Oscillator Frequency
VFREQSET = Open (Note 7)
190
220
250
fLOW
fHIGH
IFREQSET
kHz
Lowest Frequency
VFREQSET = 0V
120
140
170
kHz
Highest Frequency
VFREQSET = 2.4V
280
310
350
kHz
FREQSET Input Current
VFREQSET = 0V
–2
–1
µA
3.3V Linear Regulator
V3.3OUT
3.3V Regulator Output Voltage
No Load
3.35
3.45
V
V3.3IL
3.3V Regulator Load Regulation
I3.3 = 0 to 10mA
0.5
2
%
V3.3VL
3.3V Regulator Line Regulation
6V < VIN < 30V
0.05
0.2
%
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
0.1
0.3
V
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
1
µA
VPG
PGOOD Trip Level
Relative to the 0.8V Regulated Feedback Voltage
EAIN1, 2 Ramping Negative from 0.8V
EAIN1, 2 Ramping Positive from 0.8V
–5
10
%
%
●
3.25
PGOOD Output
– 10
5
– 7.5
7.5
1708f
3
LTC1708-PG
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VID Parameters
VIDVCC
VID Operating Supply Voltage
IVIDVCC
VID Supply Current
2.7
RFBOUT1/SENSE1
Resistance Between ATTNIN/ATTNOUT
RRATIO
Resistor Ratio Accuracy
Programmed from 0.925V to 2.00V
RPULL-UP
VID0 to VID4 Pull-Up Resistance
(Note 9) VDIODE = 0.7V
VIDT
VID Voltage Threshold
IVIDLEAK
VID Input Leakage Current
(Note 9) VIDVCC < VIDVCC < 7V
VPULL-UP
VID Pull-Up Voltage
VIDVCC = 3V
VIDVCC = 3.3V (Note 8)
V
5
µA
10
5
kΩ
–0.35
0.25
%
40
0.4
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC1708EG-PG is guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC1708EG-PG: TJ = TA + (PD • 85°C/W)
Note 4: The LTC1708-PG is tested in a feedback loop that servos VITH1, 2
to a specified voltage and measures the resultant EAIN1, 2.
Note 5: The supply current is higher due to the gate charge being delivered
at the switching frequency. See Applications Information.
5.5
0.01
2.5
kΩ
1.0
1.6
V
0.1
1
µA
2.8
3.1
V
Note 6: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥ 40% of IMAX (see minimum on-time
considerations in the Applications Information section).
Note 7: VFREQSET pin internally tied to 1.19V reference through a large
resistance.
Note 8: With all five VID inputs floating (or tied to VIDVCC) the VIDVCC
current is typically < 1µA. However, the VIDVCC current will rise and be
approximately equal to the number of grounded VID input pins times
(VIDVCC – 0.6V)/40k. (See the Applications Information section.)
Note 9: Each built-in pull-up resistor attached to the VID inputs also has a
series diode to allow input voltages higher than the VIDVCC supply without
damage or clamping. (See Applications Information section.)
Note 10: Rise and fall times are measured at 20% to 80% levels. Delay
and nonoverlap times are measured using 50% levels.
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Output Current
(Figure 13)
Efficiency vs Output Current
and Mode (Figure 13)
100
100
Burst Mode
OPERATION
15A
70
60
50
CONSTANT FREQUENCY
MODE
40
20
VIN = 15V
VOUT1 = OFF
VOUT2 = 1.6V
10
0
0.1
15A
70
60
50
40
VOUT1 = OFF
VOUT2 = 1.6V
EXTVCC = 0V
90
VIN = 10V
VIN = 15V
VIN = 20V
IOUT = 7A
80
IOUT = 12A
70
30
PWM MODE
30
VIN = 5V
80
EFFICIENCY (%)
EFFICIENCY (%)
80
90
100
EXTVCC = 0V
EFFICIENCY (%)
90
Efficiency vs Input Voltage
(Figure 13)
10
1
OUTPUT CURRENT (A)
100
1708 G01
20
10
0
0.01
VFCB = OPEN
VOUT1 = OFF
VOUT2 = 1.6V
1
0.1
10
OUTPUT CURRENT (A)
100
1708 G02
60
50
5
10
15
20
INPUT VOLTAGE (V)
25
28
1708 G03
1708f
4
LTC1708-PG
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Input Voltage
and Mode (Figure 13)
1000
BOTH
CONTROLLERS ON
600
400
200
STANDBY
5.05
INTVCC AND EXTVCC SWITCH VOLTAGE (V)
EXTVCC VOLTAGE DROP (mV)
250
800
SUPPLY CURRENT (µA)
INTVCC and EXTVCC Switch
Voltage vs Temperature
EXTVCC Voltage Drop
200
150
100
50
SHUTDOWN
0
0
0
5
20
15
10
25
INPUT VOLTAGE (V)
30
35
0
10
30
20
CURRENT (mA)
40
4.85
4.80
EXTVCC SWITCHOVER THRESHOLD
4.75
4.70
– 50 – 25
50
50
25
75
0
TEMPERATURE (°C)
100
125
1708 G06
Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)
75
80
ILOAD = 1mA
70
5.0
60
4.8
4.7
50
VSENSE (mV)
4.9
VSENSE (mV)
INTVCC VOLTAGE (V)
4.90
Maximum Current Sense Threshold
vs Duty Factor
Internal 5V LDO Line Reg
25
4.6
50
40
30
20
4.5
10
0
4.4
0
5
20
15
25
10
INPUT VOLTAGE (V)
30
0
35
20
40
60
DUTY FACTOR (%)
80
50
100
0
25
75
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
1708 G09
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
Maximum Current Sense Threshold
vs VRUN/SS (Soft-Start)
80
0
100
1708 G08
1708 G07
Current Sense Threshold
vs ITH Voltage
90
80
VSENSE(CM) = 1.6V
80
70
76
40
60
VSENSE (mV)
VSENSE (mV)
60
VSENSE (mV)
4.95
1708 G05
1708 G04
5.1
INTVCC VOLTAGE
5.00
72
68
50
40
30
20
10
20
0
64
–10
–20
0
0
1
2
3
4
5
6
VRUN/SS (V)
1708 G10
60
0
1
3
4
2
COMMON MODE VOLTAGE (V)
5
1708 G11
–30
0
0.5
1
1.5
VITH (V)
2
2.5
1708 G12
1708f
5
LTC1708-PG
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
FCB = 0V
VIN = 15V
FIGURE 1
VOUT2
SENSE Pins Total Source Current
100
VEAIN = 0.7V
2.0
–0.2
50
ISENSE (µA)
–0.1
VITH (V)
NORMALIZED VOUT (%)
VITH vs VRUN/SS
2.5
0.0
1.5
1.0
–0.3
0
–50
0.5
–0.4
0
1
0
3
2
LOAD CURRENT (A)
4
5
0
2
1
3
4
5
6
–100
2
0
VRUN/SS (V)
4
6
VSENSE COMMON MODE VOLTAGE (V)
1708 G14
1708 G13
Maximum Current Sense
Threshold vs Temperature
1708 G15
Dropout Voltage vs Output Current
80
4
RUN/SS Current vs Temperature
1.8
VOUT = 5V
1.6
76
74
3
RUN/SS CURRENT (µA)
DROPOUT VOLTAGE (V)
VSENSE (mV)
78
2
RSENSE = 0.015Ω
1
72
RSENSE = 0.010Ω
1.4
1.2
1.0
0.8
0.6
0.4
0.2
70
–50 –25
0
50
25
0
75
TEMPERATURE (°C)
100
125
0
0.5
1.0 1.5 2.0 2.5 3.0
OUTPUT CURRENT (A)
3.5
4.0
100
125
Load Step (Figure 13)
VOUT
100mV/DIV
VOUT
100mV/DIV
IOUT
5A/DIV
10µs/DIV
1708 G22
VIN = 15V
VOUT2 = 1.6V
LOAD STEP = 100mA – 15A
CONSTANT FREQUENCY MODE: VFCB = VINTVCC
ACTIVE VOLTAGE POSITIONING CIRCUIT
0
25
50
75
TEMPERATURE (°C)
1708 G25
Load Step (Figure 13)
Load Step (Figure 13)
IOUT
5A/DIV
–25
1708 G18
1708 G17
VOUT
100mV/DIV
0
–50
IOUT
5A/DIV
VIN = 15V
10µs/DIV
VOUT2 = 1.6V
LOAD STEP = 100mA – 15A
Burst Mode OPERATION: VFCB = OPEN
ACTIVE VOLTAGE POSITIONING CIRCUIT
1708 G20
VIN = 15V
10µs/DIV
VOUT2 = 1.6V
LOAD STEP = 100mA – 15A
CONTINUOUS MODE: VFCB = 0V
ACTIVE VOLTAGE POSITIONING CIRCUIT
1708 G21
1708f
6
LTC1708-PG
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Constant Frequency (Burst Inhibit)
Operation (Figure 13)
Burst Mode Operation (Figure 13)
Soft-Start Up (Figure 13)
VRUN/SS
2V/DIV
VOUT
20mV/DIV
VOUT
20mV/DIV
IOUT
5A/DIV
IOUT
2A/DIV
VOUT
1V/DIV
IOUT
5A/DIV
VIN = 15V
VOUT2 = 1.6V
100ms/DIV
VIN = 15V
VOUT2 = 1.6V
VFCB = OPEN
IOUT = 250mA
1708 G19
Current Sense Input Current
vs Temperature
VIN = 15V
VOUT2 = 1.6V
VFCB = VINTVCC
IOUT = 250mA
1708 G23
EXTVCC Switch Resistance
vs Temperature
20µs/DIV
1708 G24
Oscillator Frequency
vs Temperature
10
35
350
33
31
29
27
50
25
0
75
TEMPERATURE (°C)
100
125
8
6
4
VFREQSET = OPEN
200
VFREQSET = 0V
150
100
50
0
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
0
– 50 – 25
50
25
75
0
TEMPERATURE (°C)
1708 G27
1708 G26
Undervoltage Lockout
vs Temperature
100
125
1708 G28
Shutdown Latch Thresholds
vs Temperature
4.5
3.50
3.45
3.40
3.35
3.30
3.25
3.20
–50 –25
250
2
SHUTDOWN LATCH THRESHOLDS (V)
25
–50 –25
300
FREQUENCY (kHz)
EXTVCC SWITCH RESISTANCE (Ω)
VFREQSET = 2.4V
UNDERVOLTAGE LOCKOUT (V)
CURRENT SENSE INPUT CURRENT (µA)
20µs/DIV
50
25
75
0
TEMPERATURE (°C)
100
125
1708 G29
LATCH ARMING
4.0
3.5
3.0
LATCHOFF
THRESHOLD
2.5
2.0
1.5
1.0
0.5
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1708 G30
1708f
7
LTC1708-PG
U
U
U
PI FU CTIO S
RUN/SS1, RUN/SS2 (Pins 1, 23): Combination of softstart, run control inputs and short-circuit detection timers.
A capacitor to ground at each of these pins sets the ramp
time to full output current. Forcing either of these pins
back below 1.0V causes the IC to shut down the circuitry
required for that particular controller. Latchoff overvoltage protection is also invoked via this pin as described in
the Applications Information section.
SENSE1+, SENSE2+ (Pins 2, 14): The (+) Input to the
Differential Current Comparators. The Ith pin voltage and
built-in offsets between the SENSE– and SENSE+ pins in
conjunction with RSENSE sets the current trip threshold.
SENSE1–, SENSE2– (Pins 3, 13): The (–) Input to the
Differential Current Comparators.
EAIN1, EAIN2 (Pins 4, 12): Receives the remotely sensed
feedback voltage for each controller from a resistive
divider across the output. The VID section may be used for
one resistive divider.
FREQSET (Pin 5): Frequency Control Input to the Oscillator. This pin can be left open, tied to ground, tied to INTVCC
or driven by an external voltage source. This pin can also
be used with an external phase detector to build a true
phase-locked loop.
STBYMD (Pin 6): Control pin that determines which circuitry remains active when the controllers are shut down
and/or provides a common control point to shut down
both controllers. See the Operation section for details.
FCB (Pin 7): Forced Continuous Control Input. This input
acts on both controllers and is normally used to regulate
a secondary winding using a resistive divider. An applied
input voltage below 0.8V will force continuous synchronous operation on both controllers. Do not leave this pin
floating.
ITH1, ITH2 (Pins 8, 11): Error Amplifier Output and Switching Regulator Compensation Point. Each associated channels’ current comparator trip point increases with this
control voltage.
SGND (Pin 9): Small-Signal Ground. Common to both
controllers, this pin must be routed separately from high
current grounds to the common (–) terminals of the
COUT capacitors.
3.3VOUT (Pin 10): Output of a linear regulator capable of
supplying 10mA DC with peak currents as high as 50mA.
ATTNOUT (Pin 15): Divided down output voltage feeding
the EAIN pin of the regulator. The VID inputs program a
resistive divider between ATTNIN and SGND. ATTNOUT is
the tap point on the divider. The voltage on ATTNOUT is
0.8V when the output is in regulation. This pin can be
bypassed to SGND with 50pF.
ATTNIN (Pin 16): Receives the remotely sensed feedback
voltage from the output.
VID0 to VID4 (Pins 17 to 21): Digital inputs for controlling
the output voltage from 0.925V to 2.0V. Table 1 specifies
the output voltage for the 32 combinations of digital
inputs. The LSB (VID0) represents 50mV increments in
the upper voltage range (2.00V to 1.30V) and 25mV
increments in the lower voltage range (1.275V to 0.925V).
Logic Low = GND, Logic High = VIDVCC or Float.
VIDVCC (Pin 22): VID Input Supply Voltage. Range from
2.7V to 5.5V. Typically this pin is tied to INTVCC.
PGND (Pin 28): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs, anode of the Schottky rectifier and the (–) terminal(s) of CIN.
INTVCC (Pin 29): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTVCC Switch. The driver and
control circuits are powered from this voltage source. Must
be decoupled to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor. The INTVCC regulator
standby function is determined by the STBYMD pin.
EXTVCC (Pin 30): External Power Input to an Internal
Switch Connected to INTVCC. This switch closes and
supplies VCC power, bypassing the internal low dropout
regulator, whenever EXTVCC is higher than 4.7V. See
EXTVCC connection in Applications Information section.
Do not exceed 7V on this pin.
BG1, BG2 (Pins 31, 27): High Current Gate Drives for
Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTVCC.
VIN (Pin 32): Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.
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BOOST1, BOOST2 (Pins 33, 26): Bootstrapped Supplies
to the Topside Floating Drivers. Capacitors are connected
between the boost and switch pins and Schottky diodes
are tied between the boost and INTVCC pins. Voltage swing
at the boost pins is from INTVCC to (VIN + INTVCC).
TG1, TG2 (Pins 35, 24): High Current Gate Drives for Top
N-Channel MOSFETs. These are the outputs of floating
drivers with a voltage swing equal to INTVCC – 0.5V
superimposed on the switch node voltage SW.
PGOOD (Pin 36): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage at either EAIN pin is not
within 7.5% of the setpoint.
SW1, SW2 (Pins 34, 25): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to VIN.
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FREQSET
VIN
INTVCC
1M
1.19V
CLK1
OSCILLATOR
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
CLK2
–
BOOST
0.86V
DROP
OUT
DET
+
PGOOD
VFB1
–
+
–
S
Q
R
Q
TG
TOP
BOT
DB
CB
+
CIN
D1
FCB
SW
TOP ON
0.74V
SWITCH
LOGIC
0.86V
INTVCC
BOT
BG
+
VFB2
4.5V
0.74V
–
+
I1
–
+
FCB
+
–
VREF
–
++
RSENSE
SLOPE
COMP
VIN
VIN
–
INTVCC
I2
–
+
30k SENSE
+
–
EXTVCC
5V
45k
45k
–
EA
+
5V
LDO
REG
OV
INTVCC
+
EAIN
0.800V
0.860V
ITH
INTERNAL
SUPPLY
SHDN
RST
4(VFB)
6V
STBYMD
VFB
+
–
1.2µA
SGND
CSEC
–
30k SENSE
2.4V
+
DSEC
3mV
0.86V
4(VFB)
–
4.8V
VOUT
BINH
+
0.8V
SHDN
–
FCB
3.3VOUT
+
0.6V
+
0.17µA
+
+
VSEC
COUT
PGND
–
RUN
SOFTSTART
CC
CC2 RC
RUN/SS
ATTNIN
CSS
ATTNOUT
R2
10k
5-BIT VID DECODER
R1
VARIABLE
40k
VID0 VID1 VID2 VID3 VID4
EACH VID
INPUT
VIDVCC
1708 F02
Figure 2
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OPERATIO (Refer to Functional Diagram)
Main Control Loop
The LTC1708 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal operation, each top MOSFET is turned on when the clock for that
channel sets the RS latch, and turned off when the main
current comparator, I1, resets the RS latch. The peak
inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of
each error amplifier EA. The EAIN pin receives the voltage
feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases,
it causes a slight decrease in EAIN relative to the 0.8V
reference, which in turn causes the ITH voltage to increase
until the average inductor current matches the new load
current. After the top MOSFET has turned off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I2, or
the beginning of the next cycle.
The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during
each off cycle through an external diode when the top
MOSFET turns off. As VIN decreases to a voltage close to
VOUT, the loop may enter dropout and attempt to turn on
the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 500ns
every tenth cycle to allow CB to recharge.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with the
ITH voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, the ITH pin voltage is
gradually released allowing normal, full-current operation. When both RUN/SS1 and RUN/SS2 are low, all
LTC1708 controller functions are shut down, and the
STBYMD pin determines if the standby 5V and 3.3V
regulators are kept alive.
Low Current Operation
The FCB pin is a multifunction pin providing two functions: 1) to provide regulation for a secondary winding by
temporarily forcing continuous PWM operation on
controller 1 and 2) select between two modes of low
current operation. When the FCB pin voltage is below
0.8V, the controller forces continuous PWM current
mode operation. In this mode, the top and bottom
MOSFETs are alternately turned on to maintain the output
voltage independent of direction of inductor current.
When the FCB pin is below VINTVCC␣ –␣ 2V but greater than
0.8V, the controller enters Burst Mode operation. Burst
Mode operation sets a minimum output current level
before inhibiting the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low currents, force the ITH pin below a voltage threshold that will
temporarily inhibit turn-on of both output MOSFETs until
the output voltage drops. There is 60mV of hysteresis in
the burst comparator B tied to the ITH pin. This hysteresis
produces output signals to the MOSFETs that turn them
on for several cycles, followed by a variable “sleep”
interval depending upon the load current. The resultant
output voltage ripple is held to a very small value by
having the hysteretic comparator after the error amplifier
gain block.
Constant Frequency Operation
When the FCB pin is tied to INTVCC, Burst Mode operation
is disabled and the forced minimum output current requirement is removed. This provides constant frequency,
discontinuous (preventing reverse inductor current) current operation over the widest possible output current
range. This constant frequency operation is not as efficient
as Burst Mode operation, but does provide a lower noise,
constant frequency operating mode down to approximately 1% of designed maximum output current.
Continuous Current (PWM) Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boosting the input supply to dangerous voltage levels—
BEWARE!
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OPERATIO
(Refer to Functional Diagram)
Frequency Setting
VID Control
The FREQSET pin provides frequency adjustment of the
internal oscillator from approximately 140kHz to 310kHz.
This input is nominally biased through an internal resistor
to the 1.19V reference, setting the oscillator frequency to
approximately 220kHz. This pin can be driven from an
external AC or DC signal source to control the instantaneous frequency of the oscillator.
Logic inputs VID0 to VID4 program an internal resistive
divider. The output voltage can be programmed in 50mV
and 25mV increments from 0.925V to 2.0V (see Table 1).
These logic input pins are internally pulled up to the
VIDVCC pin using separate internal series resistor/diode
paths. The diodes provide electrical isolation when the
logic pins are externally pulled up to a higher voltage
supply than VIDVCC.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open, an internal 5V low
dropout linear regulator supplies INTVCC power. If EXTVCC
is taken above 4.7V, the 5V regulator is turned off and an
internal switch is turned on connecting EXTVCC to INTVCC.
This allows the INTVCC power to be derived from a high
efficiency external source such as the output of the regulator itself or a secondary winding, as described in the
Applications Information.
Power Good (PGOOD)
Standby Mode Pin
The RUN/SS capacitors are used initially to limit the inrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out
circuit. If the output voltage falls to less than 70% of its
nominal output voltage, the RUN/SS capacitor begins
discharging on the assumption that the output is in an
overcurrent and/or short-circuit condition. If the condition
lasts for a long enough period as determined by the size of
the RUN/SS capacitor, both controllers will be shut down
until the RUN/SS pin’s voltages are recycled. This built-in
latchoff can be overridden by providing a >5µA pull-up at
a compliance of 5V to the RUN/SS pin(s). This current
shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor(s) during an overcurrent
and/or short-circuit condition. Foldback current limiting is
also activated when the output voltage falls below 70% of
its nominal level whether or not the short-circuit latchoff
circuit is enabled. Even if a short is present and the shortcircuit latchoff is not enabled, a safe, low output current is
provided due to internal current foldback and actual power
The STBYMD pin is a three-state input that controls
common circuitry within the IC as follows: When the
STBYMD pin is held at ground, both controller RUN/SS
pins are pulled to ground providing a single control pin to
shut down both controllers. When the pin is left open, the
internal RUN/SS currents are enabled to charge the
RUN/SS capacitor(s), allowing the turn-on of either controller and activating necessary common internal biasing.
When the STBYMD pin is taken above 2V, both internal
linear regulators are turned on independent of the state on
the RUN/SS pins of the two switching regulator controllers, providing an output power source for “wake-up”
circuitry. Decouple the pin with a small capacitor (0.01µF)
to ground if the pin is not connected to a DC potential.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.
The PGOOD pin is connected to an open drain of an internal
MOSFET. The MOSFET turns on when the outputs are not
both within ±7.5% of their nominal output levels as
determined by their feedback dividers. When both outputs
are within ±7.5% of their nominal values, the MOSFET is
turned off within 10µs and the pin is pulled up by an
external source
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
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OPERATIO (Refer to Functional Diagram)
wasted is low due to the efficient nature of the current
mode switching regulator.
expensive input capacitors to be used, reduces shielding
requirements for EMI and improves real world operating
efficiency.
THEORY AND BENEFITS OF 2-PHASE OPERATION
Figure 3 compares the input waveforms for a representative single-phase dual switching regulator to the new
LTC1628 2-phase dual switching regulator. An actual
measurement of the RMS input current under these conditions shows that 2-phase operation dropped the input
current from 2.53ARMS to 1.55ARMS. While this is an
impressive reduction in itself, remember that the power
losses are proportional to IRMS2, meaning that the actual
power wasted is reduced by a factor of 2.66. The reduced
input ripple voltage also means less power is lost in the
input power path, which could include batteries, switches,
trace/connector resistances and protection circuitry. Improvements in both conducted and radiated EMI also
directly accrue as a result of the reduced RMS input
current and voltage.
The LTC1708 dual high efficiency DC/DC controller, like the
LTC1628, brings the considerable benefits of 2-phase
operation to portable applications for the first time. Notebook computers, PDAs, handheld terminals and automotive electronics will all benefit from the lower input filtering
requirement, reduced electromagnetic interference (EMI)
and increased efficiency associated with 2-phase operation.
Why the need for 2-phase operation? Up until the LTC1628,
constant-frequency dual switching regulators operated
both channels in phase (i.e., single-phase operation). This
means that both switches turned on at the same time,
causing current pulses of up to twice the amplitude of
those for one regulator to be drawn from the input capacitor and battery. These large amplitude current pulses
increased the total RMS current flowing from the input
capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
With 2-phase operation, the two channels of the dualswitching regulator are operated 180 degrees out of
phase. This effectively interleaves the current pulses
drawn by the switches, greatly reducing the overlap time
where they add together. The result is a significant reduction in total RMS input current, which in turn allows less
Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows how
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
IIN(MEAS) = 2.53ARMS
(a)
DC236 F03a
IIN(MEAS) = 1.55ARMS
DC236 F03b
(b)
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation
for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The
Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows Less Expensive
Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
1708f
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LTC1708-PG
(Refer to Functional Diagram)
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer is
that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived “slope compensation” signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in singlephase dual switching regulators, but required the development of a new and proprietary technique to allow 2-phase
operation. In addition, isolation between the two channels
becomes more critical with 2-phase operation because
switch transitions in one channel could potentially disrupt
the operation of the other channel.
The LTC1708 is proof that these hurdles have been surmounted. The new device offers unique advantages for the
ever-expanding number of high efficiency power supplies
required in portable electronics.
15.0
SINGLE PHASE
DUAL CONTROLLER
12.5
INPUT RMS CURRENT (A)
U
OPERATIO
10.0
7.5
2-PHASE
DUAL CONTROLLER
5.0
2.5
0
VO1 = 5V/15A
VO2 = 3.3V/15A
0
10
20
30
INPUT VOLTAGE (V)
40
1708 F04
Figure 4. RMS Input Current Comparison
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APPLICATIO S I FOR ATIO
Figure 1 on the first page is a basic LTC1708 application
circuit. External component selection is driven by the load
requirement, and begins with the selection of RSENSE.
Once RSENSE is known, L can be chosen. Next, the power
MOSFETs and D1 are selected. Finally, CIN and COUT are
selected . The circuit shown in Figure 1 can be configured
for operation up to an input voltage of 28V (limited by the
external MOSFETs).
RSENSE Selection For Output Current
RSENSE is chosen based on the required output current.
The LTC1708 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of
SGND to 1.1(INTVCC). The current comparator threshold
sets the peak of the inductor current, yielding a maximum
average output current IMAX equal to the peak value less
half the peak-to-peak ripple current, ∆IL.
Allowing a margin for variations in the LTC1708 and
external component values yields:
RSENSE =
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability criterion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reducton
in peak output current level depending upon the operating
duty factor.
Selection of Operating Frequency
The LTC1708 uses a constant frequency architecture with
the frequency determined by an internal oscillator capacitor. This internal capacitor is charged by a fixed current
plus an additional current that is proportional to the
voltage applied to the FREQSET pin.
A graph for the voltage applied to the FREQSET pin vs
frequency is given in Figure 5. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.
50mV
IMAX
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APPLICATIO S I FOR ATIO
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
FREQSET PIN VOLTAGE (V)
2.5
2.0
1.5
Inductor Core Selection
1.0
0.5
0
120
170
220
270
OPERATING FREQUENCY (kHz)
320
1708 F05
Figure 5. FREQSET Pin Voltage vs Frequency
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN:
∆IL =
 V

1
VOUT  1 – OUT 
( f)(L)
VIN 

Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL=0.3(IMAX). Remember, the
maximum ∆IL occurs at the maximum input voltage.
Power MOSFET and D1 Selection
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see
EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only
exception is if low input voltage is expected (VIN < 5V);
Two external power MOSFETs must be selected for each
controller with the LTC1708: One N-channel MOSFET for
each top (main) switch, and one N-channel MOSFET for
each bottom (synchronous) switch.
Kool Mµ is a registered trademark of Magnetics, Inc.
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then, sub-logic level threshold MOSFETs (VGS(TH) < 3V)
should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level
MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “on”
resistance RSD(ON), input capacitance, input voltage and
maximum output current.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 6).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gateto-drain capacitance. The flat portion of the curve is the
result of the Miller capacitance effect of the drain-tosource capacitance as the drain drops the voltage across
the current source load. The upper sloping line is due to
the drain-to-gate accumulation capacitance and the gateto-source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given VDS drain voltage, but can be
adjusted for different VDS voltages by multiplying by the
ratio of the application VDS to the curve specified VDS
values. A way to estimate the CMILLER term is to take the
change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage
specified. CMILLER is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. CRSS
and COS are specified sometimes but definitions of these
parameters are not included.
VIN
MILLER EFFECT
V
VGS
a
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
+V
DS
–
–
3732 F06
Figure 6. Gate Charge Characteristic
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =
VOUT
VIN
V –V 
Synchronous Switch Duty Cycle =  IN OUT 
VIN


The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
2
I

V
PMAIN = OUT  MAX  1 + δ RDS(ON) +
VIN  N 
2 IMAX
VIN
( )
( )(
)
RDR C MILLER •
2N

1
1 
+

f
 VCC – VTH VTH 
()
2
PSYNC
I

V –V
= IN OUT  MAX  1 + δ RDS(ON)
VIN
 N 
( )
where N is the number of output stages, δ is the temperature dependency of RDS(ON), RDR is the effective top driver
resistance (approximately 4Ω at VGS = VMILLER), VIN is the
drain potential and the change in drain potential in the
particular application. VTH is the data sheet specified
typical gate threshold voltage specified in the power
MOSFET data sheet at the operating drain current. CMILLER
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
The term (1+δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the deadtime and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high VIN. A 1A to 3A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.
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CIN and COUT Selection
The selection of CIN is simplified by the multiphase architecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the input RMS ripple current from this maximum value
(see Figure 4). The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor
of 30% to 70% when compared to a single phase power
supply solution.
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selection process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20µF to 40µF is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramic voltage
coefficients are very high and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics’ higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22µF or two to three 10µF ceramic capacitors are an ideal choice in a 20W to 35W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also consider parallel ceramic and high quality electrolytic capacitors as an effective means of achieving ESR and bulk
capacitance goals.
In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current of one channel must
be used. The maximum RMS capacitor current is given by:
CIN Re quiredIRMS ≈ IMAX
[V (V
OUT
IN − VOUT
)]
1/ 2
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
The benefit of the LTC1708 multiphase can be calculated
by using the equation above for the higher power controller and then calculating the loss that would have resulted
if both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the interleaving of current pulses through
the input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case controller is adequate for the dual controller design. Remember
that input protection fuse resistance, battery resistance
and PC board trace resistance losses are also reduced due
to the reduced peak currents in a multiphase system. The
overall benefit of a multiphase design will only be fully
realized when the source impedance of the power supply/
battery is included in the efficiency testing. The drains of
the two top MOSFETS should be placed within 1cm of each
other and share a common CIN(s). Separating the drains
and CIN may produce undesirable voltage and current
resonances at VIN.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering.
The output ripple (∆VOUT) is determined by:
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
1 
∆VOUT ≈ ∆IL  ESR +

8fC OUT 

Where f = operating frequency, COUT = output capacitance,
and ∆IL= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3IOUT(MAX) the output
ripple will typically be less than 50mV at max VIN assuming:
COUT Recommended ESR < 2 RSENSE
and COUT > 1/(8fRSENSE)
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guarantees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output
capacitors selected.
Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR
but have lower storage capacity per unit volume than other
capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors can be used in cost-driven applications providing that consideration is given to ripple current
ratings, temperature and long term reliability. A typical
application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above
mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor
types include Nichicon PL series, NEC Neocap, Pansonic
SP and Sprague 595D series. Consult manufacturers for
other specific recommendations.
INTVCC Regulator
An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. INTVCC powers
the drivers and internal circuitry within the LTC1708. The
INTVCC pin regulator can supply a peak current of 50mA
and must be bypassed to ground with a minimum of
4.7µF tantalum, 10µF special polymer, or low ESR type
electrolytic capacitor. A 1µF ceramic capacitor placed
directly adjacent to the INTVCC and PGND IC pins is highly
recommended. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between channels.
Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1708 to be
exceeded. The system supply current is normally dominated by the gate charge current. Additional external
loading of the INTVCC and 3.3V linear regulators also
needs to be taken into account for the power dissipation
calculations. The total INTVCC current can be supplied by
either the 5V internal linear regulator or by the EXTVCC
input pin. When the voltage applied to the EXTVCC pin is
less than 4.7V, all of the INTVCC current is supplied by the
internal 5V linear regulator. Power dissipation for the IC in
this case is highest: (VIN)(IINTVCC), and overall efficiency
is lowered. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be esti1708f
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mated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC1708 VIN
current is limited to less than 24mA from a 24V supply
when not using the EXTVCC pin as follows:
TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C
Use of the EXTVCC input pin reduces the junction temperature to:
TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C
Dissipation should be calculated to also include any added
current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN.
EXTVCC Connection
The LTC1708 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
When the voltage applied to EXTVCC rises above 4.7V, the
internal regulator is turned off and the switch closes,
connecting the EXTVCC pin to the INTVCC pin thereby
supplying internal power. The switch remains closed as
long as the voltage applied to EXTVCC remains above 4.5V.
This allows the MOSFET driver and control power to be
derived from the output during normal operation (4.7V <
VOUT < 7V) and from the internal regulator when the output
is out of regulation (start-up, short-circuit). If more current is required through the EXTVCC switch than is specified, an external Schottky diode can be added between the
EXTVCC and INTVCC pins. Do not apply greater than 7V to
the EXTVCC pin and ensure that EXTVCC␣ <␣ VIN.
Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
supply means connecting the EXTVCC pin directly to VOUT.
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTVCC power
from the output.
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC Left Open (or Grounded). This will cause INTVCC
to be powered from the internal 5V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.
2. EXTVCC Connected directly to VOUT. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
3. EXTVCC Connected to an External supply. If an external
supply is available in the 5V to 7V range, it may be used to
power EXTVCC providing it is compatible with the MOSFET
gate drive requirements.
4. EXTVCC Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with either the inductive boost
winding as shown in Figure 7a or the capacitive charge
pump shown in Figure 7b. The charge pump has the
advantage of simple magnetics.
1µF
+
+
CIN
CIN
+
N-CH
BAT85
VIN
VSEC
VIN
LTC1708-PG
+
VIN
VIN
OPTIONAL EXTVCC
CONNECTION
5V < VSEC < 7V
RSENSE
VOUT
SW
FCB
BG1
T1
1:N
R6
VOUT
EXTVCC
COUT
COUT
BG1
N-CH
N-CH
SGND
L1
SW
+
+
R5
BAT85
VN2222LL
TG1
RSENSE
EXTVCC
BAT85
N-CH
LTC1708-PG
1µF
TG1
0.22µF
PGND
PGND
1708 F07a
Figure 7a. Secondary Output Loop & EXTVCC Connection
1708 F07b
Figure 7b. Capacitive Charge Pump for EXTVCC
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Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the functional diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: VBOOST =
VIN + VINTVCC. The value of the boost capacitor CB needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.
The LSB (VID0) represents 50mV increments in the upper
voltage range (1.30V to 2.00V) and 25mV increments in
the lower voltage range (0.925V to 1.275V). The MSB is
VID4. When all bits are low, or grounded, the output
voltage is 2.00V.
Table 1. VID Output Voltage Programming
VID4
VID3
VID2
VID1
VID0
VOUT (V)
0
0
0
0
0
2.000V
0
0
0
0
1
1.950V
0
0
0
1
0
1.900V
0
0
0
1
1
1.850V
0
0
1
0
0
1.800V
0
0
1
0
1
1.750V
0
0
1
1
0
1.700V
0
0
1
1
1
1.650V
0
1
0
0
0
1.600V
0
1
0
0
1
1.550V
0
1
0
1
0
1.500V
0
1
0
1
1
1.450V
0
1
1
0
0
1.400V
0
1
1
0
1
1.350V
0
1
1
1
0
1.300V
0
1
1
1
1
*
1
0
0
0
0
1.275V
1
0
0
0
1
1.250V
1
0
0
1
0
1.225V
1
0
0
1
1
1.200V
1
0
1
0
0
1.175V
1
0
1
0
1
1.150V
1
0
1
1
0
1.125V
1
0
1
1
1
1.100V
1
1
0
0
0
1.075V
The output voltage of the first controller is digitally set to
levels between 0.925V and 2.00V using the voltage identification (VID) inputs VID0 to VID4. The internal 5-bit DAC
configured as a precision resistive voltage divider sets the
output voltage in 50mV or 25mV increments according to
Table 1.
1
1
0
0
1
1.050V
1
1
0
1
0
1.025V
1
1
0
1
1
1.000V
1
1
1
0
0
0.975V
1
1
1
0
1
0.950V
1
1
1
1
0
0.925V
The VID codes (00000-11110) are engineered to be compatible with Intel Mobile Pentium® II and Pentium III
processor specifications for output voltages from 0.925V
to 2.00V.
1
1
1
1
1
**
Output Voltage Programming
The LTC1708 output voltages are set by the VID logic
inputs for the first controller and by an external feedback
resistive divider carefully placed across the output capacitor for the second controller. The resultant feedback signal
is compared with the internal precision 0.800V voltage
reference by the error amplifier. The output voltage is
given by the equation:
 R2 
VOUT = 0.8 V 1 + 
 R1
Note: *, ** represent codes without a defined output voltage as specified in
Intel specifications. The LTC1708 interprets these codes as valid inputs and
produces output voltages as follows: [01111] = 1.250V, [11111] = 0.900V.
Pentium is a registered trademark of Intel Corporation.
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Between the ATTNOUT pin and ground is a variable resistor, R1, whose value is controlled by the five input pins (VID0
to VID4). Another resistor, R2, between the ATTNIN and
the ATTNOUT pins completes the resistive divider. The
output voltage is thus set by the ratio of (R1 + R2) to R1.
The LTC1708 has remote sense capability. The top of the
internal resistive divider is connected to ATTNIN, and it is
referenced to the SGND pin. This allows a Kelvin connection for remotely sensing the output voltage directly across
the load, eliminating any PC board trace resistance errors.


0.8 V
R1(MAX ) = 24k 

 2.4V – VOUT 
for VOUT < 2.4V
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32K. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the VEAIN
feedback current.
Each VID digital input is pulled up by a 40k resistor in
series with a diode from VIDVCC. Therefore, it must be
grounded to get a digital low input, and can be either
floated or connected to VIDVCC to get a digital high input.
The series diode is used to prevent the digital inputs from
being damaged or clamped if they are driven higher than
VIDVCC. The digital inputs accept CMOS voltage levels.
Soft-Start/Run Function
VIDVCC is the supply voltage for the VID section. It is
normally connected to INTVCC but can be driven from
other sources such as a 3.3V supply. If it is driven from
another source, that source MUST be in the range of 2.7V
to 5.5V and MUST be alive prior to enabling the LTC1708.
An internal 1.2µA current source charges up the CSS
capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/
RSENSE to 75mV/RSENSE. The output current limit ramps
up slowly, taking an additional 1.25s/µF to reach full
current. The output current thus ramps up slowly, reducing the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
SENSE+/SENSE– Pins
The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTVCC. Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTVCC. A differential NPN input
stage is biased with internal resistors from an internal
2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pins to the main output. The output can be easily preloaded
by the VOUT resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:
ISENSE+ + ISENSE– = (2.4V – VOUT)/24k
Since VEAIN is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 8 to have a maximum value to
absorb this current.
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC1708. Soft-start reduces the input power
source’s surge currents by gradually increasing the
controller’s current limit (proportional to VITH). This pin
can also be used for power supply sequencing.
(
)
tDELAY =
1.5V
CSS = 1.25s / µF CSS
1.2µA
tIRAMP =
3V − 1.5V
CSS = 1.25s / µF CSS
1.2µA
(
)
By pulling both RUN/SS pins below 1V and/or pulling the
STBYMD pin below 0.2V, the LTC1708 is put into low
current shutdown (IQ = 20µA). The RUN/SS pins can be
driven directly from logic as shown in Figure 8. Diode D1
in Figure 8 reduces the start delay but allows CSS to ramp
up slowly providing the soft-start function. Each RUN/SS
pin has an internal 6V zener clamp (See Functional
Diagram).
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VIN
3.3V OR 5V
D1
INTVCC
RUN/SS
RSS*
RSS*
RUN/SS
CSS
CSS
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
(a)
(b)
1708 F07
Figure 8. RUN/SS Pin Interfacing
Fault Conditions: Overcurrent Latchoff
The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
The RUN/SS capacitor, CSS, is used initially to turn on and
limit the inrush current. After the controller has been
started and been given adequate time to charge up the
output capacitor and provide full load current, the RUN/SS
capacitor is used for a short-circuit timer. If the regulator’s
output voltage falls to less than 70% of its nominal value
after CSS reaches 4.1V, CSS begins discharging on the
assumption that the output is in an overcurrent condition.
If the condition lasts for a long enough period as determined by the size of the CSS and the specified discharge
current, the controller will be shut down until the RUN/SS
pin voltage is recycled. If the overload occurs during startup, the time can be approximated by:
tLO1 ≈ [CSS (4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)
= 2.7 • 106 (CSS)
If the overload occurs after start-up the voltage on CSS will
begin discharging from the zener clamp voltage:
tLO2 ≈ [CSS (6 – 3.5)]/(1.2µA) = 2.1 • 106 (CSS)
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin as shown
in Figure 8. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor
during an over current condition. Tying this pull-up resistor to VIN as in Figure 8a, defeats overcurrent latchoff.
Diode-connecting this pull-up resistor to INTVCC , as in
Figure 8b, eliminates any extra supply current during
controller shutdown while eliminating the INTV CC loading
from preventing controller start-up.
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capacitance is given by:
CSS > (COUT )(VOUT) (10 – 4) (RSENSE)
The minimum recommended soft-start capacitor of
CSS = 0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The LTC1708 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current
of 75mV/RSENSE. The maximum value of current limit
generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the highest power
dissipation in the top MOSFET.
The LTC1708 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
output falls below 70% of its nominal output level, then the
maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the LTC1708 will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN) of
the LTC1708 (less than 200ns), the input voltage and
inductor value:
∆IL(SC) = tON(MIN) (VIN/L)
The resulting short-circuit current is:
ISC =
25mV 1
+ ∆IL(SC)
RSENSE 2
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Fault Conditions: Overvoltage Protection (Crowbar)
Frequency of Operation
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.
The LTC1708 has an internal voltage controlled oscillator.
The frequency of this oscillator can be varied over a 2 to 1
range. The pin is internally self-biased at 1.19V, resulting
in a free-running frequency of approximately 220kHz. The
FREQSET pin can be grounded to lower this frequency to
approximately 140kHz or tied to the INTVCC pin to yield
approximately 310kHz. The FREQSET pin may be driven
with a voltage from 0 to INTVCC to fix or modulate the
oscillator frequency as shown in Figure 5.
A comparator monitors the output for overvoltage conditions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if VOUT returns to a safe level,
normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.
The Standby Mode (STBYMD) Pin Function
The Standby Mode (STBYMD) pin provides several choices
for start-up and standby operational modes. If the pin is
pulled to ground, the RUN/SS pins for both controllers are
internally pulled to ground, preventing start-up and thereby
providing a single control pin for turning off both controllers at once. If the pin is left open or decoupled with a
capacitor to ground, the RUN/SS pins are each internally
provided with a starting current enabling external control
for turning on each controller independently. If the pin is
provided with a current of >3µA at a voltage greater than
2V, both internal linear regulators (INTVCC and 3.3V) will
be on even when both controllers are shut down. In this
mode, the onboard 3.3V and 5V linear regulators can
provide power to keep-alive functions such as a keyboard
controller. This pin can also be used as a latching “on” and/
or latching “off” power switch if so designed.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC1708 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that
tON(MIN) <
VOUT
VIN( f)
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1708 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC1708 is generally less
than 200ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
when the FCB pin drops below 0.8V. During continuous
mode, current flows continuously in the transformer primary. The secondary winding(s) draw current only when
the bottom, synchronous switch is on. When primary load
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currents are low and/or the VIN/VOUT ratio is low, the
synchronous switch may not be on for a sufficient amount
of time to transfer power from the output capacitor to the
secondary load. Forced continuous operation will support
secondary windings providing there is sufficient synchronous switch duty factor. Thus, the FCB input pin removes
the requirement that power must be drawn from the
inductor primary in order to extract power from the
auxiliary windings. With the loop in continuous mode, the
auxiliary outputs may nominally be loaded without regard
to the primary output load.
Voltage Positioning
The secondary output voltage VSEC is normally set as
shown in Figure 6a by the turns ratio N of the transformer:
The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The
worst-case peak-to-peak output voltage deviation due to
transient loading can theoretically be reduced to half or
alternatively the amount of output capacitance can be
reduced for a particular application. A complete explanation is included in Design Solutions 10 or the LTC1736
data sheet. (See www.linear.com)
VSEC ≅ (N + 1) VOUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then VSEC will droop. An external resistive divider from
VSEC to the FCB pin sets a minimum voltage VSEC(MIN):
 R6 
VSEC(MIN) ≈ 0.8 V 1 + 
 R5 
If VSEC drops below this level, the FCB voltage forces
temporary continuous switching operation until VSEC is
again above its minimum.
In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.18µA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
The following table summarizes the possible states available on the FCB pin:
Table 2
FCB Pin
Condition
0V to 0.75V
Forced Continuous (Current Reversal
Allowed—Burst Inhibited)
0.85V < VFCB < 4.3V
Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Feedback Resistors
Regulating a Secondary Winding
>4.8V
Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
Voltage positioning can be used to minimize peak-to-peak
output voltage excursion under worst-case transient loading conditions. The open-loop DC gain of the control loop
is reduced depending upon the maximum load step specifications. Voltage positioning can easily be added to the
LTC1708 by loading the ITH pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 9).
VOUT
INTVCC
RT2
R2
ITH
RT1
RC
EAIN
LTC1708-PG
R1
CC
1708 F09
Figure 9. Active Voltage Positioning Applied to the LTC1708
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1708 circuits: 1) LTC1708 VIN current (including loading on the 3.3V internal regulator), 2) INTVCC
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regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VIN current has two components: the first is the DC
supply current given in the Electrical Characteristics table,
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. VIN current typically results in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, IGATECHG =f(QT+QB), where QT and QB
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTVCC power through the EXTVCC switch input
from an output-derived source will scale the VIN current
required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approximately 2.5mA of VIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and RSENSE,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of
L, RSENSE and ESR to obtain I2R losses. For example, if
each RDS(ON) = 10mΩ, RL = 5mΩ, RSENSE = 3mΩ and
RESR = 10mΩ (sum of both input and output capacitance
losses), then the total resistance is 28mΩ. This results in
losses ranging from 3% to 8% as the output current
increases from 5A to 15A for a 5V output, or an 8% to 20%
loss for a 1.6V output. Efficiency varies as the inverse
square of VOUT for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) VIN2 IO(MAX) CRSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a
maximum of 20mΩ to 50mΩ of ESR. The LTC1708 2phase architecture typically halves this input capacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTILOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response. Assuming a
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predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 100%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal cannot
be used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by
decreasing CC. If RC is increased by the same factor that
CC is decreased, the zero frequency will be kept the same,
thereby keeping the phase the same in the most critical
frequency range of the feedback loop. The output voltage
settling behavior is related to the stability of the closedloop system and will demonstrate the actual overall supply
performance.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current to
about 200mA.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery and
double-battery.
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 10 is the most straight
forward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse-battery,
while the transient suppressor clamps the input voltage
during load-dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1708 has a maximum input
voltage of 36V, most applications will be limited to 30V by
the MOSFET BVDSS.
50A IPK RATING
12V
VIN
LTC1708-PG
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
1708 F10
Figure 10. Automotive Application Protection
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Design Example
As a design example for one channel, assume VIN =
12V(nominal), VIN = 22V(max), VOUT = 1.6V, IMAX = 14A,
and f = 300kHz, RSENSE can immediately be calculated:
RSENSE = 50mV/14A ≈ 0.0035Ω → 0.003Ω
Tie the FREQSET pin to the INTVCC pin for 300kHz operation, or use a resistive divider from INTVCC according to
Figure 5 to reduce the operating frequency.
Assume a 1µH inductor and check the actual value of the
ripple current. The following equation is used:
 V

V
∆IL = OUT  1 – OUT 
( f)(L) 
VIN 
The highest value of the ripple current occurs at the
maximum input voltage:
∆IL =
 1.6V 
1.6V
1–
 = 4.95A
300kHz(1µH)  22V 
The ripple current is 35% of maximum output current.
Increasing the ripple current will also help ensure that the
minimum on-time of 200ns is not violated. The minimum
on-time occurs at maximum VIN:
tON(MIN) =
VOUT
VIN(MAX)f
=
1.6 V
= 242ns
22V(300kHz)
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins current.


0.8V
R1(MAX) = 24k

 2.4V – VOUT 

0.8V 
= 24K
 = 24k
 2.4V – 1.6V 
Choosing 1% resistors; R1 = R2 = 20k yields an output
voltage of 1.600V. If the VID section of the LTC1708-PG is
used, R1 will range from a value of 6.6k to 64k. If the forced
continuous mode is not selected and the programmed
voltage is less than 1.4V with no external load, it is
necessary to preload the output in order to prevent the
current comparator input bias current from causing the
output voltage to rise above the designed level. A 16k
preload resistor will prevent this from happening for all
programmed output voltages down to the minimum 0.925V
level.
The top driver output resistance at the MOSFET threshold
is approximately 4Ω. The power dissipation on the topside
MOSFET can be easily estimated. Choosing a International
Rectifier IRF7809/IRF7811 combination results in; RDS(ON)
= 0.012Ω, CMILLER = 4nC/16V =250pF. At maximum input
voltage with T(estimated) = 50°C:
( ) [1+ (0.005)(50°C – 25°C )]

2
(0.012Ω) + (22)  142A  (4Ω)(250pF )(300kHz)
PMAIN =
1.6V
14
22V
2
= 1.2W
A short-circuit to ground will result in a folded back current
of:
ISC =
25mV
1  200ns(22V)
+ 
= 10.5A
0.003Ω 2 
1µH 
with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1
for an IRF7809. The resulting power dissipated in the
bottom MOSFET is:
(
22V – 1.6V
10.5A
22V
= 1W
PSYNC =
) (1.1)(0.009Ω)
2
which is less than full-load conditions.
CIN is chosen for an RMS current rating of at least 5A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.01Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR(∆IL) = 0.01Ω(4.95A) = 50mVP–P
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PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1708. These items are also illustrated graphically in
the layout diagram of Figure 11. The Figure 12 illustrates
the current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at CIN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined LTC1708 signal ground pin and the ground
return of CINTVCC must return to the combined COUT (–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to the
(–) terminals of the input capacitor by placing the
POWER GOOD
2
3
4
INTVCC
5
6
7
8
10
11
12
13
14
15
16
17
18
SENSE1 +
TG1
SENSE1 –
SW1
EAIN1
BOOST1
FREQSET
VIN
STBYMD
BG1
FCB
EXTVCC
ITH1
INTVCC
SGND
PGND
36
INTVCC
35
VOUT1
34
33
32
31
30
29
+
9
PGOOD
+
INTVCC
RUN/SS1
+
1
28
VIN
LTC1708-PG
27
BG2
3.3VOUT
ITH2
BOOST2
EAIN2
SW2
SENSE2 –
TG2
SENSE2 +
RUN/SS2
ATTNOUT
VIDVCC
ATTNIN
VID4
VID0
VID3
VID1
VID2
26
25
24
VOUT2
23
22
21
20
19
VID CONTROL
INPUTS
1708 F11
Figure 11. LTC1708 Recommended Printed Circuit Layout Diagram
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capacitors next to each other and away from the Schottky
loop described above.
3. Do the LTC1708 feedback resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The R2 (Figure 8) connection should not be along
the high current input feeds from the input capacitor(s).
4. Are the SENSE – and SENSE + leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE + and SENSE – should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections.
SW1
5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve noise
performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC1708 and occupy minimum PC trace area.
L1
D1
RSENSE1
COUT1
VOUT1
+
RL1
VIN
RIN
CIN
+
SW2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
D2
L2
RSENSE2
COUT2
VOUT2
+
RL2
1628 F12
Figure 12. Branch Current Waveforms
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7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the application. The frequency of operation should be maintained
over the input voltage range down to dropout and until the
output load drops below the low current operation threshold—typically 10% to 20% of the maximum designed
current level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for their individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current comparator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5µA can be provided to the RUN/
SS pin(s) by resistors from VIN to prevent the short-circuit
latchoff from occurring.
Reduce VIN from its nominal level to verify operation of the
regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If problems coincide with high input voltages and low output
currents, look for capacitive coupling between the BOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are encountered with high current output loading at lower input
voltages, look for inductive coupling between CIN, Schottky
and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still be
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
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0.1µF
100Ω
100Ω
1
2
180pF
3
1000pF
4.3k
TG1
SENSE1 –
SW1
INTVCC
VIN
1M 6
EAIN1
FREQSET
STBYMD
BOOST1
VIN
BG1
0.1µF
33
31
10Ω
FCB
68k
12
160k
13
1000pF
100Ω
1000pF
14
15
16
17
18
ITH2
BOOST2
EAIN2
SW2
SENSE2 –
TG2
SENSE2 +
RUN/SS2
ATTNOUT
VIDVCC
ATTNIN
VID4
VID0
VID3
VID1
VID2
+
11
10µF
35V
×3
M2
26
+
1000pF
15k
M1b
M3
D2
B340A
0.47µF
25
0.003Ω
24
22
INTVCC
21
270µF 2V
PANASONIC SP
×4
10µF
6.3V
CER
VOUT2
0.925V TO 2V
14A
L2
1µH
23
VIN
7.5V TO 24V
180µF 4V
PANASONIC SP
+
33pF
M1a
32
+
470pF
100Ω
VOUT1
1.5V/2.5A
PEAK
34
CMDSH-3TR
30 5V
EXTVCC
(OPTIONAL)
0.1µF
LTC1708-PG
29
8
INTVCC
ITH1
1µF
33pF
4.7µF
28
9
10V
SGND
PGND
CMDSH-3TR
27
10
3.3VOUT
BG2
7
INTVCC
L1
2.2µH
35
+
10k
SENSE1 +
100k
36
+
0.01µF
INTVCC
4
5
10k
PGOOD
0.02Ω
17.5k
1%
20k
1%
RUN/SS1
TIGHTLY COUPLE
THESE CURRENT
SENSING FEEDBACK
PATHS
POWER GOOD
TIGHTLY COUPLE
THESE CURRENT
SENSING FEEDBACK
PATHS
20
19
VID CONTROL
INPUTS
0.1µF
1708 F13
VIN: 12V TO 22V
VOUT1: 1.5V/2.5A
VOUT2: 0.925V TO 2V/14A
SWITCHING FREQUENCY: 250kHz
M1a, M1b: FDS6982S
M2: IRF7811W
M3: ZXIRF7811W
L1: 2.2µH
L2: 1µH
NOTE: ELECTRICAL PATHS DRAWN WITH THICK LINES
SHOULD BE KEPT AS SHORT AND WIDE AS POSSIBLE.
THESE PATHS WILL RADIATE EMI AT THE SWITCHING
FREQUENCY. KEEP THE PATHS’ ENCLOSED AREA SMALL.
Figure 13. LTC1708 High Efficiency, Constant Frequency CPU Core/IO Power Supply with Active Voltage Positioning
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PACKAGE DESCRIPTIO
G Package
36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12
7.8 – 8.2
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
RECOMMENDED SOLDER PAD LAYOUT
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
0.05
(.002)
G36 SSOP 0802
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1708f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC1708-PG
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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High Efficiency Synchronous Step-Down Switching Regulator Controller
100% DC, Logic Level MOSFETs, VIN < 40V
LTC1430
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High Efficiency Low Noise Synchronous Step-Down Switching Regulator
Adaptive PowerTM Mode 20-Pin, 24-Pin SSOP
LTC1438/LTC1439
Dual High Efficiency Low Noise Synchronous Step-Down
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POR, Auxiliary Regulator
LTC1438-ADJ
Dual Synchronous Controller with Auxiliary Regulator
POR, External Feedback Divider
LTC1538-AUX
Dual High Efficiency Low Noise Synchronous Step-Down
Switching Regulator
Auxiliary Regulator, 5V Standby
LTC1539
Dual High Efficiency Low Noise Synchronous Step-Down
Switching Regulator
5V Standby, POR, Low-Battery, Aux Regulator
LTC1625/LTC1775
No RSENSETM Current Mode Synchronous Step-Down Controller
97% Efficiency, No Sense Resistor, 16-Pin SSOP
LTC1628
Dual Output, 2-Phase Step-Down Synchronous Current Mode Controller
Optimized Solution Cost, 3.5V ≤ VIN ≤ 36V
TM
LTC1629
20A to 200A PolyPhase Synchronous Current Mode Controller
Expandable from 2-Phase to 12-Phase, Uses All
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LTC1702
No RSENSE 2-Phase Dual Synchronous Step-Down Controller
550kHz, No Sense Resistor, VIN ≤ 7V
LTC1703
No RSENSE 2-Phase Dual Synchronous Step-Down Controller
with 5-Bit Mobile VID Control
Mobile Pentium III Processors, 550kHz, VIN ≤ 7V
LTC1709
42A High Efficiency Synchronous Current Mode Controller with
5-Bit Desktop VID Control
Server, Workstation All Surface Mount Solution
LTC1735
High Efficiency Synchronous Step-Down Synchronous Current
Mode Controller
Output Fault Protection, 16-Pin SSOP
LTC1736
High Efficiency Synchronous Current Mode Controller with
5-Bit Mobile VID Control
Output Fault Protection, 24-Pin SSOP, Power Good
3.5V ≤ VIN ≤ 36V
LTC1778/LTC1778-1 No RSENSE Current Mode Synchronous Step-Down Controller
Up to 97% Efficiency, 4V ≤ VIN ≤ 36V,
0.8V ≤ VOUT ≤ (0.9)(VIN), IOUT up to 20A
LTC1929
Single Output, 2-Phase Synchronous Current Mode Controller
Up to 42A, Uses All Surface Mount Components,
No Heat Sink
LTC1960
Dual Battery Charger/Selector with SPI Interface
Simultaneous Dual-Battery Discharge Extends Run
Time by 10%. Reduces Charging Time by up to 50%
LTC3711
No RSENSE Current Mode Synchronous Step-Down Controller
with Digital 5-Bit Interface
Up to 97% Efficiency, Ideal for Pentium III Processors,
0.925V ≤ VOUT ≤ 2V, 4V ≤ VIN ≤ 36V, IOUT up to 20A
LTC3728
Dual, 550kHz, 2-Phase Synchronous Step-Down Controller
3.5V ≤ VIN ≤ 35V, 99% Duty Cycle,
5mm × 5mm QFN, SSOP-28
LTC3729
20A to 200A, 550kHz PolyPhase Synchronous Controller
Expandable from 2-Phase to 12-Phase, Uses all
Surface Mount Components, VIN up to 36V,
QFN, SSOP-28
LTC3732
3-Phase, 5-Bit VID 600kHz Synchronous Buck up to 60A
VRM 9.0, VID, SSOP-36
Adaptive Power, No RSENSE and PolyPhase are trademarks of Linear Technology Corporation.
1708f
32
Linear Technology Corporation
LT/TP 1102 2k • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2000

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LINER LTC1708-PG_1