AD ADA4075-2ARZ

Ultralow Noise Amplifier at Lower Power
ADA4075-2
PIN CONFIGURATION
Ultralow noise: 2.8 nV/√Hz at 1 kHz typical
Ultralow distortion: 0.0002% typical
Low supply current: 1.8 mA per amplifier typical
Offset voltage: 1 mV maximum
Bandwidth: 6.5 MHz typical
Slew rate: 12 V/μs typical
Unity-gain stable
Extended industrial temperature range
SOIC package
OUTA 1
–INA 2
8
ADA4075-2
V+
OUTB
TOP VIEW
6 –INB
(Not to Scale)
5 +INB
V– 4
7
+INA 3
07642-001
FEATURES
Figure 1. 8-Lead SOIC
APPLICATIONS
Precision instrumentation
Professional audio
Active filters
Low noise amplifier front end
Integrators
GENERAL DESCRIPTION
Table 1. Low Noise Precision Op Amps
The ADA4075-2 is a dual, high performance, low noise operational
amplifier combining excellent dc and ac characteristics on the
Analog Devices, Inc., iPolar® process. The iPolar process is an
advanced bipolar technology implementing vertical junction
isolation with lateral trench isolation. This allows for low noise
performance amplifiers in smaller die size at faster speed and
lower power. Its high slew rate, low distortion, and ultralow
noise make the ADA4075-2 ideal for high fidelity audio and
high performance instrumentation applications. It is also
especially useful for lower power demands, small enclosures,
and high density applications. The ADA4075-2 is specified for
the temperature range of −40°C to +125°C and is available in a
standard SOIC package.
Supply
Single
44 V
OP27
Dual
OP275
Quad
36 V
AD8671
AD8675
AD797
AD8672
AD8676
AD8599
ADA4004-4
AD8674
12 V to 16 V
AD8665
OP162
AD8666
OP262
AD8668
OP462
5V
AD8605
AD8655
AD8691
AD8606
AD8656
AD8692
AD8608
AD8694
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADA4075-2
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications Information .............................................................. 15 Applications ....................................................................................... 1 Input Protection ......................................................................... 15 Pin Configurations ........................................................................... 1 Total Harmonic Distortion ....................................................... 15 General Description ......................................................................... 1 Phase Reversal ............................................................................ 15 Revision History ............................................................................... 2 DAC Output Filter...................................................................... 16 Specifications..................................................................................... 3 Balanced Line Driver ................................................................. 17 Absolute Maximum Ratings............................................................ 4 Balanced Line Receiver.............................................................. 18 Thermal Resistance ...................................................................... 4 Low Noise Parametric Equalizer .............................................. 19 Power Sequencing ........................................................................ 4 Schematic ......................................................................................... 20 ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 21 Typical Performance Characteristics ............................................. 5 Ordering Guide .......................................................................... 21 REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADA4075-2
SPECIFICATIONS
VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
Min
VOS
Typ
Max
Unit
0.2
1
1.2
100
150
50
75
+12.5
mV
mV
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
dB
μV/°C
MΩ
pF
pF
−40°C ≤ TA ≤ +125°C
Input Bias Current
IB
30
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large-Signal Voltage Gain
AVO
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
THD + NOISE
Total Harmonic Distortion and Noise
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
∆VOS/∆T
RIN
CINDM
CINCM
VOH
VOL
ISC
ZOUT
PSRR
ISY
5
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
VCM = −12.5 V to +12.5 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ, VO = −11 V to +11 V
−40°C ≤ TA ≤ +125°C
RL = 600 Ω, VO = −10 V to +10 V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
VSY = ±18 V, RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
VSY = ±18 V, RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
−12.5
110
106
114
108
112
106
117
117
0.3
40
2.4
2.1
12.8
12.5
12.4
12
15.4
15
13
12.8
15.8
−14
−13.6
−16.6
−13.6
−13
−13
−12.5
−16
−15.5
40
0.3
f = 100 kHz, AV = 1
VSY = ±4.5 V to ±18 V
−40°C ≤ TA ≤ +125°C
VSY = ±4.5 V to ±18 V, IO = 0 mA
−40°C ≤ TA ≤ +125°C
118
106
100
110
1.8
2.25
3.35
V
V
V
V
V
V
V
V
V
V
V
V
mA
Ω
dB
dB
mA
mA
SR
tS
GBP
ΦM
RL = 2 kΩ, AV = 1
To 0.01%, VIN = 10 V step, RL = 1 kΩ
RL = 1 MΩ, CL = 35 pF, AV = 1
RL = 1 MΩ, CL = 35 pF, AV = 1
12
3
6.5
60
V/μs
μs
MHz
Degrees
THD + N
RL = 2 kΩ, AV = 1, VIN = 3 V rms, f = 20 Hz to 20 kHz
0.0002
%
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
60
2.8
1.2
nV p-p
nV/√Hz
pA/√Hz
Rev. 0 | Page 3 of 24
ADA4075-2
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
1
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. This
was measured using a standard 2-layer board.
Rating
±20 V
±VSY
±10 mA
±1 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Table 3. Thermal Resistance
Package Type
8-Lead SOIC
θJA
158
θJC
43
Unit
°C/W
POWER SEQUENCING
The op amp supplies must be established simultaneously with,
or before, any input signals are applied. If this is not possible,
the input current must be limited to 10 mA.
The input pins have clamp diodes to the power supply pins.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 4 of 24
ADA4075-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
250
250
VSY = ±15V
VCM = 0V
200
NUMBER OF AMPLIFIERS
150
100
150
100
–0.5
0
0.5
1.0
VOS (mV)
0
–1.0
07642-003
0
–1.0
40
30
20
10
60
50
40
30
20
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
2.0
0
–2.0
07642-004
–1.6
100
100
VOS (μV)
200
0
–100
–200
–200
10
VCM (V)
15
–300
–5
07642-005
5
0
0.4
0.8
1.2
1.6
2.0
VSY = ±5V
0
–100
0
–0.4
300
200
–5
–0.8
Figure 6. Input Offset Voltage Drift Distribution
VSY = ±15V
–10
–1.2
TCVOS (μV/°C)
Figure 3. Input Offset Voltage Drift Distribution
300
–1.6
07642-007
10
TCVOS (μV/°C)
VOS (μV)
1.0
VSY = ±5V
–40°C ≤ TA ≤ +125°C
70
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
80
50
–300
–15
0.5
Figure 5. Input Offset Voltage Distribution
VSY = ±15V
–40°C ≤ TA ≤ +125°C
60
0
VOS (mV)
Figure 2. Input Offset Voltage Distribution
70
–0.5
07642-006
50
50
–4
–3
–2
–1
0
1
2
3
4
VCM (V)
Figure 4. Input Offset Voltage vs. Common-Mode Voltage
Figure 7. Input Offset Voltage vs. Common-Mode Voltage
Rev. 0 | Page 5 of 24
5
07642-008
NUMBER OF AMPLIFIERS
200
0
–2.0
VSY = ±5V
VCM = 0V
ADA4075-2
80
100
VSY = ±15V
VSY = ±5V
80
60
IB (nA)
IB (nA)
60
40
40
20
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
0
–40
40
IB (nA)
40
30
50
65
80
95
110
125
30
20
20
10
10
–5
0
5
10
15
0
–4
07642-047
IB (nA)
50
VCM (V)
10
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
1
VOL – VEE
LOAD CURRENT (mA)
100
0
1
2
3
4
VSY = ±5V
VCC – VOH
1
VOL – VEE
0.1
0.001
07642-010
10
–1
10
VCC – VOH
1
–2
Figure 12. Input Bias Current vs. Input Common-Mode Voltage
VSY = ±15V
0.1
–3
VCM (V)
Figure 9. Input Bias Current vs. Input Common-Mode Voltage
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
35
VSY = ±5V
50
0.01
20
60
VSY = ±15V
0.1
0.001
5
Figure 11. Input Bias Current vs. Temperature
60
–10
–10
TEMPERATURE (°C)
Figure 8. Input Bias Current vs. Temperature
0
–15
–25
07642-049
–10
0.01
0.1
1
10
LOAD CURRENT (mA)
Figure 10. Output Voltage to Supply Rail vs. Load Current
Figure 13. Output Voltage to Supply Rail vs. Load Current
Rev. 0 | Page 6 of 24
100
07642-013
–25
07642-009
0
–40
07642-012
20
ADA4075-2
2.0
1.5
VOL – VEE
0.5
0
–40
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
1.0
0.5
0
–40
100
100
80
80
80
60
60
60
40
40
20
20
GAIN
0
0
80
60
GAIN
40
40
20
20
0
0
–80
–100
100M
–100
1k
10k
100k
1M
–100
100M
10M
FREQUENCY (Hz)
Figure 18. Open-Loop Gain and Phase vs. Frequency
50
VSY =±15V
±15V
40
VSY =±15V±5V
AV = +100
30
AV = +10
GAIN (dB)
20
AV = +1
0
–10
–20
–20
–30
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
AV = +10
10
–10
07642-016
GAIN (dB)
120
100
PHASE
–60
10
0
140
–80
30
20
125
AV = +1
–30
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 19. Closed-Loop Gain vs. Frequency
Figure 16. Closed-Loop Gain vs. Frequency
Rev. 0 | Page 7 of 24
100M
07642-019
40
110
–80
FREQUENCY (Hz)
AV = +100
95
VSY = ±5V
Figure 15. Open-Loop Gain and Phase vs. Frequency
50
80
–40
–80
10M
65
–60
–60
1M
50
–60
–40
100k
35
–20
–40
10k
20
–40
–20
–100
1k
5
–20
–20
07642-015
GAIN (dB)
PHASE
GAIN (dB)
120
PHASE (Degrees)
140
120
100
–10
Figure 17. Output Voltage to Supply Rail vs. Temperature
140
VSY = ±15V
120
–25
TEMPERATURE (°C)
Figure 14. Output Voltage to Supply Rail vs. Temperature
140
VOL – VEE
PHASE (Degrees)
1.0
1.5
07642-014
VCC – VOH
VSY = ±5V
RL = 2kΩ
VCC – VOH
07642-018
2.0
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
VSY = ±15V
RL = 2kΩ
07642-011
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
2.5
ADA4075-2
1k
AV = +10
10
AV = +100
AV = +1
AV = +1
1
0.1
0.1
0.01
0.01
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0.001
10
100
CMRR (dB)
100
80
60
20
20
1M
10M
FREQUENCY (Hz)
0
100
1k
PSRR (dB)
PSRR–
40
60
PSRR+
20
0
0
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 22. PSRR vs. Frequency
PSRR–
40
20
07642-022
PSRR (dB)
80
1k
10M
VSY = ±5V
80
100
1M
120
100
–20
10
100k
Figure 24. CMRR vs. Frequency
100
PSRR+
10k
FREQUENCY (Hz)
VSY = ±15V
60
10M
VSY = ±5V
Figure 21. CMRR vs. Frequency
120
1M
60
40
100k
100k
80
40
07642-021
CMRR (dB)
120
10k
10k
140
120
1k
1k
Figure 23. Output Impedance vs. Frequency
VSY = ±15V
0
100
100
FREQUENCY (Hz)
Figure 20. Output Impedance vs. Frequency
140
AV = +100
07642-024
1
07642-017
ZOUT (Ω)
10
AV = +10
100
–20
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 25. PSRR vs. Frequency
Rev. 0 | Page 8 of 24
10M
100M
07642-025
100
VSY = ±5V
07642-020
VSY = ±15V
ZOUT (Ω)
1k
ADA4075-2
35
30
20
15
25
20
15
10
10
5
5
1000
CAPACITANCE (pF)
0
10
07642-023
100
100
Figure 26. Small-Signal Overshoot vs. Load Capacitance
Figure 29. Small-Signal Overshoot vs. Load Capacitance
VSY = ±5V
VIN = 7V p-p
AV = +1
RL = 2kΩ
CL = 100pF
AMPLITUDE (2V/DIV)
VOLTAGE (5V/DIV)
VSY = ±15V
VIN = 20V p-p
AV = +1
RL = 2kΩ
CL = 100pF
07642-027
0V
TIME (4µs/DIV)
Figure 30. Large-Signal Transient Response
VOLTAGE (20mV/DIV)
0V
07642-028
TIME (10µs/DIV)
0V
TIME (4µs/DIV)
Figure 27. Large-Signal Transient Response
VSY = ±15V
VIN = 100mV p-p
AV = +1
RL = 2kΩ
CL = 100pF
1000
CAPACITANCE (pF)
VSY = ±5V
VIN = 100mV p-p
AV = +1
RL = 2kΩ
CL = 100pF
TIME (10µs/DIV)
Figure 31. Small-Signal Transient Response
Figure 28. Small-Signal Transient Response
Rev. 0 | Page 9 of 24
0V
07642-026
OVERSHOOT (%)
25
VOLTAGE (20mV/DIV)
OVERSHOOT (%)
30
0
10
VSY = ±5V
AV = +1
RL = 2kΩ
07642-030
35
40
VSY = ±15V
AV = +1
RL = 2kΩ
07642-031
40
ADA4075-2
4
4
VSY = ±5V
VSY = ±15V
2
–5
OUTPUT
0
–2
–10
–4
–15
–6
–20
TIME (1µs/DIV)
INPUT VOLTAGE (V)
0
OUTPUT VOLTAGE (V)
OUTPUT
07642-029
INPUT VOLTAGE (V)
INPUT
0
Figure 35. Negative Overload Recovery
4
4
VSY = ±5V
VSY = ±15V
2
INPUT
INPUT
15
10
5
OUTPUT
–2
4
2
OUTPUT
0
0
–2
07642-033
–5
–10
TIME (1µs/DIV)
INPUT
–4
TIME (1µs/DIV)
Figure 33. Positive Overload Recovery
07642-034
–2
INPUT VOLTAGE (V)
0
OUTPUT VOLTAGE (V)
0
OUTPUT VOLTAGE (V)
2
INPUT VOLTAGE (V)
–8
TIME (1µs/DIV)
Figure 32. Negative Overload Recovery
OUTPUT VOLTAGE (V)
INPUT
0
07642-032
2
Figure 36. Positive Overload Recovery
VSY = ±5V
VSY = ±15V
OUTPUT
VOLTAGE (5V/DIV)
+10mV
+6mV
OUTPUT
0V
0V
ERROR BAND
ERROR BAND
–10mV
07642-061
TIME (2µs/DIV)
–6mV
TIME (2µs/DIV)
Figure 37. Positive Settling Time to 0.01%
Figure 34. Positive Settling Time to 0.01%
Rev. 0 | Page 10 of 24
07642-062
VOLTAGE (5V/DIV)
INPUT
ADA4075-2
VSY = ±5V
VSY = ±15V
INPUT
VOLTAGE (5V/DIV)
VOLTAGE (5V/DIV)
INPUT
+10mV
OUTPUT
+6mV
ERROR BAND
OUTPUT
0V
0V
ERROR BAND
–10mV
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 41. Negative Settling Time to 0.01%
Figure 38. Negative Settling Time to 0.01%
10
10
VSY = ±5V
100
1k
10k
100k
FREQUENCY (Hz)
1
1
10
10
CURRENT NOISE DENSITY (pA/√Hz)
RS2
UNCORRELATED
RS1 = 0
1
1
10
100
1k
FREQUENCY (Hz)
10k
100k
07642-045
CORRELATED
RS1 = RS2
0.1
10k
100k
100k
Figure 42. Voltage Noise Density
RS1
VSY = ±15V
1k
FREQUENCY (Hz)
Figure 39. Voltage Noise Density
10
100
07642-038
10
07642-035
1
07642-046
VOLTAGE NOISE DENSITY (nV/√Hz)
VSY = ±15V
VOLTAGE NOISE DENSITY (nV/√Hz)
1
CURRENT NOISE DENSITY (pA/√Hz)
07642-063
07642-064
–6mV
VSY = ±5V
RS1
RS2
UNCORRELATED
RS1 = 0
1
CORRELATED
RS1 = RS2
0.1
1
10
100
1k
FREQUENCY (Hz)
Figure 43. Current Noise Density
Figure 40. Current Noise Density
Rev. 0 | Page 11 of 24
10k
ADA4075-2
TIME (1s/DIV)
07642-039
07642-036
INPUT NOISE VOLTAGE (10nV/DIV)
VSY = ±5V
INPUT NOISE VOLTAGE (10nV/DIV)
VSY = ±15V
TIME (1s/DIV)
Figure 44. 0.1 Hz to 10 Hz Noise
Figure 47. 0.1 Hz to 10 Hz Noise
8
6
VSY = ±15V
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
5
6
+125°C
+85°C
4
+25°C
–40°C
2
4
VSY = ±5V
3
2
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±V)
0
–40
35
50
65
80
95
110
125
VSY = ±5V
VIN = 5V p-p
RL = 2kΩ
CHANNEL SEPARATION (dB)
–20
–60
–80
–100
–120
–40
–60
–80
–100
–120
1k
10k
FREQUENCY (Hz)
100k
07642-041
CHANNEL SEPARATION (dB)
20
0
–40
–140
100
5
Figure 48. Supply Current vs. Temperature
VSY = ±15V
VIN = 10V p-p
RL = 2kΩ
–20
–10
TEMPERATURE (°C)
Figure 45. Supply Current vs. Supply Voltage
0
–25
Figure 46. Channel Separation vs. Frequency
–140
100
1k
10k
FREQUENCY (Hz)
Figure 49. Channel Separation vs. Frequency
Rev. 0 | Page 12 of 24
100k
07642-044
4
07642-048
0
07642-057
1
ADA4075-2
10
VSY = ±15V
f = 1kHz
1
1
0.1
0.1
THD + NOISE (%)
THD + NOISE (%)
10
0.01
0.001
VSY = ±5V
f = 1kHz
0.01
0.001
600Ω
600Ω
0.001
0.01
0.1
1
2kΩ
10
AMPLITUDE (V rms)
07642-058
0.00001
0.0001
0.0001
2kΩ
0.00001
0.0001
0.1
1
10
Figure 53. THD + Noise vs. Amplitude
1
VSY = ±15V
VIN = 3V rms
VSY = ±5V
VIN = 1.5V rms
0.1
THD + NOISE (%)
0.1
THD + NOISE (%)
0.01
AMPLITUDE (V rms)
Figure 50. THD + Noise vs. Amplitude
1
0.001
07642-065
0.0001
0.01
0.001
0.01
600Ω
0.001
600Ω
2kΩ
100
1k
10k
100k
FREQUENCY (Hz)
0.0001
10
07642-060
0.0001
10
10k
100k
Figure 54. THD + Noise vs. Frequency
1
VSY = ±18V
f = 1kHz
1
VSY = ±18V
VIN = 8V rms
0.1
0.1
THD + NOISE (%)
THD + NOISE (%)
1k
FREQUENCY (Hz)
Figure 51. THD + Noise vs. Frequency
10
100
07642-067
2kΩ
0.01
0.001
0.01
0.001
600Ω
600Ω
0.0001
0.0001
2kΩ
0.001
0.01
0.1
1
AMPLITUDE (V rms)
10
100
Figure 52. THD + Noise vs. Amplitude
0.00001
10
100
1k
10k
FREQUENCY (Hz)
Figure 55. THD + Noise vs. Frequency
Rev. 0 | Page 13 of 24
100k
07642-059
0.00001
0.0001
07642-056
2kΩ
ADA4075-2
10
VCC – VOH
1.5
VOL – VEE
1.0
0.5
0
–40
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
125
Figure 56. Output Voltage to Supply Rail vs. Temperature
VSY = ±18V
VCC – VOH
1
0.1
0.001
VOL – VEE
0.01
0.1
1
10
LOAD CURRENT (mA)
Figure 57. Output Voltage to Supply Rail vs. Load Current
Rev. 0 | Page 14 of 24
100
07642-068
2.0
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
VSY = ±18V
RL = 2kΩ
07642-066
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
2.5
ADA4075-2
APPLICATIONS INFORMATION
1
INPUT PROTECTION
ADA4075-2
R1 2
1
07642-050
R2 3
Figure 58. Input Protection
TOTAL HARMONIC DISTORTION
THD + NOISE (%)
VSY = ±15V
RL = 2kΩ
VIN = 3V rms
0.001
0.0001
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 59. THD + Noise vs. Frequency
PHASE REVERSAL
Phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. When the voltage
driving the input to these amplifiers exceeds the maximum
input common-mode voltage range, the output of the amplifiers
changes polarity. Phase reversal can cause permanent damage to
the amplifier as well as system lockups in feedback loops.
The ADA4075-2 amplifiers have been carefully designed to prevent
output phase reversal when both inputs are maintained within
the specified input voltage range. If one or both inputs exceed
the input voltage range but remain within the supply rails, the
output is capped at the maximum output that it can swing to.
For a supply voltage of ±15 V and a load resistance of 2 kΩ, the
output is capped at 13 V typical when the input voltage exceeds
the input voltage range but stays within the supply rails. Figure 60
shows the output voltage of the AD4075-2 configured as a unitygain buffer with a supply voltage of ±15 V.
VIN
VSY = ±15V
VOUT
07642-053
The total harmonic distortion + noise (THD + N) of the
ADA4075-2 is 0.0002% typical with a load resistance of 2 kΩ.
Figure 59 shows the performance of the ADA4075-2 driving a
2 kΩ load with supply voltages of ±4 V and ±15 V. Notice that
there is more distortion for the supply voltage of ±4 V than for a
supply voltage of ±15 V. Thus, it is very important to operate the
ADA4075-2 at a supply voltage greater than ±5 V for optimum
distortion. The THD + noise graphs for supply voltages of ±5 V
and ±18 V are available in Figure 54 and Figure 55.
VSY = ±4V
RL = 2kΩ
VIN = 1.5V rms
0.01
07642-069
In small-signal applications, this is not an issue; however, in
applications where large differential voltages can be inadvertently
applied to the device, large currents may flow through these
diodes. If the differential voltage of the ADA4075-2 exceeds ±1 V,
external resistors should be used at both inputs of the op amp to
limit the input currents to less than ±10 mA (see Figure 58).
However, when series resistors are added, the total voltage noise
degrades because the resistors may have a thermal noise that is
greater than the voltage noise of the op amp itself. For example, a
1 kΩ resistor at room temperature has a thermal noise of 4 nV/√Hz,
whereas the ADA4075-2 has an ultralow voltage noise of only
2.8 nV/√Hz typical.
0.1
VOLTAGE (5V/DIV)
The maximum differential input voltage that can be applied to
the ADA4075-2 is determined by the internal diodes connected
across its inputs. These diodes limit the maximum differential
input voltage to ±1 V and are needed to prevent base-emitter
junction breakdown from occurring in the input stage of the
ADA4075-2 when very large differential voltages are applied. To
make sure that the ultralow voltage noise feature of the ADA4075-2
is preserved, the commonly used internal resistors in series with
the inputs were not used to limit the current in the diodes.
TIME (40µs/DIV)
Figure 60. No Phase Reversal
Rev. 0 | Page 15 of 24
ADA4075-2
on the output pins of the DAC. It also provides differential-tosingle-ended conversion from the differential outputs of the DAC.
DAC OUTPUT FILTER
The ultralow voltage noise, low distortion, and high slew rate of
the ADA4075-2 make it an ideal choice for professional audio
signal processing. Figure 61 shows the ADA4075-2 used in a
typical audio DAC output filter configuration. The differential
outputs of the DAC are fed into the ADA4075-2. The ADA4075-2
is configured as a differential Sallen-key filter. It operates as an
external low-pass filter to remove high frequency noise present
For a DAC output filter, an op amp with reasonable slew rate
and bandwidth is required. The slew rate of the ADA4075-2 is
at a high 12 V/μs, and the bandwidth is 6.5 MHz. The cutoff
frequency of the low-pass filter is approximately 167 kHz. In
addition, the 100 kΩ and 47 μF RC network perform ac coupling
to block out the dc components at the output.
11kΩ
68pF
5.62kΩ
1.5kΩ
1/2
100Ω
ADA4075-2
560pF
5.62kΩ
270pF
47µF
2.2nF
150pF
Figure 61. Typical DAC Output Filter Circuit (Differential)
Rev. 0 | Page 16 of 24
OUTPUT
100kΩ
07642-054
DAC OUTP
3.01kΩ
11kΩ
+
DAC OUTN
ADA4075-2
Finally, even with these precautions, it is vital that the positive
feedback be accurately controlled. This is partly achieved by
using 1% resistors. In addition, the following setup procedure
ensures that the positive feedback does not become excessive:
BALANCED LINE DRIVER
The circuit of Figure 62 shows a balanced line driver designed
for audio use. Such drivers are intended to mimic an output
transformer in operation, whereby the common-mode voltage
can be impressed by the load. Furthermore, either output can be
shorted to ground in single-ended applications without affecting
the overall operation.
1.
Set R11 to its mid position (or short the ends together,
whichever is easier), and temporarily short the negative
output to ground.
Apply a 10 V p-p sine wave at approximately 1 kHz to the
input, and adjust R7 to provide 930 mV p-p at the point
marked “test.”
Remove the short from the negative output (and across
R11, if used), and adjust R11 until the output waveforms
are symmetric.
2.
Circuits of this type use positive and negative feedback to obtain a
high common-mode output impedance, and they are somewhat
notorious for component sensitivity and susceptibility to latch-up.
This circuit uses several techniques to avoid spurious behavior.
3.
First, the 4-op-amp arrangement ensures that the input impedance
is load independent (the input impedance can become negative
with some configurations). Note that the output op amps are
packaged with the input op amps to maximize drive capability.
The overall gain of the driver is equal to 2, which provides an
extra 6 dB of headroom in balanced differential mode. The
output noise is about −109 dBV in a 20 kHz bandwidth.
Second, the positive feedback is ac-coupled by C2 and C3, which
eliminates the need for offset trim. Because the circuit is ac-coupled
at the input, these capacitors do not have significant dc voltage
across them, thus tantalum types of capacitors can be used.
C5
IN
50pF
C1
10µF
A1
R4
R5
4.7kΩ
4.7kΩ
A2
1/2
R1
10kΩ
R13
1/2
ADA4075-2
OUT+
100Ω
ADA4075-2
C4
50pF
R3
4.7kΩ
A3
R10
4.7kΩ
1/2
ADA4075-2
R8
4.7kΩ FEEDBACK
TRIM
SYMMETRY
TRIM
R12
R11
250Ω
TEST
4.7kΩ
C2
10µF
C3
10µF
4.7kΩ
C6
50pF
A4
R15
R9
100Ω 4.7kΩ
1/2
R14
100Ω
OUT–
ADA4075-2
R16
R17
100Ω
4.7kΩ
NOTES
1. ALL RESISTORS SHOULD HAVE 1% TOLERANCE.
2. A1/A2 IN SAME PACKAGE; A3/A4 IN SAME PACKAGE.
Figure 62. Balanced Line Driver
Rev. 0 | Page 17 of 24
07642-073
R6
R2
4.7kΩ
R7
250Ω
ADA4075-2
complementary output. A3 raises the common-mode input
impedance from about 7.5 kΩ to about 70 kΩ, reducing the
degradation of CMRR due to mismatches in source impedance.
It should be noted that A3 is not in the signal path, and almost any
op amp will work well here. Although it may seem as though the
inverting output should be noisier than the noninverting one,
they are in fact symmetric at about −111 dBV (20 kHz bandwidth).
BALANCED LINE RECEIVER
Figure 63 depicts a unity-gain balanced line receiver capable of
a high degree of hum rejection. The CMRR is approximately
given by
R1R4 ⎞
20 log 10 ⎛⎜
⎟
⎝ R2R3 ⎠
Therefore, R1 to R4 should be close-tolerance components to
obtain the best possible CMRR without adjustment. The presence
of A2 ensures that the impedances are symmetric at the two inputs
(unlike many other designs), and, as a bonus, A2 also provides a
Sometimes an overall gain of ½ is desired to provide an extra
6 dB of differential input headroom. This can be attained by
reducing R3 and R4 to 5 kΩ and increasing R9 to 22 kΩ.
C2
50pF
R3
OUT+
C3
10kΩ
50pF
R6
R1
IN–
IN+
R7
5.6kΩ
R2
5kΩ
A1
5kΩ
1/2
R5
A2
5kΩ
ADA4075-2
R8
5.6kΩ
5kΩ
1/2
OUT–
ADA4075-2
R4
10kΩ
A3*
R9
R10
11kΩ
11kΩ
*A3 REDUCES THE DEGRADATION OF CMRR
(SEE THE BALANCED LINE RECEIVER SECTION FOR MORE DETAILS).
Figure 63. Balanced Line Receiver
Rev. 0 | Page 18 of 24
07642-071
C1
22µF
(NON-POLAR)
ADA4075-2
48 Hz/Ct, where Ct is the value of C1 and C2 in microfarads.
The bandwidth control adjusts the Q from 0.9 to about 11. The
overall noise is setting dependent, but with all controls centered
it is about −104 dBV in a 20 kHz bandwidth. Such a low noise
level can obviate the need for a bypass switch in many applications.
LOW NOISE PARAMETRIC EQUALIZER
The circuit of Figure 64 is a reciprocal parametric equalizer
yielding ±20 dB of cut or boost with variable bandwidth and
frequency. The frequency control range is 6.9:1, with the geometric
mean center frequency conveniently occurring at the midpoint
of the potentiometer setting. The center frequency is equal to
47µF
6.2kΩ
IN
6.2kΩ
OUT
620Ω
ADA4075-2
1/2
100Ω
BOOST
CUT
BANDWIDTH
5kΩ
1kΩ
2.7kΩ
1.5kΩ
ADA4075-2
1.5kΩ
C1*
C2*
1/2
2.5kΩ
2.5kΩ
1.3kΩ
2.5kΩ
1.3kΩ
1/2
2.5kΩ
620Ω
ADA4075-2
1/2
620Ω
ADA4075-2
*THE CENTER FREQUENCY IS AFFECTED BY THE VALUE OF C1 AND C2
(SEE THE LOW NOISE PARAMETRIC EQUALIZER SECTION FOR MORE DETAILS).
Figure 64. Low Noise Parametric Equalizer
Rev. 0 | Page 19 of 24
07642-074
FREQUENCY (GANGED POTENTIOMETER)
ADA4075-2
SCHEMATIC
V+
+INA/
+INB
OUTA/
OUTB
V–
Figure 65. Simplified Schematic
Rev. 0 | Page 20 of 24
07642-072
–INA/
–INB
ADA4075-2
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 66. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADA4075-2ARZ 1
ADA4075-2ARZ-R71
ADA4075-2ARZ-RL1
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Z = RoHS Compliant Part.
Rev. 0 | Page 21 of 24
Package Option
R-8
R-8
R-8
ADA4075-2
NOTES
Rev. 0 | Page 22 of 24
ADA4075-2
NOTES
Rev. 0 | Page 23 of 24
ADA4075-2
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07642-0-10/08(0)
Rev. 0 | Page 24 of 24