100 dB Range (10 nA to 1 mA) Logarithmic Converter AD8305* FEATURES Optimized for Fiber Optic Photodiode Interfacing Measures Current over 5 Decades Law Conformance 0.1 dB from 10 nA to 1 mA Single- or Dual-Supply Operation (3 V to 12 V Total) Full Log-Ratio Capabilities Nominal Slope of 10 mV/dB (200 mV/Decade) Nominal Intercept of 1 nA (Set by External Resistor) Optional Adjustment of Slope and Intercept Complete and Temperature Stable Rapid Response Time for a Given Current Level Miniature 16-Lead Chip Scale Package (LFCSP 3 mm ⴛ 3 mm) Low Power: ~5 mA Quiescent Current APPLICATIONS Optical Power Measurement Wide Range Baseband Logarithmic Compression Measurement of Current and Voltage Ratios Optical Absorbance Measurement GENERAL DESCRIPTION The AD8305 is an inexpensive microminiature logarithmic converter optimized for determining optical power in fiber optic systems. It uses an advanced implementation of a classic translinear (junction based) technique to provide a large dynamic range in a versatile and easily used form. A single-supply voltage of between 3 V and 12 V is adequate; dual supplies may optionally be used. The low quiescent current (typically 5 mA) permits use in battery-operated applications. The input current, IPD, of 10 nA to 1 mA applied to the INPT pin is the collector current of an optimally scaled NPN transistor, which converts this current to a voltage (VBE) with a precise logarithmic relationship. A second such converter is used to handle the reference current (IREF) applied to pin IREF. These input nodes are biased slightly above ground (0.5 V). This is generally acceptable for photodiode applications where the anode does not need to be grounded. Similarly, this bias voltage is easily accounted for in generating IREF. The output of the logarithmic front end is available at Pin VLOG. The basic logarithmic slope at this output is nominally 200 mV/ decade (10 mV/dB). Thus, a 100 dB range corresponds to an output change of 1 V. When this voltage (or the buffer output) is applied to an ADC that permits an external reference voltage to be employed, the AD8305’s voltage reference output of 2.5 V at Pin VREF can be used to improve the scaling accuracy. Suitable ADCs include the AD7810 (serial 10-bit), AD7823 (serial *Protected by U.S. Patent No. 4,604,532 and 5,519,308; other patents pending. FUNCTIONAL BLOCK DIAGRAM VP 0.20 log10 VPOS ( ) VRDZ VOUT 80k⍀ VREF 200k⍀ 2.5V 20k⍀ 0.5V SCAL VBE2 VBIAS BIAS GENERATOR COMM IREF Q2 Q1 IPD – + 0.5V 14.2k⍀ TEMPERATURE COMPENSATION VBE1 INPT VSUM IPD 1nA ILOG BFIN 451⍀ VLOG 6.69k⍀ COMM VNEG COMM 8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other values of the logarithmic slope can be provided using a simple external resistor network. The logarithmic intercept (also known as the reference current) is nominally positioned at 1 nA by the use of the externally generated current, IREF, of 10 mA, provided by a 200 kW resistor connected between VREF, at 2.5 V, and the reference input IREF, at 0.5 V. The intercept can be adjusted over a wide range by varying this resistor. The AD8305 can also operate in a logratio mode, with the numerator current applied to INPT and the denominator current applied to IREF. A buffer amplifier is provided for driving a substantial load, for use in raising the basic slope of 10 mV/dB to higher values, as a precision comparator (threshold detector), or in implementing low-pass filters. Its rail-to-rail output stage can swing to within 100 mV of the positive and negative supply rails, and its peak current sourcing capacity is 25 mA. It is a fundamental aspect of translinear logarithmic converters that the small signal bandwidth falls as the current level diminishes, and the low frequency noise-spectral density increases. At the 10 nA level, the bandwidth of the AD8305 is about 50 kHz, and increases in proportion to IPD up to a maximum value of about 15 MHz. Using the buffer amplifier, the increase in noise level at low currents can be addressed by using it to realize lowpass filters of up to three poles. The AD8305 is available in a 16-lead LFCSP package and is specified for operation from –40∞C to +85∞C. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. (V = 5 V, V = 0 V, T = 25C, R AD8305–SPECIFICATIONS otherwise noted.) P N A Parameter Conditions INPUT INTERFACE Specified Current Range, IPD Input Current Min/Max Limits Reference Current, IREF, Range Summing Node Voltage Temperature Drift Input Offset Voltage Pin 4, INPT, Pin 3, IREF Flows toward INPT Pin Flows toward INPT Pin Flows toward IREF Pin Internally Preset; May be Altered by User –40∞C < TA < +85∞C VINPT – VSUM, VIREF – VSUM LOGARITHMIC OUTPUT Logarithmic Slope Pin 9, VLOG REF Min Logarithmic Intercept1 REFERENCE OUTPUT Voltage wrt Ground Maximum Output Current Incremental Output Resistance OUTPUT BUFFER Input Offset Voltage Input Bias Current Incremental Input Resistance Output Range Incremental Output Resistance Peak Source/Sink Current Small Signal Bandwidth Slew Rate POWER SUPPLY Positive Supply Voltage Quiescent Current Negative Supply Voltage (Optional) –40∞C < TA < +85∞C 10 nA < IPD < 1 mA IPD > 1 mA IPD > 1 mA Typ 10 n 10 n 0.46 0.5 0.015 –20 190 185 0.3 0.1 –40∞C < TA < +85∞C Law Conformance Error Wideband Noise2 Small Signal Bandwidth2 Maximum Output Voltage Minimum Output Voltage Output Resistance = 200 k, and VRDZ connected to VREF, unless Limited by VN = 0 V 4.375 Max Unit 1m 10 m 1m 0.54 A A A V mV/∞C mV +20 200 1 0.1 0.7 0.7 1.7 0.01 5 210 215 1.7 2.5 0.4 5.625 mV/dec mV/dec nA nA dB mV÷Hz MHz V V kW Pin 2, VREF –40∞C < TA < +85∞C Sourcing (Grounded Load) Load Current < 10 mA 2.435 2.4 2.5 2.565 2.6 V V mA W +20 mV mA MW V W mA MHz V/ms 12 6.5 V mA V 20 2 Pin 10, BFIN; Pin 11, SCAL; Pin 12, VOUT –20 Flowing out of Pin 10 or 11 0.4 35 VP – 0.1 0.5 25 15 15 RL = 1 kW to ground Load Current < 10 mA GAIN = 1 0.2 V to 4.8 V Output Swing Pin 8, VPOS; Pin 6 and Pin 7, VNEG (VP – VN) £ 12 V 3 (VP – VN) £ 12 V –5.5 5 5.4 0 NOTES 1 Other values of logarithmic intercept can be achieved by adjusting R REF. 2 Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN = 1. –2– REV. A AD8305 ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Supply Voltage VP – VN . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 500 mW JA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30∞C/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C Operating Temperature Range . . . . . . . . . . . . –40∞C to +85∞C Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C Model Temperature Range AD8305ACP –40∞C to +85∞C AD8305ACP-REEL7 7" Tape and Reel AD8305-EVAL Evaluation Board Package Description Package Option 16-Lead LFCSP CP-16 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 With package die paddle soldered to thermal pad containing nine vias connected to inner and bottom layers. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8305 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN 1 INDICATOR VRDZ 1 12 VOUT 11 SCAL 10 BFIN 9 VLOG VPOS 8 TOP VIEW VSUM 5 INPT 4 AD8305 VNEG 6 VNEG 7 VREF 2 IREF 3 15 COMM 14 COMM 13 COMM 16 COMM PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 VRDZ Top of a Resistive Divider Network that Offsets VLOG to Position the Intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be provided. 2 VREF Reference Output Voltage of 2.5 V. 3 IREF Accepts (Sinks) Reference Current, IREF. 4 INPT Accepts (Sinks) Photodiode Current, IPD. Usually connected to photodiode anode such that photo current flows into INPT. 5 VSUM Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential. 6, 7 VNEG Optional Negative Supply, VN. (This pin is usually grounded; for details of usage, see the Applications section). 8 VPOS Positive Supply, (VP – VN ) £ 12 V. 9 VLOG Output of the Logarithmic Front End. 10 BFIN Buffer Amplifier Noninverting Input. 11 SCAL Buffer Amplifier Inverting Input. 12 VOUT Buffer Output. 13–16 COMM Analog Ground. REV. A –3– (VP = 5 V, V N = 0 V, R REF = 200 k, T A = 25C, unless otherwise noted.) AD8305–Typical Performance Characteristics 1.6 1.4 2.0 TA = –40C, 0C, +25C, +70C, +85C VN = 0V VLOG – V ERROR – dB(10mV/dB) 1.2 –40C +25C +85C 1.0 0.8 0.6 0C +70C 0.4 1.0 +85C +70C 0.5 0 –0.5 10n 100n 1 10 IPD – A 100 1m –2.0 1n 10m 1.6 ERROR – dB(10mV/dB) 0C +70C 1.2 VLOG – V 1 10 IPD – A 100 1m 10m 1.0 +25C +85C 0.8 TA = –40C, 0C, +25C, +70C, +85C VN = 0V 1.5 1.4 0.6 1.0 +70C 0 –0.5 +25C 0C –1.5 0.2 10n 100n 1 10 IREF – A 100 1m –2.0 1n 10m 0.5 1.6 0.4 1.4 0.3 ERROR – dB(10mV/dB) 1.8 1.2 10nA 100nA 1A 0.6 –40C 10n 100n 1 10 IREF – A 10A 1m 10m 10A 100A 1mA 0.2 0.1 0 –0.1 1A –0.2 100A 0.4 100 TPC 5. Law Conformance Error vs. IREF (at IPD = 10 m A) for Multiple Temperatures, Normalized to 25∞C TPC 2. VLOG vs. IREF for Multiple Temperatures 0.8 +85C 0.5 –1.0 0.4 VLOG – V 100n 2.0 TA = –40C, 0C, +25C, +70C, +85C VN = 0V –40C 10nA 100nA 100 1m –0.3 1mA 0.2 0 1n 10n TPC 4. Law Conformance Error vs. IPD (at IREF = 10 m A) for Multiple Temperatures, Normalized to 25∞C 1.8 1.0 +25C –1.5 TPC 1. VLOG vs. IPD for Multiple Temperatures 0 1n 0C –40C –1.0 0.2 0 1n TA = –40C, 0C, +25C, +70C, +85C VN = 0V 1.5 –0.4 10n 100n 1 10 IPD – A 100 1m –0.5 1n 10m TPC 3. VLOG vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA) 10n 100n 1 10 IPD – A 10m TPC 6. Law Conformance Error vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA) –4– REV. A AD8305 1.8 0.5 1.6 0.4 10nA ERROR – dB(10mV/dB) VLOG – V 1A 10A 1.2 1.0 1mA 100A 10A 1A 0.8 0.6 100nA 10nA 0.4 0.2 0.1 0 –0.1 –0.2 100A 1mA –0.3 0.2 0 1n 100nA 0.3 1.4 –0.4 10n 100n 1 10 IREF – A 100 1m –0.5 1n 10m TPC 7. VLOG vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA) 10n 100n 1 10 IREF – A 100 1m 10m TPC 10. Law Conformance Error vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA) 0.5 1.4 +3V, 0V 0.4 +5V, 0V 1.2 +12V, 0V 100A TO 1mA: T-RISE = <1s, T-FALL = < 1s 0.3 1.0 0.2 10A TO 10A: T-RISE = <1s, T-FALL = < 1s 0.1 VOUT – V ERROR – dB(10mV/dB) +9V, 0V 0 –0.1 0.8 1A TO 10A: T-RISE = 1s, T-FALL = 5s 0.6 100nA TO 1A: T-RISE = 5s, T-FALL = 20s +3V, –0.5V –0.2 0.4 +5V, –5V 10nA TO 100nA: T-RISE = 20s, T-FALL = 30s –0.3 0.2 –0.4 –0.5 1n 10n 100n 1 10 IPD – A 100 1m 0 –20 10m 0.3 1.4 0.2 1.2 0.1 1.0 VOUT – V VSUM – V INPT – mV 1.6 0 –0.2 0.4 –0.3 0.2 100 1m 0 –20 10m 100 120 140 160 180 100nA TO 1A: T-RISE = 30s, T-FALL = 5s 1A TO 10A: T-RISE = 5s, T-FALL = < 1s 100A TO 1mA: T-RISE = < 1s, T-FALL = < 1s 0 20 40 60 80 100 TIME – s 120 140 160 180 TPC 12. Pulse Response – IREF to VOUT (G = 1) TPC 9. VINPT – VSUM vs. IPD REV. A 80 10A TO 100A: T-RISE = 1s, T-FALL = < 1s 0.6 1 10 IPD – A 60 10nA TO 100nA: T-RISE = 30s, T-FALL = 20s 0.8 –0.1 100n 40 TPC 11. Pulse Response – IPD to VOUT (G = 1) 0.4 10n 20 TIME – s TPC 8. Law Conformance Error vs. IPD for Various Supply Conditions (see Annotations) –0.4 1n 0 –5– AD8305 10 10nA 3 100nA 10A NORMALIZED RESPONSE – dB 0 100A VOUT –10 –20 1mA –30 1A –40 –50 100 1k 10k 100k 1M FREQUENCY – Hz 10M AV = 1 –3 AV = 2 AV = 5 –6 AV = 2.5 –9 –12 10k 100M TPC 13. Small Signal AC Response (5% Sine Modulation), from IPD to VOUT (G = 1) for IPD in Decade Steps from 10 nA to 1 mA, IREF = 10 m A 100k 1M FREQUENCY – Hz 10M 100M TPC 16. Small Signal AC Response of the Buffer for Various Closed-Loop Gains (RL = 1 k W CL < 2 pF) 10 2.0 10nA 100nA 10A 1.5 0 100A 1.0 MEAN + 3 –10 VOS DRIFT – mV NORMALIZED RESPONSE – dB 0 –20 1mA –30 0.5 0 –0.5 MEAN – 3 1A –1.0 –40 –1.5 –50 100 1k 10k 100k 1M FREQUENCY – Hz 10M –2.0 –40 –30 –20 –10 100M 0 10 20 30 40 50 60 70 80 90 TEMPERATURE – C TPC 14. Small Signal AC Response (5% Sine Modulation), from IREF to VOUT (G = 1) for IREF in Decade Steps from 10 nA to 1 mA, IPD = 10 m A TPC 17. Buffer Input Offset Drift vs. Temperature (3 to Either Side of Mean) 100 6 10nA 5 10 4 mVrms Vrms/ Hz 100nA 1 1A 3 10A 2 0.1 100A 0.01 100 1k 10k 100k FREQUENCY – Hz 1 1M 0 10n 10M TPC 15. Spot Noise Spectral Density at VOUT (G = 1) vs. Frequency for IPD in Decade Steps from 10 nA to 1 mA 100n 1 10 IPD – A 100 1m 10m TPC 18. Total Wideband Noise Voltage at VOUT vs. IPD (G = 1) –6– REV. A AD8305 20 2.0 TA = 25C 15 10 1.0 0.5 VREF DRIFT – mV ERROR – dB(10mV/dB) 1.5 MEAN + 3 0 MEAN – 3 –0.5 –1.0 0 –5 –10 MEAN – 3 –15 –1.5 –2.0 1n MEAN + 3 5 –20 10n 100n 1 10 IPD – A 100 1m –25 –40 –30 –20 –10 10m 0 10 20 30 40 50 60 70 80 90 TEMPERATURE – C TPC 22. VREF Drift vs. Temperature (3 to Either Side of Mean) TPC 19. Law Conformance Error Distribution (3 to Either Side of Mean) 20 2.0 TA = 0C, 70C 15 MEAN + 3 @ 70C 1.0 10 0.5 5 DRIFT – mV ERROR – dB(10mV/dB) 1.5 0 MEAN 3 @ 0C –0.5 MEAN + 3 0 –5 MEAN – 3 –10 –1.0 MEAN – 3 @ 70C –1.5 –2.0 –15 1n 10n 100n 1 10 IPD – A 100 1m –20 –40 –30 –20 –10 10m 0 10 20 30 40 50 60 70 80 90 TEMPERATURE – C TPC 20. Law Conformance Error Distribution (3 to Either Side of Mean) TPC 23. VREF – VIREF Drift vs. Temperature (3 to Either Side of Mean) 4 5 TA = –40C, +85C 4 3 3 2 2 VINPT DRIFT – mV ERROR – dB(10mV/dB) MEAN + 3 @ –40C 1 MEAN 3 @ +85C 0 –1 1 MEAN + 3 0 –1 –2 MEAN – 3 –2 –3 –3 –4 1n MEAN – 3 @ –40C 10n 100n 1 10 IPD – A –4 100 1m –5 –40 –30 –20 –10 10m 10 20 30 40 50 60 70 80 90 TEMPERATURE – C TPC 24. VINPT Drift vs. Temperature (3 to Either Side of Mean) TPC 21. Law Conformance Error Distribution (3 to Either Side of Mean) REV. A 0 –7– AD8305 10 4000 8 3500 6 MEAN + 3 2500 2 COUNT Vy DRIFT – mV/dec 3000 4 0 –2 2000 1500 MEAN – 3 –4 1000 –6 500 –8 –10 –40 –30 –20 –10 0 10 20 30 40 50 TEMPERATURE – C 60 70 80 0 0.4 90 TPC 25. Slope Drift vs. Temperature (3 to Either Side of Mean of 200 mV/decade) 0.6 0.8 1.0 1.2 INTERCEPT – nA 1.4 1.6 TPC 28. Distribution of Logarithmic Intercept (Nominally 1 nA when RREF = 200 kW ± 0.1%) Sample >22,000 350 7000 6000 250 150 5000 50 4000 COUNT Iz DRIFT – pA MEAN + 3 –50 3000 2000 –150 MEAN – 3 1000 –250 –350 –40 –30 –20 –10 0 10 20 30 40 50 TEMPERATURE – C 60 0 2.44 70 80 85 90 6000 5000 5000 4000 4000 COUNT COUNT 6000 3000 2000 1000 1000 200 SLOPE – mV/dec 205 2.50 VREF – V 2.52 2.54 2.56 3000 2000 195 2.48 TPC 29. Distribution of VREF (RL = 100 kW) Sample >22,000 TPC 26. Intercept Drift vs. Temperature (3 to Either Side of Mean of 1 nA) 0 190 2.46 0 –0.015 210 –0.010 –0.005 0.0 0.005 VINPT – VSUM VOLTAGE – V 0.010 0.015 TPC 30. Distribution of Offset Voltage (VINPT – VSUM) Sample >22,000 TPC 27. Distribution of Logarithmic Slope (Nominally 200 mV/decade) Sample >22,000 –8– REV. A AD8305 billion between –35∞C and +85∞C. Thus, to make use of the BJT as an accurate logarithmic element, both of these temperature dependencies must be eliminated. GENERAL STRUCTURE The AD8305 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and will also be useful in many nonoptical applications. These notes explain the structure of this unique style of translinear log amp. Figure 1 is a simplified schematic showing the key elements. BIAS GENERATOR PHOTODIODE 2.5V INPUT CURRENT 80k IPD 0.5V VBE1 IREF VREF IREF VBE2 20k The difference between the base-emitter voltages of a matched pair of BJTs, one operating at the photodiode current IPD and the second operating at a reference current IREF, can be written as: VBE1 – VBE2 = kT /q In(IC /IS ) – kT /q In(IREF /IS ) = In (10) kT /q log10 (IPD /IREF ) = 59.5 mV log10 (IPD /IREF ) (T = 300 K ) TEMPERATURE COMPENSATION (SUBTRACT AND DIVIDE BY T K The uncertain and temperature dependent saturation current IS, which appears in Equation 1, has thus been eliminated. To eliminate the temperature variation of kT/q, this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under Equation 2. The output of this process, which also involves a conversion from voltage-mode to currentmode, is an intermediate, temperature-corrected current: COMM VSUM 0.5V 44A/dec INPT 14.2k VRDZ 451 VLOG 0.5V Q1 VBE1 Q2 VBE2 6.69k ILOG = IY log10 (IPD /IREF ) COMM VNEG (NORMALLY GROUNDED) Figure 1. Simplified Schematic It is apparent that this output should be zero for IPD = IREF, and would need to swing negative for smaller values of input current. To avoid this, IREF would need to be as small as the smallest value of IPD. However, it is impractical to use such a small reference current as 1 nA. Accordingly, an offset voltage is added to VLOG to shift it upward by 0.8 V when Pin VRDZ is directly connected to VREF. This has the effect of moving the intercept to the left by four decades, from 10 mA to 1 nA: ILOG = IY log10 (IPD /IINTC ) The AD8305 also supports the use of an optional negative supply voltage, VN, at Pin VNEG. When VN is –0.5 V or more negative, VSUM may be connected to ground; thus INPT and IREF assume this potential. This allows operation as a voltage-input logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting IREF will need to be adjusted to maintain the intercept value. It should also be noted that the collector-emitter voltages of Q1 and Q2 are now the full VN, and effects due to self-heating will cause errors at large input currents. (4) where IINTC is the operational value of the intercept current. To disable this offset, Pin VRDZ should be grounded, then the intercept IINTC is simply IREF. Since values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is required to accommodate this situation (discussed later). The voltage VLOG is generated by applying ILOG to an internal resistance of 4.55 kW, formed by the parallel combination of a 6.69 kW resistor to ground and the 14.2 kW resistor to the VRDZ pin. When the VLOG pin is unloaded and the intercept repositioning is disabled by grounding VRDZ, the output current ILOG generates a voltage at the VLOG pin of: VLOG = I LOG ¥ 4.55 k W The input dependent VBE1 of Q1 is compared with the reference VBE2 of a second transistor, Q2, operating at IREF. This is generated externally, to a recommended value of 10 mA. However, other values over a several-decade range can be used with a slight degradation in law conformance (TPC 1). = 44 mA ¥ 4.55 k W ¥ log10 ( I PD /I REF ) Theory = VY log10 ( I PD /I REF ) The base-emitter voltage of a BJT (bipolar junction transistor) can be expressed by Equation 1, which immediately shows its basic logarithmic nature: (5) where VY = 200 mV/decade, or 10 mV/dB. Note that any resistive loading on VLOG will lower this slope and also result in an overall scaling uncertainty due to the variability of the on-chip resistors. Consequently, this practice is not recommended. (1) where IC is its collector current, IS is a scaling current, typically only 10–17 A, and kT/q is the thermal voltage, proportional to absolute temperature (PTAT) and is 25.85 mV at 300 K. The current, IS, is never precisely defined and exhibits an even stronger temperature dependence, varying by a factor of roughly a REV. A (3) where IY is an accurate, temperature-stable scaling current that determines the slope of the function (the change in current per decade). For the AD8305, IY is 44 mA, resulting in a temperatureindependent slope of 44 mA/decade, for all values of IPD and IREF. This current is subsequently converted back to a voltage-mode output, VLOG, scaled 200 mV/decade. The photodiode current I PD is received at Pin INPT. The voltage at this node is essentially equal to those on the two adjacent guard pins, VSUM and IREF, due to the low offset voltage of the JFET op amp. Transistor Q1 converts the input current IPD to a corresponding logarithmic voltage, as shown in Equation 1. A finite positive value of V SUM is needed to bias the collector of Q1 for the usual case of a single-supply voltage. This is internally set to 0.5 V, that is, one fifth of the reference voltage of 2.5 V appearing on Pin VREF. The resistance at the VSUM pin is nominally 16 kW; this voltage is not intended as a general bias source. VBE = kT /qIn(I C /I S ) (2) VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = –0.5 V or larger, the input pins INPT and IREF may now be positioned at ground level by simply grounding VSUM. –9– AD8305 Managing Intercept and Slope +5V When using a single supply, VRDZ should be directly connected to VREF to allow operation over the entire five-decade input current range. As noted previously, this introduces an accurate offset voltage of 0.8 V at the VLOG pin, equivalent to four decades, resulting in a logarithmic transfer function that can be written as: ( VLOG = VY log10 10 ¥ I PD /I REF 4 = VY log10 ( I PD /I INTC ) ) VRDZ VREF 200k 20k 0.5V (6) VBIAS 80k 2.5V The AD8305 buffer is essentially an uncommitted op amp with rail-to-rail output swing, good load-driving capabilities and a unity-gain bandwidth of >12 MHz. In addition to allowing the introduction of gain, using standard feedback networks and thereby increasing the slope voltage VY, the buffer can be used to implement multipole low-pass filters, threshold detectors, and a variety of other functions. Further details of these can be found in the AD8304 data sheet. Response Time and Noise Considerations The response time and output noise of the AD8305 are fundamentally a function of the signal current IPD. For small currents, the bandwidth is proportional to IPD, as shown in TPC 13. The output low frequency voltage-noise spectral-density is a function of IPD (TPC 15) and also increases for small values of IREF. Details of the noise and bandwidth performance of translinear log amps can be found in the AD8304 Data Sheet. – + 14.2k TEMPERATURE COMPENSATION VBE1 ILOG BFIN 451 VLOG CFLT 10nF 6.69k COMM 0.5V 1nF The slope can be reduced by attaching a resistor to the VLOG pin. This is strongly discouraged, in view of the fact that the on-chip resistors will not ratio correctly to the added resistance. Also, it is rare that one would want to lower the basic slope of 10 mV/dB; if this is needed, it should be effected at the low impedance output of the buffer, which is provided to avoid such miscalibration and also allow higher slopes to be used. The AD8305 is easy to use in optical supervisory systems and in similar situations where a wide ranging current is to be converted to its logarithmic equivalent, which is represented in decibel terms. Basic connections for measuring a single-current input are shown in Figure 2, which also includes various nonessential components, as will be explained. Q2 VSUM 1nF 12k 8k VBE2 1k 1nF BIAS GENERATOR SCAL Q1 1k IPD 1nA COMM IPD INPT where IINTC = IREF /104 Thus, the effective intercept current I INTC is only one tenthousandth of IREF, corresponding to 1 nA when using the recommended value of IREF = 10 mA. ( ) VOUT IREF APPLICATIONS 0.5 log10 VPOS VNEG COMM Figure 2. Basic Connections for Fixed Intercept Use The 2 V difference in voltage between the VREF and INPT pins in conjunction with the external 200 kW resistor RREF provide a reference current IREF of 10 mA into Pin IREF. Connecting pin VRDZ to VREF raises the voltage at VLOG by 0.8 V, effectively lowering the intercept current IINTC by a factor of 104 to position it at 1 nA. A wide range of other values for IREF, from under 100 nA to over 1 mA, may be used. The effect of such changes is shown in TPC 3. Any temperature variation in RREF must be taken into account when estimating the stability of the intercept. Also, the overall noise will increase when using very low values of IREF. In fixedintercept applications, there is little benefit in using a large reference current, since this only compresses the low current end of the dynamic range when operated from a single supply, here shown as 5 V. The capacitor between VSUM and ground is recommended to minimize the noise on this node and to help provide a clean reference current. Since the basic scaling at VLOG is 0.2 V/decade, and thus a swing of 4 V at the buffer output would correspond to 20 decades, it will often be useful to raise the slope to make better use of the railto-rail voltage range. For illustrative purposes, the circuit in Figure 2 provides an overall slope of 0.5 V/decade (25 mV/dB). Thus, using IREF = 10 mA, VLOG runs from 0.2 V at IPD = 10 nA to 1.4 V at IPD = 1 mA while the buffer output runs from 0.5 V to 3.5 V, corresponding to a dynamic range of 120 dB (electrical, that is, 60 dB optical power). The optional capacitor from VLOG to ground forms a single-pole low-pass filter in combination with the 4.55 kW resistance at this pin. For example, using a CFLT of 10 nF, the –3 dB corner frequency is 3.5 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multipole filters are more effective in reducing the total noise; examples are provided in the AD8304 data sheet. –10– REV. A AD8305 The dynamic response of this overall input system is influenced by the external RC networks connected from the two inputs (INPT, IREF) to ground. These are required to stabilize the input systems over the full current range. The bandwidth changes with the input current due to the widely varying pole frequency. The RC network adds a zero to the input system to ensure stability over the full range of input current levels. The network values shown in Figure 2 will usually suffice, but some experimentation may be necessary when the photodiode capacitance is high. The Uncalibrated Error line in Figure 3 was generated assuming that the slope of the measured output was 200 mV/decade when in fact it was actually 194 mV/decade. Correcting for this discrepancy decreased measurement error up to 3 dB. USING A NEGATIVE SUPPLY Most applications of the AD8305 require only a single supply of 3.0 V to 5.5 V. However, to provide further versatility, dual supplies may be employed, as illustrated in Figure 4. Although the two current inputs are similar, some care is needed to operate the reference input at extremes of current (<100 nA) and temperature (<0∞C). Modifying the RC network to 4.7 nF and 2 kW will allow operation to –40∞C at 10 nA. By inspecting the transient response to perturbations in IREF at representative current levels, the capacitor value can be adjusted to provide fast rise and fall times with acceptable settling. To fine tune the network zero, the resistor value should be adjusted. 5V VPOS VRDZ VREF RREF 200k 20k 0.5V CALIBRATION VBIAS The AD8305 has a nominal slope and intercept of 200 mV/decade and 1 nA, respectively. These values are untrimmed and the slope alone may vary as much as 7.5% over temperature. For this reason, it is recommended that a simple calibration be done to achieve increased accuracy. 80k 2.5V UNCALIBRATED ERROR 1.2 3 1.0 2 Q2 Q1 8k SCAL 14.2k – TEMPERATURE + COMPENSATION VBE1 VSUM 451 VLOG CFLT 10nF 6.69k VNEG Iq + ISIG ISIG = IPD + IREF RS BFIN ILOG COMM 0.5V + VF – 1nA 12k COMM IPD INPT 4 BIAS GENERATOR VBE2 1k 1nF 1k 1nF IPD ( ) VOUT IREF 1.4 0.5 log10 COMM VNEG £ –0.5V C1 RS £ VN – V F Iq + ISIGMAX VLOG – V MEASURED OUTPUT 1 0.8 0 0.6 CALIBRATED ERROR –1 0.4 ERROR – dB(10mV/dB) VN Figure 4. Negative Supply Application The use of a negative supply, VN, allows the summing node to be placed at ground level whenever the input transistor (Q1 in Figure 1) has a sufficiently negative bias on its emitter. When VNEG = –0.5 V, the VCE of Q1 and Q2 will be the same as for the default case when VSUM is grounded. This bias need not be accurate, and a poorly defined source can be used. The source does however need to be able to support the quiescent current as well as the INPT and IREF signal current. For example, it may be convenient to utilize a forward-biased junction voltage of about 0.7 V or a Schottky barrier voltage of a little over 0.5 V. The effect of supply on the dynamic range and accuracy can be seen in TPC 8. IDEAL OUTPUT –2 0.2 0 1n 10n 100n 1 10 IPD – A 100 1m –3 10m Figure 3. Using Two-Point Calibration to Increase Measurement Accuracy Figure 3 shows the improvement in accuracy when using a twopoint calibration method. To perform this calibration, apply two known currents, I1 and I2, in the linear operating range between 10 nA and 1 mA. Measure the resulting output, V1 and V2, respectively, and calculate the slope m and intercept b. [ m = (V1 – V2 ) / log10 ( I1 ) – log10 ( I 2 ) b = V1 – m ¥ log10 ( I1 ) ] (7) (8) The same calibration could be performed with two known optical powers, P1 and P2. This allows for calibration of the entire measurement system while providing a simplified relationship between the incident optical power and VLOG voltage. m = (V1 – V2 ) / (P1 – P2 ) b = V1 – m ¥ P1 REV. A (9) With the summing node at ground, the AD8305 may now be used as a voltage-input log amp at either the numerator input, INPT, or the denominator input, IREF, by inserting a suitably scaled resistor from the voltage source to the relevant pin. The overall accuracy for small input voltages is limited by the voltage offset at the inputs of the JFET op amps. The use of a negative supply also allows the output to swing below ground, thereby allowing the intercept to correspond to a midrange value of IPD. However, the voltage VLOG remains referenced to the ACOM pin, and while it does not swing negative for default operating conditions, it is free to do so. Thus, adding a resistor from VLOG to the negative supply lowers all values of VLOG, which raises the intercept. The disadvantage of this method is that the slope is reduced by the shunting of the external resistor, and the poorly defined ratio of onchip and off-chip resistances causes errors in both the slope and the intercept. (10) –11– AD8305 +5V VPOS VRDZ VOUT PREF REFERENCE DETECTOR BIAS 2.5 V GENERATOR 20k 0.5V 1k SCAL VBE2 Q2 Q1 PSIG INPT 1k VSUM 1nF IREF +2 18nF – + 33nF 14.2k BFIN ILOG 451 TEMPERATURE COMPENSATION VLOG VBE1 SIGNAL DETECTOR IPD ( ) 28.0k IREF 1nF IPD 44.2k COMM IREF +5V 0.5 log10 80k VREF 12.1k 6.69k COMM 0.5V VNEG COMM Figure 5. Optical Absorbance Measurement It is often desirable to determine the ratio of two currents, for example, in absorbance measurements. These are commonly used to assess the attenuation of a passive optical component, such as an optical filter or variable optical attenuator. In these situations, a reference detector is used to measure the incident power entering the component. The exiting power is then measured using a second detector and the ratio is calculated to determine the attenuation factor. Since the AD8305 is fundamentally a ratiometric device, having nearly identical logging systems for both numerator and denominator (IPD and IREF, respectively), it can greatly simplify such measurements. Figure 5 illustrates the AD8305’s log-ratio capabilities in optical absorbance measurements. Here a reference detector diode is used to provide the reference current, IREF, proportional to the optical reference power level. A second detector measures the transmitted signal power, proportional to IPD. The AD8305 calculates the logarithm of the ratio of these two currents, as shown in Equation 11, and which is reformulated in power terms in Equation 12. Both of these equations include the internal factor of 10,000 introduced by the output offset applied to VLOG via pin VRDZ. If the true (nonoffset) log ratio shown in Equation 4 is preferred, VRDZ should be grounded to remove the offset. As already noted, the use of a negative supply at Pin VNEG will allow both VLOG and the buffer output to swing below ground, and also allow the input pins INPT and IREF to be set to ground potential. Thus, the AD8305 may also be used to determine the log ratio of two voltages. exactly to the external resistor, which may slightly alter the Q of the filter, the effect on pulse response will be negligible for most purposes. Note that the gain of the buffer (⫻2.5) is an integral part of this illustrative filter design; in general, the filter may be redesigned for other closed-loop gains. The transfer characteristics can be expressed in terms of optical power. If we assume that the two detectors have equal responsivities, the relationship is ( VOUT = 0.5V log10 10 4 ¥ PSIG /PREF ) (11) Using the identity log10(AB) = log10A + log10B and defining the attenuation as –10 ⫻ log10(PSIG / PREF), the overall transfer characteristic can be written as VOUT = 2 – 50 mV dB ¥ a (12) where a = –10 ¥ log10 (PSIG PREF ) Figure 6 illustrates the linear-in-dB relationship between the absorbance and the output of the circuit in Figure 5. Figure 5 also illustrates how a second order Sallen-Key low-pass filter can be realized using two external capacitors and one resistor. Here, the corner frequency is set to 1 kHz and the filter Q is chosen to provide an optimally flat (overshoot-free) pulse response. To scale this frequency either up or down, simply scale the capacitors by the appropriate factor. Note that one of the resistors needed to realize this filter is the output resistance of 4.55 kW present at Pin VLOG. While this will not ratio –12– 2.5 2.0 1.5 VLOG – V LOG-RATIO APPLICATIONS 1.0 0.5 0 0 5 10 15 20 25 30 35 ATTENUATION – dB 40 45 50 Figure 6. Example of an Absorbance Transfer Function REV. A AD8305 REVERSING THE INPUT POLARITY These measures are needed to minimize the risk of leakage current paths. With 0.5 V as the nominal bias on the INPT pin, a leakage-path resistance of 1 GW to ground would subtract 0.5 nA from the input, which amounts to an error of –0.44 dB for a source current of 10 nA. Additionally, the very high output resistance at the input pins and the long cables commonly needed during characterization allow 60 Hz and RF emissions to introduce substantial measurement errors. Careful guarding techniques are essential to reduce the pickup of these spurious signals. Some applications may require interfacing to a circuit that sources current rather than sinks current, such as connecting to the cathode side of a photodiode. Figure 7 shows the use of a current mirror circuit. This allows for simultaneous monitoring of the optical power at the cathode, and a data recovery path using a transimpedance amplifier at the anode. The modified Wilson mirror provides a current gain very close to unity and a high output resistance. Figure 8 shows measured transfer function and law conformance performance of the AD8305 in conjunction with this current mirror interface. VREF KEITHLEY 236 IREF 5V 16 15 14 13 1 VRDZ 2 VREF 2.5V MAT03 200k VSUM VOUT 12 SCAL 11 TRIAX CONNECTORS (SIGNAL – INPT AND IREF GUARD – VSUM SHIELD – GROUND) AD8305 0V 3 IREF BFIN 10 4 INPT VLOG 9 1nF 0V IPD 1k IIN⬇I PD 10nA TO 1mA 5 6 7 8 0.1F 5V DATA PATH TIA Figure 7. Wilson Current Mirror for Cathode Interfacing 1.00 1.4 0.75 1.2 0.50 VLOG – V 1.0 0.25 +5V 0 0.8 +3V –0.25 0.6 5V –0.50 0.4 HP 3577A NETWORK ANALYZER ERROR – dB(10mV/dB) 1.6 OUTPUT –0.75 10n INPUT A 16 BNC-T INPUT B 15 14 13 COMM COMM COMM COMM 5V 0 1n INPUT R +IN AD8138 B EVALUATION BOARD A +3V +5V 0.2 DC MATRIX/DC SUPPLIES/DMM Figure 9. Primary Characterization Setup The primary characterization setup shown in Figure 9 is used to measure VREF, the static (dc) performance, logarithmic conformance, slope and intercept, the voltages appearing at pins VSUM, INPT and IREF, and the buffer offset and VREF drift with temperature. To ensure stable operation over the full current range of IREF and temperature extremes, filter components of C1 = 4.7 nF and R13 = 2 kW are used at pin to IREF ground. In some cases, a fixed resistor between pins VREF and IREF was used in place of a precision current source. For the dynamic tests, including noise and bandwidth measurements, more specialized setups are required. VSUM VNEG VNEG VPOS 1nF BFIN VLOG INPT OUTPUT MAT03 VOUT CHARACTERIZATION BOARD KEITHLEY 236 COMM COMM COMM COMM VPOS AD8305 VOUT = 0.2 log10 (I PD/1nA) 0.1F VNEG 100n 1 10 100 1m AD8138 PROVIDES DC OFFSET –1.00 10m 1 VRDZ 2 VREF VOUT 12 IPD – A Figure 8. Log Output and Error Using Current Mirror with Various Supplies CHARACTERIZATION METHODS During the characterization of the AD8305, the device was treated as a precision current-input logarithmic converter, since it is not practical for several reasons to generate accurate photocurrents by illuminating a photodiode. The test currents were generated either by using well calibrated current sources, such as the Keithley 236, or by using a high value resistor from a voltage source to the input pin. Great care is needed when using very small input currents. For example, the triax output connection from the current generator was used with the guard tied to VSUM. The input trace on the PC board was guarded by connecting adjacent traces to VSUM. REV. A SCAL 11 AD8305 3 IREF BFIN 10 4 INPT VLOG 9 VSUM VNEG VNEG VPOS 5 6 7 8 +VS 0.1F Figure 10. Configuration for Buffer Amplifier Bandwidth Measurement Figure 10 shows the configuration used to measure the buffer amplifier bandwidth. The AD8138 evaluation board includes –13– AD8305 provisions to offset VLOG at the buffer input, allowing measurements over the full range of IPD using a single supply. The network analyzer input impedances were set to 1 MW. HP 3577A NETWORK ANALYZER OUTPUT INPUT R INPUT A INPUT B The configuration in Figure 12 is used to measure the noise performance. Batteries provide both the supply voltage and the input current in order to minimize the introduction of spurious noise and ground loop effects. The entire evaluation system, including the current setting resistors, is mounted in a closed aluminum enclosure to provide additional shielding to external noise sources. LECROY 9210 CH A 9213 TDS5104 CH1 POWER SPLITTER 16 15 14 13 COMM COMM COMM COMM 1 VRDZ 2 VREF VOUT 12 SCAL 11 +IN AD8138 B EVALUATION BOARD A 1k R1 16 AD8305 1nF R2 3 IREF BFIN 10 4 INPT VLOG 9 VSUM VNEG VNEG VPOS 1k 5 1nF 6 7 1nF 1k R1 0.1F VRDZ 2 VREF 14 13 HP 89410A CHANNEL 1 CHANNEL 2 SCAL 11 3 IREF BFIN 10 4 INPT VLOG 9 1nF The setup shown in Figure 11 was used for frequency response measurements of the logarithmic amplifier section. The AD8138 output is offset to 1.5 V dc and modulated to a depth of 5% at frequency. R1 is chosen (over a wide range of values up to 1.0 GW) to provide IPD. The buffer was used to deload VLOG from the measurement system. VOUT 12 AD8305 1k Figure 11. Configuration for Logarithmic Amplifier Bandwidth Measurement TRIGGER 1 200k 8 +VS SOURCE 15 COMM COMM COMM COMM VSUM VNEG VNEG VPOS 5 6 7 8 +VS 0.1F Figure 13. Configuration for Logarithmic Amplifier Pulse Response Measurement Figure 13 shows the setup used to make the pulse response measurements. As with the bandwidth measurement, the VLOG is connected directly to BFIN and the buffer amplifier is configured for unity gain. The buffer’s output is connected through a short cable to the TDS5104 scope with input impedance set to 1 MW. The LeCroy’s output is offset to create the initial pedestal current for a given value of R1, the pulse then creates one-decade current step. EVALUATION BOARD 16 15 14 An evaluation board is available for the AD8305, the schematic for which is shown in Figure 16. It can be configured for a wide variety of experiments. The buffer gain is factory-set to unity, providing a slope of 200 mV/decade, and the intercept is set to 1 nA. Table I describes the various configuration options. 13 COMM COMM COMM COMM 1 VRDZ 2 VREF SCAL 11 AD8305 1nF 200k ALKALINE “D” CELL + – VOUT 12 3 IREF BFIN 10 4 INPT VLOG 9 1k R1 1k 1nF VSUM VNEG VNEG VPOS 5 6 7 8 ALKALINE “D” CELL 0.1F + – + – + – Figure 12. Configuration for Noise Spectral Density Measurement –14– REV. A AD8305 Table I. Evaluation Board Configuration Options Component Function Default Condition P1 Supply Interface. Provides access to supply pins, VNEG, COMM, and VPOS. P1 = Installed P2, R8, R9, R10, R11, R17, R18 Monitor Interface. By adding 0 W resistors to R8, R9, R10, R11, R17, and R18, P2 = Not Installed the VRDZ, VREF, VSUM, VOUT, and VLOG pin voltages can be monitored R8 = R9 = R10 = Open (Size 0603) using a high impedance probe. R17 = R18 = Open (Size 0603) R2, R3, R4, R6, R14, Buffer Amplifier/Output Interface. The logarithmic slope of the AD8305 C2, C7, C9, C10 can be altered using the buffer’s gain-setting resistors, R2 and R3. R4, R14, and C2 allow variation in the buffer loading. R6, C7, C9, and C10 are provided for a variety of filtering applications. R2 = R6 = 0 W (Size 0603) R3 = R4 = Open (Size 0603) R11 = R14 = 0 W (Size 0603) C2 = C7 = Open (Size 0603) C9 = C10 = Open (Size 0603) VLOG = VOUT = Installed R1, R7, R19, R20 Intercept Adjustment. The voltage dropped across resistor R1 determines the R1 = 200 kW (Size 0603) intercept reference current, nominally set to 10 mA using a 200 kW 1% resistor. R7 = R19 = 0 W (Size 0603) R7 and R19 can be used to adjust the output-offset voltage at the VLOG output. R20 = Open (Size 0603) R12, R15, C3, C4, C5, C6 Supply Decoupling. C3 = C4 = 0.01 F (Size 0603) C5 = C6 = 0.1 F (Size 0603) R12 = R15 = 0 W (Size 0603) C11 R13, R16, C1, C8 VSUM Decoupling Capacitor. Input Compensation. Provides essential HF compensation at the input pins, INPT and IREF. C11 = 1 nF (Size 0603) R13 = R16 = 1 kW (Size 0603) C1 = C8 = 1 nF (Size 0603) IREF, INPT, PD, LK1, R5 Input Interface. The test board is configured to accept a current through the IREF = INPT = Installed SMA connector labeled INPT. An SC-style packaged photodiode can be PD = Not Installed used in place of the INPT SMA for optical interfacing. By removing R1 and LK1 = Installed adding a 0 W short for R5, a second current can be applied to the IREF input R5 = Open (Size 0603) (also SMA) for evaluating the AD8305 in log-ratio applications. J1 SC-Style Photodiode. Allows for direct mounting of SC style photodiodes. REV. A –15– J1 = Not Installed AD8305 Figure 14. Component Side Layout Figure 15. Component Side Silkscreen –16– REV. A AD8305 16 15 14 R10 13 VOUT OPEN COMM R20 OPEN R17 VRDZ 1 OPEN R19 OPEN 0 R1 200k I 1% REF R5 IREF COMM COMM VOUT VRDZ OPEN 2 VREF SCAL 11 AD8305 3 IREF BFIN 10 4 INPT VLOG 9 R13 1k I PD 1 C1 1nF VSUM 2 SC-STYLE PD 3 VNEG 5 VNEG 6 C2 OPEN R2 0 R3 C10 OPEN VOUT 0 R4 OPEN C9 OPEN OPEN R6 R8 0 OPEN VLOG R11 VLOG 0 C7 OPEN VPOS 7 R14 12 R7 0 R18 VREF COMM 8 VRDZ 1 AGND 2 VOUT 3 VREF 4 VSUM 5 VLOG 6 INPT C4 0.01F C3 0.01F LK1 C11 1nF R9 OPEN R16 1k C8 VSUM R15 0 1nF R12 0 C5 0.1F C6 0.1F AGND VNEG 1 2 3 VPOS P1 P2 Figure 16. Evaluation Board Schematic REV. A –17– AD8305 OUTLINE DIMENSIONS 16-Lead Leadframe Chip-Scale Package [LFCSP] 3 mm 3 mm Body (CP-16) Dimensions shown in millimeters 3.00 BSC SQ 0.50 0.40 0.30 0.60 MAX PIN 1 INDICATOR 0.45 PIN 1 INDICATOR 1 2 TOP VIEW 2.75 BSC SQ BOTTOM VIEW 0.50 BSC 1.00 0.90 0.80 SEATING PLANE 0.25 MIN 1.50 REF 0.80 MAX 0.65 NOM 12 MAX 1.45 1.30 SQ 1.15 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 –18– REV. A AD8305 Revision History Location Page 3/03—Data Sheet changed from REV. 0 to REV. A. Changes to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to TPC 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REV. A –19– –20– PRINTED IN U.S.A. C03053–0–3/03(A)