a Complete 10-Bit 40 MSPS CCD Signal Processor AD9840A FEATURES 40 MSPS Correlated Double Sampler (CDS) 4 dB 6 dB Variable CDS Gain with 6-Bit Resolution 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function 10-Bit 40 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power: 155 mW @ 3.0 V Supply 48-Lead LQFP Package PRODUCT DESCRIPTION APPLICATIONS Digital Video Camcorders Digital Still Cameras Industrial Imaging The AD9840A operates from a 3 V power supply, typically dissipates 155 mW, and is packaged in a 48-lead LQFP. The AD9840A is a complete analog signal processor for CCD applications. It features a 40 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9840A’s signal chain consists of an input clamp, correlated double sampler (CDS), digitally controlled variable gain amplifier (VGA), black level clamp, and 10-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input configuration, and power-down modes. FUNCTIONAL BLOCK DIAGRAM PBLK AVDD CLPOB AVSS DRVDD CLP 4dB6dB DRVSS 2dB TO 36dB CDS CCDIN 2:1 MUX 10 10-BIT ADC VGA DOUT CLP CLPDM 10 AUX1IN 2:1 MUX BUF OFFSET DAC 6 AUX2IN 8 VRT BANDGAP REFERENCE VRB INTERNAL BIAS CML INTERNAL REGISTERS CLP DVDD DIGITAL INTERFACE AD9840A SL SCK INTERNAL TIMING SDATA SHP SHD DVSS DATACLK REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD9840A–SPECIFICATIONS GENERAL SPECIFICATIONS (T MIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.) Parameter Min TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Fast Recovery Mode Standby Total Power-Down Typ Max Unit –20 –65 +85 +150 °C °C 2.7 3.6 V (Specified Under Each Mode of Operation) 90 5 1 MAXIMUM CLOCK RATE mW mW mW 40 A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage Data Output Coding MHz 10 ± 0.5 ± 1.0 10 2.0 Straight Binary VOLTAGE REFERENCE Reference Top Voltage (VRT) Reference Bottom Voltage (VRB) 2.0 1.0 Bits LSB Bits Guaranteed V V V Specifications subject to change without notice. DIGITAL SPECIFICATIONS (DRVDD = 2.7 V, C = 20 pF unless otherwise noted.) L Parameter Symbol Min LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance VIH VIL IIH IIL CIN 2.1 LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA VOH VOL 2.2 Typ Max 0.6 10 10 10 0.5 Unit V V µA µA pF V V Specifications subject to change without notice. –2– REV. 0 AD9840A CCD-MODE SPECIFICATIONS Parameter (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 40 MHz, unless otherwise noted.) Min Typ POWER CONSUMPTION MAXIMUM CLOCK RATE CDS Allowable CCD Reset Transient 1 Max CCD Black Pixel Amplitude 1 Max Input Range before Saturation 1 Max Input Range before Saturation Max Input Range before Saturation Max Output Range Gain Resolution Gain Range (Two’s Complement Coding) Min Gain (CDS Gain Register Code 32) Medium Gain (CDS Gain Code 63) Max Gain (CDS Gain Code 31) VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (VGA Register Code 91) Max Gain (VGA Code 1023) 155 500 200 64 mV mV V p-p V p-p V p-p V p-p Steps –2 4 10 dB dB dB 1.0 1.5 0.5 1.6 1.6 2.0 With 4 dB CDS Gain With –2 dB CDS Gain With 10 dB CDS Gain At Any CDS Gain Setting 4 dB is Default with CDS Gain Disabled V p-p V p-p Steps 1024 Guaranteed 2 36 dB dB 256 Steps 0 63.75 LSB LSB See Figure 13 for VGA Gain Curve See Page 12 for Gain Equations Measured at ADC Output –1.0 +1.0 0.4 0.25 40 dB % LSB rms dB 0.1 1 3 15 ms ms ms ms Specifications Include Entire Signal Chain Use Equations on Page 12 to Calculate Gain 12 dB Gain Applied (4 dB CDS Gain) AC Grounded Input, 6 dB Gain Applied Measured with Step Change on Supply Clocks Must Be Applied, as in Figures 8 and 9 1V MAX INPUT SIGNAL RANGE Specifications subject to change without notice. REV. 0 See Input Waveform in Note 1 See Figure 15 for CDS Gain Curve NOTES 1 Input Signal Characteristics defined as follows, with 4 dB CDS gain: 200mV MAX OPTICAL BLACK PIXEL Notes MHz POWER-UP RECOVERY TIME From Fast Recovery Mode From Reference Standby Mode From Total Shutdown Mode From Power-Off Condition 500mV TYP RESET TRANSIENT Unit mW 20 BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level Max Clamp Level SYSTEM PERFORMANCE Gain Accuracy, VGA Code 91 to 1023 Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Max –3– AD9840A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS (T MIN Parameter to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.) Min Typ POWER CONSUMPTION 105 MAXIMUM CLOCK RATE 40 INPUT BUFFER Gain Max Input Range 1.0 VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Max Unit mW MHz 0 dB V p-p 2.0 1023 V p-p Steps 0 36 dB dB Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS Parameter (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.) Min Typ POWER CONSUMPTION MAXIMUM CLOCK RATE 105 40 INPUT BUFFER VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Max Unit mW MHz (Same as AUX1-MODE) 2.0 ACTIVE CLAMP Clamp Level Resolution Clamp Level (Measured at ADC Output) Min Clamp Level Max Clamp Level 512 V p-p Steps 0 18 dB dB 256 Steps 0 63.75 LSB LSB Specification subject to change without notice. –4– REV. 0 AD9840A TIMING SPECIFICATIONS (CL = 20 pF, fSAMP = 40 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7. Serial Timing in Figures 8–10.) Parameter Symbol Min SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK Hi/Low Pulsewidth SHP Pulsewidth SHD Pulsewidth CLPDM Pulsewidth CLPOB Pulsewidth1 SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay Inhibited Clock Period tCP tADC tSHP tSHD tCDM tCOB tS1 tS2 tID tINH 25 10 5 5 4 2 0 10 DATA OUTPUTS Output Delay Output Hold Time Pipeline Delay SERIAL INTERFACE Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read Typ Max Unit ns ns ns ns Pixels Pixels ns ns ns ns 12.5 6 6 10 20 6 12.5 3.0 10 tOD tH 7.0 fSCLK tLS tLH tDS tDH tDV 10 10 10 10 10 10 14.5 7.6 9 16 ns ns Cycles MHz ns ns ns ns ns NOTES 1 Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to change without notice. ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS Parameter AVDD1, AVDD2 DVDD1, DVDD2 DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, CLPDM, PBLK SCK, SL, SDATA VRT, VRB, CMLEVEL BYP1-4, CCDIN Junction Temperature Lead Temperature (10 sec) With Respect To Min Max AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS AVSS –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +3.9 +3.9 +3.9 DRVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 300 Model Unit V V V V V V V V V °C °C Temperature Range AD9840AJST –20°C to +85°C Package Option Thin Plastic Quad Flatpack (LQFP) ST-48 THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LQFP Package θJA = 92°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9840A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 Package Description –5– WARNING! ESD SENSITIVE DEVICE AD9840A VRT CML VRB THREE-STATE DVSS DVDD2 NC SDATA SL NC STBY SCK PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 DRVSS 1 DRVSS 2 PIN 1 IDENTIFIER (LSB) D0 3 D1 4 D2 5 D3 6 AD9840A AUX1IN 35 34 AVSS AUX2IN 33 AVDD2 32 BYP4 NC 31 TOP VIEW (Not to Scale) D4 7 D5 8 36 30 29 CCDIN BYP2 D6 9 D7 10 28 BYP1 27 D8 11 26 AVDD1 AVSS 25 AVSS (MSB) D9 12 DVSS SHD CLPDM CLPOB SHP PBLK DVSS DVDD1 DVSS DATACLK DRVSS DRVDD NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24 PIN FUNCTION DESCRIPTIONS Pin Number Name Type Description 1, 2 3–12 13 14 15, 18, 24, 41 16 17 19 20 21 22 23 25, 26, 35 27 28 29 30 31 32 33 34 36 37 38 39 40 42 43 44 45 46 47 48 DRVSS D0–D9 DRVDD DRVSS DVSS DATACLK DVDD1 PBLK CLPOB SHP SHD CLPDM AVSS AVDD1 BYP1 BYP2 CCDIN NC BYP4 AVDD2 AUX2IN AUX1IN CML VRT VRB DVDD2 THREE-STATE NC STBY NC SL SDATA SCK P DO P P P DI P DI DI DI DI DI P P AO AO AI NC AO P AI AI AO AO AO P DI NC DI NC DI DI DI Digital Driver Ground Digital Data Outputs Digital Output Driver Supply Digital Output Driver Ground Digital Ground Digital Data Output Latch Clock Digital Supply Preblanking Clock Input Black Level Clamp Clock Input CDS Sampling Clock for CCD’s Reference Level CDS Sampling Clock for CCD’s Data Level Input Clamp Clock Input Analog Ground Analog Supply Internal Bias Level. Decoupling Internal Bias Level Decoupling Analog Input for CCD Signal Leave Floating or Decouple to Ground with 0.1 F Internal Bias Level Decoupling Analog Supply Analog Input Analog Input Internal Bias Level Decoupling A/D Converter Top Reference Voltage Decoupling A/D Converter Bottom Reference Voltage Decoupling Digital Supply Digital Output Disable. Active High May be tied High or Low. Should not be left floating. Standby Mode, Active High. Same as Serial Interface Standby Mode Internally Not Connected. May be tied high or low Serial Digital Interface Load Pulse Serial Digital Interface Data Serial Digital Interface Clock TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. –6– REV. 0 AD9840A DEFINITIONS OF SPECIFICATIONS DIFFERENTIAL NONLINEARITY (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating conditions. PEAK NONLINEARITY Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9840A from a true straight line. The point used as “zero scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a Level 1, 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC’s full-scale range. chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale/2N codes) when N is the bit resolution of the ADC. For the AD9840A, 1 LSB is 2 mV. POWER SUPPLY REJECTION (PSR) The PSR is measured with a step change applied to the supply pins. This represents a very high-frequency disturbance on the AD9840A’s power supply. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. INTERNAL DELAY FOR SHP/SHD The internal delay (also called aperture delay) is the time delay that occurs from when a sampling edge is applied to the AD9840A until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transition from low to high, so the internal delay is measured from each clock’s rising edge to the instant the actual internal sample is taken. TOTAL OUTPUT NOISE The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB, and represents the rms noise level of the total signal EQUIVALENT INPUT CIRCUITS DVDD ACVDD 330 ACVSS DVSS Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB, CLPDM, HD, VD, PBLK, SCK, SL DVDD ACVSS Figure 3. CCDIN (Pin 30) DRVDD DATA DVDD DVDD DATA IN THREESTATE 330 DATA OUT DOUT RNW DVSS DVSS Figure 4. SDATA (Pin 47) DVSS DRVSS Figure 2. Data Outputs REV. 0 –7– DVSS AD9840A CCD-MODE AND AUX-MODE TIMING CCD SIGNAL N tID N+1 N+2 N+9 N+10 tID SHP tS1 tCP tS2 SHD tINH DATACLK tOD OUTPUT DATA tH N–10 N–9 N–8 N–1 N NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. Figure 5. CCD-Mode Timing EFFECTIVE PIXELS HORIZONTAL BLANKING OPTICAL BLACK PIXELS DUMMY PIXELS EFFECTIVE PIXELS CCD SIGNAL CLPOB CLPDM PBLK OUTPUT DATA OB PIXEL DATA EFFECTIVE PIXEL DATA DUMMY BLACK EFFECTIVE DATA NOTES: 1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB. 2. PBLK SIGNAL IS OPTIONAL. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES. Figure 6. Typical CCD-Mode Line Clamp Timing N+9 N N+1 N+8 N+2 tID VIDEO SIGNAL tCP DATACLK tOD OUTPUT DATA N–10 tH N–9 N–8 N–1 N Figure 7. AUX-Mode Timing –8– REV. 0 AD9840A SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Table I. Internal Register Map Register Name Address A0 A1 A2 Operation 0 0 0 Channel Select CCD/AUX VGA Gain 1 0 0 LSB Clamp Level 0 1 0 LSB Control 1 1 0 0* CDS Gain 0 0 1 LSB D0 D1 D2 Data Bits D4 D5 D3 Power-Down Modes 0* 0* D6 Software OB Clamp 0* Reset On/Off CDS Gain Clock Polarity Select for On/Off SHP/SHD/CLP/DATA MSB X D7 D8 D9 D10 1** 0* 0* 0* MSB X MSB X X X 0* 0* ThreeState X X X X X *Internal use only, must be set to zero. **Should be set to one. RNW TEST 0 SDATA A0 tDS A1 0 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 tDH SCK tLS tLH SL NOTES: 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION. 3. TEST BIT = INTERNAL USE ONLY. MUST BE SET LOW. 4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE. Figure 8. Serial Write Operation RNW SDATA TEST 1 A0 tDS A1 0 A2 D0 tDH D1 D2 D3 D4 D5 D6 D7 D9 D8 D10 tDV SCK tLS tLH SL NOTES: 1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION. 2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW. 3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK FALLING EDGES. Figure 9. Serial Readback Operation RNW A0 SDATA 0 0 11 BITS OPERATION A1 0 0 0 D0 D1 D2 D3 ... D10 D0 D1 D2 D3 1 2 3 4 5 6 7 8 9 ... D9 D0 16 17 18 19 20 ... D7 10 BITS CONTROL D0 ... ... ... SCK 8 BITS CLAMP LEVEL 10 BITS AGC GAIN 26 27 ... D9 ... 34 35 44 SL ... NOTES: 1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME. 2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER. 3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL. Figure 10. Continuous Serial Write Operation to Multiple Registers REV. 0 –9– AD9840A Table II. Operation Register Contents (Default Value x000) D10 D9 D8 D7 D6 0* 0* 0* 1** 0* Optical Black Clamp D5 Reset D4 Power-Down Modes D3 D2 Channel Selection D1 D0 0 Enable Clamping 1 Disable Clamping 0 Normal 1 Reset all Registers to Default 0 0 1 1 0 0 1 1 0 1 0 1 Normal Power Fast Recovery Standby Total Power-Down 0 1 0 1 CCD-Mode AUX1-Mode AUX2-Mode Test Only *Must be set to zero. **Set to one. Table III. VGA Gain Register Contents (Default Value x096) D10 MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 Gain (dB) X 0 0 0 1 0 1 1 1 1 1 2.0 • • • 1 1 1 1 1 1 1 1 1 1 • • • 1 1 1 1 1 1 1 1 0 1 35.965 36.0 Table IV. Clamp Level Register Contents (Default Value x080) D10 D9 D8 X X X MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 Clamp Level (LSB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0.25 0.5 • • • • • • 1 1 1 1 1 1 1 0 63.5 1 1 1 1 1 1 1 1 63.75 Table V. Control Register Contents (Default Value x000) D10 X Data Out D9 0 Enable 1 Three-State D8 D7 0* 0* DATACLK D6 CLP/PBLK D5 SHP/SHD D4 CDS Gain D3 D2 D1 D0 0 Rising Edge Trigger 1 Falling Edge Trigger 0 Active Low 1 Active High 0 Active Low 1 Active High 0 Disabled** 0* 1 Enabled 0* 0* *Must be set to zero. **When D3 = 0 (CDS Gain Disabled), the CDS Gain Register is fixed at 4 dB (code 63 dec). Table VI. CDS Gain Register Contents (Default Value x000) D10 D9 D8 D7 D6 MSB D5 D4 D3 X X X X X 0 0 0 D2 D1 LSB D0 Gain (dB) * 0 0 0 +4.3 • • • 0 1 1 0 1 0 • • • 1 0 1 0 0 0 +10.0 –2.0 1 • • • +4.0 • • • 1 1 1 1 1 *Control Register Bit D3 must be set high for the CDS Gain Register to be used. –10– REV. 0 AD9840A DC RESTORE CDS GAIN REGISTER INTERNAL VREF 6 –2dB TO +10dB 0.1F 2V FULL SCALE 2dB TO 36dB CCDIN CDS 10 10-BIT ADC VGA DOUT INPUT OFFSET CLAMP CLPOB OPTICAL BLACK CLAMP 8-BIT DAC 10 CLPDM DIGITAL FILTERING VGA GAIN REGISTER 0 TO 64 LSB 8 CLAMP LEVEL REGISTER Figure 11. CCD-Mode Block Diagram CIRCUIT DESCRIPTION AND OPERATION The AD9840A signal processing chain is shown in Figure 11. Each processing step is essential in achieving a high-quality image from the raw CCD pixel data. DC Restore To reduce the large dc offset of the CCD output signal, a dc-restore circuit is used with an external 0.1 µF series-coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, to be compatible with the 3 V single supply of the AD9840A. Table VII. Example CDS Gain Settings Max Input Signal Recommended Gain Range 250 mV p-p 500 mV p-p 800 mV p-p 1 V p-p 1.25 V p-p 1.5 V p-p 8 dB to 10 dB 6 dB to 8 dB 4 dB to 6 dB 2 dB to 4 dB 0 dB to 2 dB –2 dB to 0 dB Register Code Range 21 to 31 10 to 21 63 to 10 53 to 63 42 to 53 32 to 42 Correlated Double Sampler The CDS circuit samples each CCD pixel twice to extract the video information and reject low-frequency noise. The timing shown in Figure 5 illustrates how the two CDS clocks, SHP and SHD, are used to sample the reference level and data level of the CCD signal respectively. The CCD signal is sampled on the rising edges of SHP and SHD. Placement of these two clock signals is critical in achieving the best performance from the CCD. An internal SHP/SHD delay (tID) of 3 ns is caused by internal propagation delays. The CDS stage has a default gain of 4 dB, but uses a unique architecture that allows the CDS gain to be varied. Using the CDS Gain Register, the gain-of is programmable from –2 dB to +10 dB in 64 steps, using two’s complement coding. The CDS Gain curve is shown in Figure 12. To change the gain of the CDS using the CDS Gain Register, the Control Register bit D3 must be set high (CDS Gain Enabled). The default gain setting when bit Control Register Bit D3 is low (CDS Gain Disabled) is 4 dB. See Tables V and VI for more details. A CDS gain of 4 dB provides some front-end signal gain and improves the overall signal-to-noise ratio. This gain setting works very well in most applications, and the CCD-Mode Specifications use this default gain setting. However, the CDS gain may be varied to optimize the AD9840A operation in a particular application. Increased CDS gain can be useful with low output level CCDs, while decreased CDS gain allows the AD9840A to accept CCD signal swings greater than 1 V p-p. Table VII summarizes some example CDS gain settings for different maximum signal swings. The CDS Gain Register may also be used “on the fly” to provide a +6 dB boost or –6 dB attenuation when setting exposure levels. It is best to keep the CDS output level from exceeding 1.5 V–1.6 V. REV. 0 10 CDS GAIN – dB 8 6 4 2 0 -2 32 (100000) 40 48 56 0 8 16 24 31 (011111) CDS GAIN REGISTER CODE Figure 12. CDS Gain Curve Input Clamp A line-rate input clamping circuit is used to remove the CCD’s optical black offset. This offset exists in the CCD’s shielded black reference pixels. Unlike some AFE architectures, the AD9840A removes this offset in the input stage to minimize the effect of a gain change on the system black level, usually called the “gain step.” Another advantage of removing this offset at the input stage is to maximize system headroom. Some area CCDs have large black level offset voltages, which, if not corrected at the input stage, can significantly reduce the available headroom in the internal circuitry when higher VGA gain settings are used. Horizontal timing is shown in Figure 6. It is recommended that the CLPDM pulse be used during valid CCD dark pixels. CLPDM may be used during the optical black pixels, either –11– AD9840A together with CLPOB or separately. The CLPDM pulse should be a minimum of four pixels wide. Variable Gain Amplifier The VGA stage provides a gain range of 2 dB to 36 dB, programmable with 10-bit resolution through the serial digital interface. Combined with the typical 4 dB gain from the CDS stage, the total gain range for the AD9840A is 6 dB to 40 dB. A gain of 6 dB will match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems (such as ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB. The VGA gain curve is divided into two separate regions. When the VGA Gain Register code is between 0 and 511, the curve follows a (1 + x)/(1 – x) shape, which is similar to a “linear-indB” characteristic. From code 512 to code 1023, the curve follows a “linear-in-dB” shape. The exact VGA gain can be calculated for any Gain Register value by using the following two equations: Code Range 0–511 512–1023 Gain Equation (dB) Gain = 20 log10 ([658 + code]/[658 – code]) – 0.35 Gain = (0.0354)(code) – 0.35 Using these two equations, the actual gain of the AD9840A can be accurately predicted to within 0.5 dB. As shown in the CCDMode Specifications, only the VGA gain range from 2 dB to 36 dB is specified. This corresponds to a VGA gain code range of 91 to 1023. The Gain Accuracy specifications also include a CDS gain of 4 dB, for a total gain range of 6 dB to 40 dB. 36 VGA GAIN – dB 30 24 18 12 black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the post processing, the AD9840A’s optical black clamping may be disabled using Bit D5 in the Operation Register (see Serial Interface Timing and Internal Register Description section). When the loop is disabled, the Clamp Level Register may still be used to provide programmable offset adjustment. Horizontal timing is shown in Figure 6. The CLPOB pulse should be placed during the CCD’s optical black pixels. It is recommended that the CLPOB pulse duration be at least 20 pixels wide to minimize clamp noise. Shorter pulsewidths may be used, but clamp noise may increase, and the loop’s ability to track low-frequency variations in the black level will be reduced. A/D Converter The AD9840A uses a high-performance ADC architecture, optimized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB. Instead of the 1 V full-scale range used by the earlier AD9801 and AD9803 products from Analog Devices, the AD9840A’s ADC uses a 2 V input range. Better noise performance results from using a larger ADC full-scale range. AUX1-Mode For applications that do not require CDS, the AD9840A can be configured to sample ac-coupled waveforms. Figure 14 shows the circuit configuration for using the AUX1 channel input (Pin 36). A single 0.1 µF ac-coupling capacitor is needed between the input signal driver and the AUX1IN pin. An on-chip dc-bias circuit sets the average value of the input signal to approximately 0.4 V, which is referenced to the midscale code of the ADC. The VGA gain register provides a gain range of 0 dB to 36 dB in this mode of operation (see VGA Gain Curve, Figure 13). The VGA gains up the signal level with respect to the 0.4 V bias level. Signal levels above the bias level will be further increased to a higher ADC code, while signal levels below the bias level will be further decreased to a lower ADC code. AUX2-Mode 6 0 0 127 255 383 511 639 767 VGA GAIN REGISTER CODE 895 1023 Figure 13. VGA Gain Curve (Gain from CDS Not Included) Optical Black Clamp The optical black clamp loop is used to remove residual offsets in the signal chain, and to track low-frequency variations in the CCD’s black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the Clamp Level Register. Any value between 0 LSB and 64 LSB may be programmed, with 8-bit resolution. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical For sampling video-type waveforms, such as NTSC and PAL signals, the AUX2 channel provides black level clamping, gain adjustment, and A/D conversion. Figure 15 shows the circuit configuration for using the AUX2 channel input (Pin 34). An external 0.1 µF blocking capacitor is used with the on-chip video clamp circuit, to level-shift the input signal to a desired reference level. The clamp circuit automatically senses the most negative portion of the input signal, and adjusts the voltage across the input capacitor. This forces the black level of the input signal to be equal to the value programmed into the Clamp Level register (see Serial Interface Register Description). The VGA provides gain adjustment from 0 dB to 18 dB. The same VGA Gain register is used, but only the 9 MSBs of the gain register are used (see Table VIII.) –12– REV. 0 AD9840A 0.8V 0.4V ??V 5k 0.1F 0dB TO 36dB AUX1IN INPUT SIGNAL ADC VGA 10 0.4V 0.4V MIDSCALE VGA GAIN REGISTER Figure 14. AUX1 Circuit Configuration VGA GAIN REGISTER 9 0dB TO 18dB BUFFER VIDEO SIGNAL AUX2IN VGA ADC 0.1F CLAMP LEVEL VIDEO CLAMP CIRCUIT LPF 8 CLAMP LEVEL REGISTER Figure 15. AUX2 Circuit Configuration Table VIII. VGA Gain Register Used for AUX2-Mode D10 X REV. 0 MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 1 1 1 1 X 0 • • • 1 1 1 1 1 1 –13– Gain (dB) 0.0 0.0 • • • 18.0 AD9840A AD9840A CCD VOUT DIGITAL OUTPUTS ADCOUT 0.1F CCDIN REGISTER DATA BUFFER SERIAL INTERFACE DIGITAL IMAGE PROCESSING ASIC CDS/CLAMP TIMING V-DRIVE CCD TIMING TIMING GENERATOR Figure 16. System Applications Diagram APPLICATIONS INFORMATION Grounding and Decoupling Recommendations The AD9840A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 16, the CCD image (pixel) data is buffered and sent to the AD9840A analog input through a series input capacitor. The AD9840A performs the dc restoration, CDS, gain adjustment, black level correction, and analog-to-digital conversion. The AD9840A’s digital output data is then processed by the image processing ASIC. The internal registers of the AD9840A—used to control gain, offset level, and other functions—are programmed by the ASIC or microprocessor through a 3-wire serial digital interface. A system timing generator provides the clock signals for both the CCD and the AFE. As shown in Figure 17, a single ground plane is recommended for the AD9840A. This ground plane should be as continuous as possible, particularly around Pins 25 through 39. This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All decoupling capacitors should be located as close as possible to the package pins. A single clean power supply is recommended for the AD9840A, but a separate digital driver supply may be used for DRVDD (Pin 13). DRVDD should always be decoupled to DRVSS (Pin 14), which should be connected to the analog ground plane. Advantages of using a separate digital driver supply include using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing digital power dissipation, and reducing potential noise coupling. If the digital outputs (Pins 3–12) must drive a load larger than 20 pF, buffering is recommended to reduce digital code transition noise. Alternatively, placing series resistors close to the digital output pins may help reduce noise. Internal Power-On Reset Circuitry After power-on, the AD9840A will automatically reset all internal registers and perform internal calibration procedures. This takes approximately 1 ms to complete. During this time, normal clock signals and serial write operations may occur. However, serial register writes will be ignored until the internal reset operation is completed. Pin 43 (formerly RSTB on the AD9843 non-A) is no longer used for the reset operation. Toggling Pin 43 in the AD9840A will have no effect. –14– REV. 0 AD9840A 3V ANALOG SUPPLY 0.1F 1.0F VRT CML DVSS 0.1F DVDD2 VRB NC STBY NC SCK SDATA SL 3 SERIAL INTERFACE THREE-STATE 1.0F 48 47 46 45 44 43 42 41 40 39 38 37 DRVSS 1 DRVSS 2 (LSB) D0 D1 D7 35 3 4 AVSS 0.1F AVDD2 33 BYP4 0.1F 3V ANALOG SUPPLY 32 AD9840A NC 31 CCDIN TOP VIEW (Not to Scale) 0.1F CCD SIGNAL 30 BYP2 29 BYP1 8 9 28 AVDD1 AVSS 26 AVSS 10 0.1F 27 D8 11 (MSB) D9 12 25 10 0.1F 0.1F CLPDM DVSS SHP SHD PBLK CLPOB DVSS DVDD1 DATACLK 3V DRIVER SUPPLY DRVSS DVSS 13 14 15 16 17 18 19 20 21 22 23 24 DRVDD DATA OUTPUTS AUX1IN AUX2IN 34 D2 5 D3 6 D4 7 D5 D6 36 PIN 1 IDENTIFIER NC = NO CONNECT 6 0.1F CLOCK INPUTS 0.1F 3V ANALOG SUPPLY Figure 17. Recommended Circuit Configuration for CCD-Mode REV. 0 –15– 3V ANALOG SUPPLY AD9840A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.354 (9.00) BSC SQ 37 48 36 1 0.276 (7.00) BSC SQ TOP VIEW (PINS DOWN) 0 MIN 25 12 13 0.019 (0.5) BSC 0.008 (0.2) 0.004 (0.09) 24 0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35) 7 0 0.006 (0.15) SEATING 0.002 (0.05) PLANE PRINTED IN U.S.A. COPLANARITY 0.003 (0.08) C02196–0–10/00 (rev. 0) 48-Lead LQFP (ST-48) –16– REV. 0