IR3Y38M IR3Y38M CCD Signal Process & Digital Interface IC DESCRIPTION PIN CONNECTIONS The IR3Y38M is a bipolar single-chip signal processing IC for CCD area sensors which includes correlated double sampling circuit (CDS), clamp circuit, automatic gain control amplifier (AGC), reference voltage generator, black level detection circuit, 10-bit analog-to-digital converter (ADC), and serial interface for internal circuits. VLOGIC VRB VRT Å NC ADIN ADOFS AGCCTL GND3 AGCOUT VCC3 GND2 48-PIN QFP TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 DO0 1 DO1 2 DO2 3 DO3 4 DO4 5 GND6 6 VCC6 7 DO5 8 DO6 9 DO7 10 DO8 11 DO9 12 FEATURES • Low power consumption : 315 mW (TYP.) • Wide AGC range : 12 to 43.5 dB • High speed sample-and-hold circuits : pulse width 12 ns (MIN.) • Built-in standby mode for power saving applications • Built-in serial interface to control the AGC gain, maximum gain and offset adjustment • 10-bit ADC operating up to 18 MHz • Digital interface for operating 3.3 V logic ICs • Single +5 V power supply • Package : 48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch 36 VCC2 35 Ô 34 OFSCTL 33 OBCAP 32 Î 31 fl/H3 30 fl/H2 29 fl/H1 28  27 ‰ 26 REFCAP 25 VCC1 ADCK GND5 VCC5 SCK VCC4 GND4 SDATA CLPCAP CCDIN REFIN GND1 SHISET 13 14 15 16 17 18 19 20 21 22 23 24 (QFP048-P-0707) In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 IR3Y38M BLOCK DIAGRAM VCC1 GND1 25 23 S/H1 SHISET SDATA 19 ADCK VCC4 GND4 VCC5 GND5 13 17 18 15 14 fl/H2 S/H1 S/H2 fl/H2 SERIAL PARALLEL CONVERTER 6 GND6 12 DO9 21 CLAMP BIAS ERROR AMP 20 24 CLAMP & S/H CURRENT SETUP S/H3 + – 10-BIT A/D CONVERTER 9 DO6 OUTPUT BUFFER 8 DO5 5 DO4 4 DO3 8-BIT AGC GAIN CONTROL D/A CONVERTER 3 DO2 2 DO1 BIAS – GAIN 1 DO0 6-BIT OFFSET CONTROL D/A CONVERTER + OBP GND2 37 10 DO7 MAX. GAIN SELECTOR – AGC AMP fl/H3 VCC2 36 11 DO8 + OBP CLPCAP S/H2 fl/H1 26 CLP CCDIN CLAMP fl/H1 REFCAP SCK 16 7 VCC6 22 CLP REFIN  fl/H1 fl/H2 28 29 30 VCC3 38 + CLAMP GND3 40 BLK + 31 32 35 fl/H3 Î Ô 34 33 OFSCTL OBCAP 41 39 43 45 42 47 46 AGCCTL AGCOUT ADIN Å ADOFS VRB VRT 2 48 27 VLOGIC ‰ IR3Y38M PIN DESCRIPTION (The voltage is measured on condition that VCC1 to VCC6 = +5.0 V, VLOGIC = +3.3 V.) PIN NO. PIN NAME VOLTAGE 1 DO0 2 DO1 EQUIVALENT CIRCUIT DESCRIPTION Digital data output pins of the A/D converter. DO0 is LSB. VCC6 500 The data format is a straight binary code. 3.1 V 200 3 DO2 4 DO3 0.2 V VOL : 0.2 V (TYP.) 10 k 5 DO4 6 GND6 0.0 V 7 VCC6 5.0 V 8 DO5 9 DO6 VOH : VLOGIC – 0.2 V (TYP.) GND6 GND pin of the output buffer of the A/D converter. Power supply pin of the output buffer of the A/D converter. Digital data output pins of the A/D converter. DO9 is MSB. VCC6 500 The data format is a straight binary code. 3.1 V 200 10 DO7 11 DO8 0.2 V VOL : 0.2 V (TYP.) 10 k 12 DO9 VOH : VLOGIC – 0.2 V (TYP.) GND6 VCC5 converter. 150 µ The A/D conversion is executed at the rising edge of the ADCK, and > 2.1 V 200 13 13 ADCK the data is output at the falling edge of the ADCK. < 0.7 V GND5 14 GND5 0.0 V 15 VCC5 5.0 V converter. Digital power supply pin of the A/D converter. Clock input pin of the serial interface. 15 µ Refer to "TRUTH TABLE" of pin 19. > 2.1 V 200 SCK Duty : 50% fmax : 18 MHz (MIN.) Digital GND pin of the A/D VCC1 16 Clock input pin of the A/D 16 < 0.7 V GND1 3 IR3Y38M PIN NO. PIN NAME VOLTAGE 17 VCC4 5.0 V 18 GND4 0.0 V EQUIVALENT CIRCUIT DESCRIPTION Analog power supply pin of the A/D converter. Analog GND pin of the A/D converter. VCC1 15 µ Data input pin of the serial interface. TRUTH TABLE > 2.1 V 200 19 SDATA 19 < 0.7 V SDATA SCK Action DATA › SHIFT 0 1 fi fi – STORE GND1 VCC1 Bias decoupling pin of the CDS signal clamp circuit. This pin is connected to the GND1 via a 20 CLPCAP 3.2 V capacitor. 200 20 100 µ GND1 VCC1 21 CCDIN 2.5 V 26 k Signal input pin of the CDS. Input CCD signal to this pin via a capacitor. 150 µ 200 Reference input pin of the CDS. 22 REFIN This pin is connected to the GND1 26 k 2.5 V 150 µ via a capacitor. GND1 GND pin of the CDS/AGC. Pay careful attention to board 23 GND1 0.0 V layout of the GND1 because the CDS/AGC are noise-sensitive circuitry. VCC1 2k 2k 26 k Operation current setting pin of the CDS and fl/H3 circuits. This pin is connected to the GND1 24 SHISET 1.7 V via a resistor. The slew rates of the fl/Hs are in 200 24 inverse proportion to the value of the resistor. 13 k GND1 4 IR3Y38M PIN NO. PIN NAME VOLTAGE 5.0 V 25 VCC1 EQUIVALENT CIRCUIT DESCRIPTION Power supply pin of the CDS/AGC. VCC1 75 µ 36 k 26 REFCAP 3.2 V Bias decoupling pin of the CDS reference clamp circuit. This pin is connected to the GND1 via a capacitor. 200 26 63 k 150 µ 2k GND1 VCC1 5.0 V (open) 27 ‰ > 2.1 V 40 µ 110 k 68 k 200 27 65 k 10 k consumption is decreased when low. The threshold voltage has 0.4 V 32 k 75 k < 0.7 V Standby function control pin. All actions stop and the power hysteresis. Connect to the Vcc if not used. GND1 Pulse input pin of the CDS feed28  29 fl/H1 VCC1 Pulse input pin of the fl/H1. 50 µ Signal is sampled when low. > 2.1 V 200 30 31 Pulse input pin of the fl/H2. fl/H2 flH3 Signal is sampled when low. Pulse input pin of the fl/H3. < 0.7 V 100 Signal is sampled when low. GND1 32 Î VCC2 20 k 3.3 k 33 OBCAP through level clamp. Signal is clamped when low. 3.7 V 20 k 3.3 k Pulse input pin of the OPB clamp and bias error amplifier. Signal is clamped when low. Clamp capacitor pin of the optical black clamp (OPB clamp) circuit. Connect to the GND2 via a capacitor. 200 33 80 µ 80 µ GND2 5 IR3Y38M PIN NO. PIN NAME VOLTAGE EQUIVALENT CIRCUIT VCC1 2.15 34 OFSCTL 200 blanking offset control D/A converter. Connect to the GND1 via 30 k 34 to DESCRIPTION Decoupling capacitor pin of the a capacitor. 10 k 2.30 V 2.2 V D/A 100 µ GND1 VCC2 The output of the AGCOUT pin is blanked when low. The blanking 20 µ > 2.1 V 200 35 Ô Blanking pulse input pin. level can be controlled by the serial interface. 35 < 0.7 V GND2 36 VCC2 5.0 V 37 GND2 0.0 V 38 VCC3 5.0 V Power supply pin of the fl/H3 and OPB clamp circuits. GND pin of the fl/H3 and OPB clamp circuits. Power supply pin of the output buffer circuit connected to the AGCOUT pin. Signal output pin of the AGC. Connect to the ADIN pin via a VCC3 300 capacitor. 39 0.9 V AGCOUT (Î = L) 20 39 10 k GND3 40 GND3 GND pin of the output buffer circuit connected to the AGCOUT pin. 0.0 V VCC1 50 µ 2.5 41 AGCCTL to 3.8 V 200 Decoupling capacitor pin of the AGC gain control D/A converter. Connect to the GND1 via a capacitor. 11 k 41 D/A GND1 6 IR3Y38M PIN NO. PIN NAME VOLTAGE EQUIVALENT CIRCUIT VCC4 3.3 V (open) 42 ADOFS Input range black level clamp. This pin is biased at 3.3 V from the inside of the IC. 70 k 200 42 1.6 to Connect to the GND4 via a 70 k 79 k 25 µ capacitor if not used. 25 µ 75 µ 5.0 V GND4 VCC4 50 µ 43 ADIN 1.4 V (Å = L) DESCRIPTION Voltage adjustment pin of the ADC 50 µ 200 Signal input pin of the ADC. Connect to the AGCOUT pin via a capacitor. This capacitor is also used as the clamp capacitor of the ADC blank 43 16 k level clamp. 16 k GND4 No connection. It is recommended 44 NC to connect to GND for better heat VCC4 level clamp. Signal is clamped 25 µ when low. When the ADOFS is opened, the > 2.1 V 45 200 Å radiation and avoiding noise. Pulse input pin of the ADC black 45 clamped level is set to make the ADC output 61 (decimal). < 0.7 V GND4 VCC4 Upper reference decoupling pin of the ADC. Connect to the GND4 via 5 46 VRT 46 VRT 3.90 V a capacitor. GND4 VCC4 Lower reference decoupling pin of 5 47 VRB the ADC. Connect to the GND4 via a capacitor. 47 VRB 1.95 V GND4 GND4 7 IR3Y38M PIN NO. PIN NAME VOLTAGE EQUIVALENT CIRCUIT VCC5 high level voltage of the DO0 to DO9 pins is set to VLOGIC – 0.2 V. 25 µ 48 VLOGIC 3.3 V DESCRIPTION ADC output voltage setting pin. The It is recommended to connect to the 200 48 power supply of the following logic ICs. GND5 FUNCTIONAL DESCRIPTION CDS Circuit Blanking Circuit The clamp circuit clamps the feed-through level of the CCD signal with the  pulse. Then the fl/H1 circuit samples the signal period of the one with the fl/H1 pulse and holds on. Thus the video signal is obtained. But this signal has a level drop caused by the reset pulse of the CCD signal, and for removing it, the fl/H2 circuit samples this signal again with the fl/H2 pulse. For reducing the effect of the sampling pulse or other noise sources, the CDS circuit is formed with a differential structure. The output signal is fixed to the blanking level with the Ô pulse. The blanking level is the sum of the black level and the offset value decided by the value of the OFFSET serial register. A/D Converter Circuit The fl/H3 circuit samples the amplified signal with the fl/H3 pulse and the A/D converter converts the sampled signal to 10-bit straight binary digital data. The clamp circuit placed in front of the A/D converter clamps the signal level beside the lower limit of the convertible input range with the Å pulse. The clamped level is controllable by the voltage of the ADOFS pin. The A/D conversion is executed at the rising edge of the ADCK clock, and the data is output at the falling edge. The high level voltage of the outputs is controlled by the voltage of the VLOGIC pin. Bias Error Amplifier Circuit For stabilizing the bias level of the CDS circuit and reducing the offset of the AGC circuit, the bias error amplifier acts with the Î pulse during the OPB period. AGC Amplifier Circuit The AGC amplifier amplifies the video signal obtained by the CDS circuit. The gain of the AGC is controlled by the value of the AGCGAIN serial register. And the maximum gain of the AGC is controlled by the value of the GAINSEL serial register. Standby Function By making the ‰ pin low, all actions of this IC stop and power consumption is decreased. The outputs of the A/D converter (DO0 to DO9) turn to high impedance when on standby. OPB Clamp Circuit For clamping the level of the amplified signal to the black level, the OPB clamp circuit acts with the Î pulse during the OPB period. 8 IR3Y38M Serial Interface Circuit the rising edge of the SCK. While transmitting data, the SDATA must be low when the SCK falls. When the SDATA is high and the SCK falls, the data on the shift register is stored at the selected data register at the following falling edge of the SDATA. The stored data register is selected by the data of the D0 and D1 bits. The IR3Y38M has a serial interface to control the gain of the AGC amplifier and the offset of the blanking level. This interface is constituted by a shift register for serial-parallel conversion, data registers and D/A converters. The data input to SDATA is fetched and shifted at SDATA D0 Shift Register SCK D1 Store Select D2-D9 3-bit Register 8-bit Register 6-bit Register Gain Selector 8-bit D/A Converter 6-bit D/A Converter AGC GAIN OFFSET MAXIMUM GAIN (dB) 22 25 GAIN SEL 0 1 Decoder 2 28 3 4 31.5 34.5 5 6 38 41 7 43.5 3.3 µs min. Dummy Cycle Store SCK D9 SDATA D8 D7 D6 D5 D3 D4 D2 D1 D0 DATA REGISTER GAIN SEL D9 D8 D7 D6 D5 D4 d0 D3 d1 D2 d2 D1 0 D0 AGC GAIN OFFSET d0 d1 d2 d0 d3 d1 d4 d2 d5 d3 d6 d4 d7 d5 0 1 1 0 1 1 (Don't care) LSB MSB 65 L= OFFSET (mV) AGC GAIN (dB) 43.5 7 E NS I 22 12 0 GA EL = 0 GAIN S 0 –75 0 255 63 Value of OFFSET Value of AGC GAIN 9 IR3Y38M TIMING CHART Reset Pulse CCD IN Signal Level SIG3 SIG2 SIG1 Feed-through Level  fl/H1 fl/H2 S/H1 output SIG3 SIG2 SIG1 SIG3 S/H2 output AGC output SIG2 SIG1 SIG1 SIG2 SIG3 fl/H3 SIG1 S/H3 output SIG2 SIG3 ADCK DO0-DO9 SIG1 tDLH tDHL 10 SIG2 tWLH tWHL SIG3 IR3Y38M CCD IN 2 ns min. –1 ns min.  12 ns min. 3 ns min. 2 ns min. fl/H1 12 ns min. 5 ns min. 3 ns min. fl/H2 3 ns min. 35 ns min. 12 ns min. fl/H3 35 ns min. 1 ns min. 12 ns min. ADCK 25 ns min. signal interval 25 ns min. idle transfer interval OPB interval Î 1.5 µs min. Ô Å 1.5 µs min. 11 signal interval IR3Y38M PRECAUTIONS converter is controllable by the voltage of the VLOGIC pin, but take care that the high level voltage does not fall below about 1.5 V, in spite of making the VLOGIC pin 0 V. This may cause the latch up of the following logic ICs if the power supply of this IC rises up faster than the power supply of the following logic. To avoid this problem, it is recommended to make the ‰ pin low until the voltage of the logic power supply becomes stable. Take care too that the high level voltage does not rise above about VCC – 1.0 V, in spite of making the VLOGIC pin the VCC potential. Each VCC1 to VCC6 pin corresponds to the each GND1 to GND6 pin. Connect a ceramic capacitor as near the IC as possible between each corresponding VCC pin and GND pin. The GND1 pin is the ground of the CDS/ADC circuit handling a weak signal. Pay careful attention to the board layout of the GND1 pattern in order to avoid the potential fluctuation of the GND1 caused by the current of the other GND pins. Especially pay attention to the current of the GND6 pin's flowing spiky current. Restore the value of the serial register when setting up the power supply or making the ‰ pin high because the value will have been removed in that case. All the GND pins must be at the same potential and not open. And keep the potential difference of each VCC pin within 0.3 V. The high level voltage of the outputs of the A/D ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage Input voltage Power consumption (Unless otherwise specified, TA = +25 ˚C) SYMBOL VCC1-VCC6 VIN CONDITIONS RATING 7 –0.3 to VCC + 0.3 UNIT V V PD TA ≤ +25 ˚C 570 mW 4.5 mW/˚C PD derating ratio TA > +25 ˚C Operating temperature TOPR –30 to +70 ˚C Storage temperature TSTG –55 to +150 ˚C APPLICABLE PINS RATING 4.75 to 5.25 UNIT V CCDIN 200 mVp-p 0 to 0.7 V 2.1 to VCC V RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltage Standard CCD input signal level Input "Low" voltage Input "High" voltage S/H pulse width Clamp pulse width SYMBOL VCC1-VCC6 VCCD VIL ‡, SCK, SDATA, VIH ‰, Â, fl/H1, fl/H2, fl/H3, Î, Ô, Å tWS/H tWC Â, fl/H1, fl/H2, fl/H3 A/D converter clock frequency fADCK Î, Å ADCK Serial interface clock frequency fSCK SCK 12 ≥ 12 ns ≥ 1.5 ≤ 18 µs MHz ≤ 300 kHz IR3Y38M ELECTRICAL CHARACTERISTICS DC Characteristics (Unless otherwise specified, TA = +25 ˚C, VCC1 = VCC2 = VCC3 = VCC4 = VCC5 = VCC6 = 5.0 V, VLOGIC = 3.3 V, ADCK = 0 V, SCK = 0 V, SDATA = 0 V, ‰ = 3.3 V,  = 0 V, fl/H1 = 0 V, fl/H2 = 0 V, fl/H3 = 0 V, Ô = 3.3 V, Î = 0 V, SW42 = OFF, SW43 = (a), Å = 3.3 V) The current direction flowing into the pin is positive direction. • General PARAMETER Supply current (1) SYMBOL CONDITIONS Measure pin 25 (VCC1) ICC1 MIN. – TYP. 27 MAX. 34 UNIT mA Supply current (2) Supply current (3) ICC2 ICC3 Measure pin 36 (VCC2). Measure pin 38 (VCC3). – – 2.3 0.7 2.8 1.0 mA mA Supply current (4) ICC4 Supply current (5) ICC5 Measure pin 17 (VCC4). Measure pin 15 (VCC5). – – 13 16 20 21 mA mA Supply current (6) Total supply current ICC6 ICC Measure pin 7 (VCC6). Total of ICC1 to ICC6 – – 5.0 63 6.5 77 mA mA ISTBY ‰ = 0 V, Total of ICC1 to ICC6. – 4.5 6.5 mA –3.5 –2.0 – µA – 0 0.1 µA –0.3 –0.2 – µA – 0 0.1 µA –0.5 –0.3 0 µA – 0 0.1 µA Standby supply current Input "Low" current (1) IIL1 VIL = 0 V Input "High" current (1) IIH1 Input "Low" current (2) IIL2 Input "High" current (2) Input "Low" current (3) Input "High" current (3) Apply to pin 28 (Â), pin 29 (fl/H1), pin 30 (fl/H2), pin 31 (fl/H3), and pin 32 (Î). IIH2 IIL3 IIH3 Apply to pin 28 (Â), pin 29 (fl/H1), pin 30 (fl/H2), pin 31 (fl/H3), and pin 32 (Î). VIH = 3.3 V Apply to pin 16 (SCK) and pin 19 (SDATA). VIL = 0 V Apply to pin 16 (SCK) and pin 19 (SDATA). VIH = 3.3 V Apply to pin 35 (Ô) and pin 45 (Å). VIL = 0 V Apply to pin 35 (Ô) and pin 45 (Å). VIH = 3.3 V Input "Low" current (4) IIL4 Apply to pin 13 (ADCK). VIL = 0 V –3.5 –2.0 – µA Input "High" current (4) IIH4 Apply to pin 13 (ADCK). VIH = 3.3 V – 0 0.1 µA V27 Open pin 27 (‰). ‰ voltage ‰ impedance Z27 13 4.5 5.0 – V 70 110 140 k$ IR3Y38M • CDS & AGC Circuits PARAMETER CLPCAP voltage SYMBOL V20 CONDITIONS MIN. 2.9 TYP. 3.2 MAX. 3.6 UNIT V 2.8 2.8 V V CCDIN voltage REFIN voltage V21 V22 2.3 2.3 2.5 2.5 SHISET voltage V24 1.5 1.7 1.9 V REFCAP voltage V26 OBCAP voltage V33 2.9 3.3 3.2 3.7 3.6 4.0 V V AGCOUT voltage CCDIN impedance V39 0.7 0.9 1.1 V Z21 9 13 18 k$ REFIN impedance Z22 9 13 18 k$ REFCAP impedance OFSCTL impedance Z26 15 23 32 k$ Z34 6 9 12 k$ AGCCTL impedance CLPCAP charge Z41 7 11 15 k$ – –135 –110 µA 110 135 – µA current CLPCAP discharge current IL20 IH20 CLPCAP = 2.8 V, OBP = 0 V Measure the current of CLPCAP. CLPCAP = 3.6 V, OBP = 0 V Measure the current of CLPCAP. CLPCAP leakage current IZ20 CLPCAP = 3.2 V, OBP = 3.3 V Measure the current of CLPCAP. –0.5 0 0.5 µA OBCAP charge current IL33 OBCAP = 3.3 V, OBP = 0 V Measure the current of OBCAP. – –90 –65 µA 65 90 – µA –0.5 0 0.5 µA OBCAP discharge current OBCAP leakage current IH33 IZ33 OBCAP = 4.1 V, OBP = 0 V Measure the current of OBCAP. OBCAP = 3.7 V, OBP = 3.3 V Measure the current of OBCAP. 14 IR3Y38M • A/D Converter Circuit PARAMETER ADOFS voltage SYMBOL V42 CONDITIONS TYP. 3.3 MAX. 3.6 UNIT V 1.2 3.7 1.4 3.9 1.6 4.1 V V ADIN voltage VRT voltage V43 V46 VRB voltage V47 1.8 1.95 2.2 V ADOFS impedance Z42 50 70 90 k$ ADIN charge current IL43 – –45 –30 µA 30 45 – µA –0.3 0 0.3 µA – 0.2 0.4 V 2.9 3.1 – V ADIN discharge current IH43 ADIN leakage current IZ43 Output "Low" voltage VOL ADCLP = 0 V MIN. 3.0 ADIN = 1.0 V, ADCLP = 0 V Measure the current of ADIN. ADIN = 1.8 V, ADCLP = 0 V Measure the current of ADIN. ADIN = 1.4 V, ADCLP = 3.3 V Measure the current of ADIN. SW43 = (b), ADCIN = 0.8 V Change the level of ADCK to L/H/L, then measure the voltages of DO0 to DO9 pins. SW43 = (b), ADCIN = 3.5 V Output "High" voltage VOH Change the level of ADCK to L/H/L, then measure the voltages of DO0 to DO9 pins. 15 IR3Y38M AC Characteristics (Unless otherwise specified, TA = +25 ˚C, VCC1 = VCC2 = VCC3 = VCC4 = VCC5 = VCC6 = 5.0 V, VLOGIC = 3.3 V, ADCK = 0 V, SCK = 0 V, SDATA = 0 V, ‰ = 3.3 V,  = 3.3 V, fl/H1 = 0 V, fl/H2 = 0 V, fl/H3 = 0 V, Ô = 3.3 V, Î = 3.3 V, SW42 = OFF, SW43 = (a), Å = 3.3 V, (OFFSET) = 32) The value of the serial register is written with decimal. • CDS & AGC Circuits PARAMETER AGC minimum gain SYMBOL GAN CONDITIONS (GAIN SEL) = 0, (AGC GAIN) = 0  = SG2, Î = SG3 Input the attenuated SG1 (f = 2 MHz, V = 1.6 Vp-p) to the SIN and seek the attenuation amount to make the amplitude of AGCOUT MIN. TYP. MAX. UNIT 11 12 13 dB 20.5 22 24.5 dB 23 25 28 dB 26 28 31 dB 28.5 31.5 35 dB 31 34.5 38 dB 34 38 42 dB 36.5 41 44.5 dB 38.5 43.5 47.5 dB 26.5 31.5 35.5 dB 1.6 Vp-p. AGC maximum gain (0) AGC maximum gain (1) AGC maximum gain (2) AGC maximum gain (3) AGC maximum gain (4) AGC maximum gain (5) AGC maximum gain (6) AGC maximum gain (7) AGC gain variable width (GAIN SEL) = 0, (AGC GAIN) = 255 GAX0 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 1, (AGC GAIN) = 255 GAX1 GAX2 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 2, (AGC GAIN) = 255 Measure the gain using the same procedure as for the measurement of GAN. GAX3 (GAIN SEL) = 3, (AGC GAIN) = 255 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 4, (AGC GAIN) = 255 GAX4 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 5, (AGC GAIN) = 255 GAX5 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 6, (AGC GAIN) = 255 GAX6 GAX7 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 7, (AGC GAIN) = 255 Measure the gain using the same procedure as for the measurement of GAN. GAR GAR = GAX7 – GAN 16 IR3Y38M PARAMETER SYMBOL CONDITIONS (GAIN SEL) = 0, (AGC GAIN) = 0 MIN. TYP. MAX. UNIT 24 35 – MHz 13 20 – MHz – –75 –60 mV 50 65 – mV 2.0 2.2 – Vp-p 2.0 2.2 – Vp-p  = SG2, Î = SG3 Bandwidth (1) (Minimum gain) fTN Input the SG1 (f = 2 MHz, V = 0.2 Vp-p) to the SIN and measure the amplitude of the AGCOUT. Increase the frequency and measure the frequency when the amplitude attenuates to –3 dB. (GAIN SEL) = 7, (AGC GAIN) = 255  = SG2, Î = SG3 Bandwidth (2) (Maximum gain) fTX Input the SG1 (f = 2 MHz, V = 8 mVp-p) to the SIN and measure the amplitude of the AGCOUT. Increase the frequency and measure the frequency when the amplitude attenuates to –3 dB. (GAIN SEL) = 0, (AGC GAIN) = 0 SIN = GND1, (OFFSET) = 0,  = 0 V, OFFSET adjustment limit (1) VBON (OFFSET = 0) Î=0V Measure the voltage of the AGCOUT at BLK = 3.3 V and define it VBO11. Measure the one similarly at BLK = 0 V and define it VBO12. VBON = VBO12 – VBO11 (GAIN SEL) = 0, (AGC GAIN) = 0 OFFSET adjustment limit (2) SIN = GND1, (OFFSET) = 63,  = 0 V, VBOX (OFFSET = 63) above-mentioned method. VBON = VBO22 – VBO21 (GAIN SEL) = 0, (AGC GAIN) = 0  = SG2, Î = SG3 Output dynamic range (1) VDYN (Minimum gain) Output dynamic range (2) (Maximum gain) Î=0V Measure the VBO21 and VBO22 similarly to Input the SG1 (f = 2 MHz, V = 0.9 Vp-p) to the SIN and measure the amplitude of the AGCOUT. VDYX (GAIN SEL) = 7, (AGC GAIN) = 255  = SG2, Î = SG3 Input the SG1 (f = 2 MHz, V = 50 mVp-p) to the SIN and measure the amplitude of the AGCOUT. 17 IR3Y38M • A/D Converter Circuit (Unless otherwise specified, TA = +25 ˚C, VCC1 = VCC2 = VCC3 = VCC4 = VCC5 = VCC6 = 5.0 V, VLOGIC = 3.3 V, ADCK = 18 MHz square wave, ˘= 0 V, ˙ = 0 V, ‰ = 3.3 V,  = 3.3 V, fl/H1 = 0 V, fl/H2 = 0 V, fl/H3 = 0 V, Ô = 3.3 V, Î = 3.3 V, SW42 = OFF, SW43 = (b), Å = 3.3 V) PARAMETER Clamp value SYMBOL DCLP CONDITIONS SW43 = (a) Å=0V ADCIN = GND4 MIN. TYP. MAX. UNIT 56 61 66 – 31 36 41 – 81 86 91 – – ±0.5 ±0.9 LSB – ±3 ±7 LSB 15 26 38 ns 15 26 38 ns 10 17 25 ns 10 17 25 ns Read the output value of DO0 to DO9. SW42 = ON, V42 = 5.0 V, Å = 0 V, Clamp value adjustment limit (1) DCLPN Clamp value adjustment limit (2) DCLPX Differential linearity error DLE ADCIN = GND4 Read the output value of DO0 to DO9. SW42 = ON, V42 = 1.6 V, Å = 0 V, ADCIN = GND4 Read the output value of DO0 to DO9. ADCIN = SG4 Read the output value of DO0 to DO9 at about 6 Integral linearity error ILE 10 times and make it a histogram. Normalize the histogram and obtain the DLE. Integrate the histogram and obtain the ILE. Propagation delay (L/H) tDLH ADCIN = SG4, CL = 20 pF Measure the delay time from the falling edge (50%) of the ADCK to the rising edge (50%) of the DO0 to DO9. ADCIN = SG4, CL = 20 pF Propagation delay (H/L) tDHL Measure the delay time from the falling edge (50%) of the ADCK to the falling edge (50%) of the DO0 to DO9. ADCIN = SG4, CL = 20 pF Output rise time tWLH Measure the rise time (10%/90%) of the DO0 to DO9. Output fall time tWHL Measure the fall time (90%/10%) of the DO0 to DO9. ADCIN = SG4, CL = 20 pF 18 IR3Y38M Measurement Waveforms f [Hz] V SG1 3.3 V SG2 0V 3.3 V SG3 0V above 1.5 µs below 100 µs 3.5 V SG4 1.1 V 1 ms 19 IR3Y38M Test Circuit Ô Î fl/H3 fl/H2 fl/H1  0.1 µF V27 0.1 µF 0.1 µF Vcc1 Vcc2 + 36 37 AGCOUT 34 33 32 31 28 38 27 26 + – Vcc3 25 0.1 µF + SHISET 24 GND1 23 41 + AGC Gain – S/H1 S/H2 S/H1 S/H2 Clamp 22 Clamp SW43 (b) 44 NC + 20 19 CLAMP GND4 18 Vcc4 17 0.1 µF 100 µF + VCC4 SCK 10-bit A/D Converter VRT VCC5 Vcc5 46 0.1 µF SDATA 16 45 Å SIN 0.1 µF Serial/Parallel Converter Gain Selector 43 GND 21 – ERR + (a) 0.1 µF 22 K$ 1 µF 8-bit D/A 6-bit D/A 42 100 µF 1 µF Bias 39 GND3 SW42 + Vcc1 GND2 40 0.1 µF ADIN 29 STBY S/H3 v42 30 Vcc2 100 µF 0.1 µF + Vcc3 100 µF 0.1 µF 35 15 VRB 14 47 0.1 µF GND5 Output Buffer 2 3 4 5 6 7 13 Vcc6 1 GND6 48 VLOGIC 8 9 10 11 12 0.1 µF 20 pF 20 pF 20 pF 20 pF 20 pF 20 pF 20 pF 20 pF 20 pF 20 pF 100 µF + DO0 DO1 DO2 DO3 DO4 Vcc6 DO5 20 + 0.1 µF 100 µF DO6 DO7 DO8 DO9 ADCK PACKAGES FOR CCD AND CMOS DEVICES PACKAGE (Unit : mm) 48 QFP (QFP048-P-0707) 0.15±0.05 0.2±0.08 M (1.0) 25 36 37 48 13 7.0±0.2 12 (1.0) 0.1±0.1 21 0.1 8.0±0.2 0.65±0.2 1.45±0.2 9.0±0.3 Package base plane 1 (1.0) (1.0) 7.0±0.2 0.08 24 9.0±0.3 0.5TYP.