19-1080; Rev 0; 6/96 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ________________________Applications Digital Gain and Offset Adjustments Programmable Attenuators Programmable Current Sources ____________________________Features ♦ +2.7V to +3.6V Single-Supply Operation ♦ Ultra-Low Supply Current: 0.7mA while Operating 1µA in Shutdown Mode ♦ Ultra-Small 16-Pin QSOP Package ♦ Ground to VDD Reference Input Range ♦ Output Buffer Amplifiers Swing Rail to Rail ♦ 10MHz Serial Interface, Compatible with SPI, QSPI (CPOL = CPHA = 0 or CPOL = CPHA = 1), and Microwire ♦ Double-Buffered Registers for Synchronous Updating ♦ Serial Data Output for Daisy Chaining ♦ Power-On Reset Clears Serial Interface and Sets All Registers to Zero ♦ Software Shutdown ♦ Software-Programmable Logic Output ♦ Asynchronous Hardware Clear Resets All Internal Registers to Zero ______________Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX533ACPE MAX533BCPE MAX533ACEE MAX533BCEE MAX533BC/D MAX533AEPE MAX533BEPE MAX533AEEE MAX533BEEE MAX533AMJE MAX533BMJE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP Dice* 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP** 16 CERDIP** Portable Instruments __________________Pin Configuration TOP VIEW OUTB 1 16 OUTC OUTA 2 15 OUTD REF 3 14 AGND UPO 4 MAX533 PDE 5 13 VDD 12 DGND LDAC 6 11 DIN CLR 7 10 SCLK DOUT 8 9 INL (LSB) ±1 ±2 ±1 ±2 ±2 ±1 ±2 ±1 ±2 ±1 ±2 *Dice are tested at TA = +25°C. **Contact factory for availability and processing to MIL-STD-883. CS Functional Diagram appears at end of data sheet. DIP/QSOP SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX533 _______________General Description The MAX533 serial-input, voltage-output, 8-bit quad digital-to-analog converter (DAC) operates from a single +2.7V to +3.6V supply. Internal precision buffers swing rail to rail, and the reference input range includes both ground and the positive rail. The MAX533 features a 1µA shutdown mode. The serial interface is double buffered: a 12-bit input shift register is followed by four 8-bit buffer registers and four 8-bit DAC registers. The 12-bit serial word consists of eight data bits and four control bits (for DAC selection and special programming commands). Both the input and DAC registers can be updated independently or simultaneously with a single software command. Two additional asynchronous control pins, LDAC and CLR, provide simultaneous updating or clearing of the input and DAC registers. The interface is compatible with SPI™, QSPI™ (CPOL = CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A buffered data output allows daisy chaining of serial devices. In addition to 16-pin DIP and CERDIP packages, the MAX533 is available in a 16-pin QSOP that occupies the same area as an 8-pin SO. MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ABSOLUTE MAXIMUM RATINGS VDD to DGND ..............................................................-0.3V, +6V VDD to AGND...............................................................-0.3V, +6V Digital Input Voltage to DGND ....................................-0.3V, +6V Digital Output Voltage to DGND....................-0.3V, (VDD + 0.3V) AGND to DGND ..................................................................±0.3V REF ................................................................-0.3V, (VDD + 0.3V) OUT_ ...........................................................................-0.3V, VDD Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 10.53mW/°C above +70°C) .........842mW QSOP (derate 8.3mW/°C above +70°C) .....................667mW CERDIP (derate 10.00mW/°C above +70°C) ..............800mW Operating Temperature Ranges MAX533 _ C_ E ..................................................0°C to +70°C MAX533 _ E_ E ...............................................-40°C to +85°C MAX533 _ MJE .............................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 8 Bits STATIC ACCURACY Resolution MAX533A ±1 MAX533B ±2 Integral Nonlinearity (Note 1) INL Differential Nonlinearity (Note 1) DNL Guaranteed monotonic (all codes) ±1.0 LSB Zero-Code Error ZCE Code = 00 hex ±20 mV 1 LSB Zero-Code-Error Supply Rejection Code = 00 hex, VDD = 2.7V to 3.6V Zero-Code Temperature Coefficient Code = 00 hex Full-Scale Error Code = FF hex Full-Scale Error Supply Rejection Code = FF hex, VDD = 2.7V to 3.6V Full-Scale Temperature Coefficient Code = FF hex ±10 LSB µV/°C ±30 mV 1 LSB ±10 µV/°C REFERENCE INPUTS Input Voltage Range 0 Input Resistance 322 Input Capacitance 460 VDD V 598 kΩ 10 pF Channel-to-Channel Isolation (Note 2) -60 dB AC Feedthrough (Note 3) -70 dB DAC OUTPUTS Output Voltage Range RL = open Load Regulation Code = FF hex, RL from 10kΩ to ∞ 2 0 _______________________________________________________________________________________ VREF V 0.25 LSB 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers (VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL 0.7VDD Input Current IIN VIN = 0V or VDD Input Capacitance CIN (Note 4) Output High Voltage VOH ISOURCE = TBDmA Output Low Voltage VOL ISINK = 1.6mA V 0.3VDD V ±1.0 µA 10 pF DIGITAL OUTPUTS VDD - 0.5 V 0.4 V DYNAMIC PERFORMANCE Voltage-Output Slew Rate CODE = FF hex 0.6 V/µs Output Settling Time To 1/2LSB, from code 00 to code FF hex (Note 5) 6 µs Digital Feedthrough and Crosstalk VREF = 0V, code 00 to code FF hex (Note 6) 5 nV-s Digital-to-Analog Glitch Impulse Code 80 hex to code 7F hex 50 nV-s VREF = 2.5Vp-p at 1kHz, VDD = 3V, code = FF hex -70 VREF = 2.5Vp-p at 10kHz -62 VREF = 0.5Vp-p, 3dB bandwidth 380 kHz 60 µVRMS Signal-to-Noise Plus Distortion Ratio SINAD Multiplying Bandwidth Wideband Amplifier Noise dB POWER SUPPLIES Power-Supply Voltage Supply Current VDD IDD 2.7 3.6 MAX533C/E 0.68 1.3 MAX533M 0.68 1.5 1 10 Shutdown Current V mA µA TIMING CHARACTERISTICS (VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.) PARAMETER SYMBOL VDD Rise to CS Fall Setup Time (Note 4) tVDCS LDAC Pulse Width Low tLDAC CS Rise to LDAC Fall Setup Time (Note 7) tCLL CLR Pulse Width Low tCLW CS Pulse Width High tCSW CONDITIONS MIN TYP MAX MAX533C/E 50 MAX533M 60 MAX533C/E 40 20 MAX533M 50 25 MAX533C/E 40 MAX533M 50 MAX533C/E 40 20 MAX533M 50 25 MAX533C/E 90 MAX533M 100 UNITS µs ns ns ns ns _______________________________________________________________________________________ 3 MAX533 ELECTRICAL CHARACTERISTICS (continued) MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers TIMING CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SERIAL-INTERFACE TIMING SCLK Clock Frequency (Note 8) fCLK SCLK Pulse Width High tCH SCLK Pulse Width Low tCL CS Fall to SCLK Rise Setup Time tCSS SCLK Rise to CS Rise Hold Time tCSH DIN to SCLK Rise to Setup Time tDS DIN to SCLK Rise to Hold Time tDH SCLK Rise to DOUT Valid Propagation Delay (Note 9) tDO1 SCLK Fall to DOUT Valid Propagation Delay (Note 10) tDO2 SCLK Rise to CS Fall Delay tCS0 CS Rise to SCLK Rise Setup Time tCS1 MAX533C/E 10 MAX533M 8.3 MAX533C/E 40 MAX533M 50 MAX533C/E 40 MAX533M 50 MAX533C/E 40 MAX533M 50 ns ns ns 0 MAX533C/E 40 MAX533M 50 ns 0 ns MAX533C/E 200 MAX533M 230 MAX533C/E 210 MAX533M 250 MAX533C/E 40 MAX533M 50 MAX533C/E 40 MAX533M 50 MHz ns ns ns ns Note 1: INL and DNL are measured with RL referenced to ground. Nonlinearity is measured from the first code that is greater than or equal to the maximum offset specification to code FF hex (full scale). See DAC Linearity and Voltage Offset section. Note 2: VREF = 2.5Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC’s code to FF hex and setting all other DAC’s codes to 00 hex. Note 3: VREF = 2.5Vp-p, 10kHz. DAC code = 00 hex. Note 4: Guaranteed by design, not production tested. Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of VOUT’s final value. Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC. Note 7: If LDAC is activated prior to CS’s rising edge, it must stay low for tLDAC or longer after CS goes high. Note 8: When DOUT is not used. If DOUT is used, fCLK max is 4MHz, due to the SCLK to DOUT propagation delay. Note 9: Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of VDD). Note 10: Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of VDD). 4 _______________________________________________________________________________________ 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers VDD = VREF = 3.0V 0.50 VDD = VREF = 5.0V 0.25 0 1 2 4 3 6 5 7 DAC CODE = FF HEX LOAD TO GND 3.5 3.0 400 DAC CODE = 00 HEX VDD = VREF = 3.0V 0 0 2 4 6 8 12 10 -55 -35 -15 5 25 45 65 85 105 125 DAC OUTPUT SOURCE CODE (mA) TEMPERATURE (°C) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = +3.0V) SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = +5.0V) 800 VDD = +5.0V 2 VDD = +3.0V 600 400 ALL DAC CODES = 00 HEX 200 25 45 0.5 1.0 1.5 2.0 3.0 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) TEMPERATURE (°C) REFERENCE VOLTAGE (V) THD + NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE THD + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY VDD = +3.0V VREF = SINE WAVE CENTERED AT 1.2V DAC C0DE = FF HEX 80kHz LOWPASS FILTER -60 VDD = +3.0V VREF = SINE WAVE CENTERED AT 1.2V DAC CODE = FF HEX 500kHz LOWPASS FILTER -30 VREF = 20kHz -50 -20 MAX533-TOC7 -30 -40 ALL DAC CODES = 00 HEX 400 0 0 65 85 105 125 THD + NOISE (dB) 5 THD + NOISE (dB) -55 -35 -15 600 200 0 0 ALL DAC CODES = FF HEX 800 ALL DAC CODES = FF HEX SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 3 1000 MAX533-TOC5 MAX533-TOC4 1000 3 -40 VREF = 2Vp-p -50 VREF = 1VP-P VREF = 1kHz -60 -70 VREF = 0.5Vp-p -70 0 0.5 1.0 MAX533-TOC3 VDD = +3.0V VREF = +2.5V 200 2.5 8 VDD = +5.0V VREF = +4.5V 600 DAC OUTPUT SINK CURRENT (mA) 5 SHUTDOWN SUPPLY CURRENT (µA) 4.0 2.0 0 1 DAC CODE = FF HEX 800 1.5 REFERENCE AMPLITUDE (Vp-p) MAX533-TOC8 0.75 1000 MAX533-TOC6 1.00 VDD = VREF = 5.0V 4.5 SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (µA) DAC FULL-SCALE OUTPUT VOLTAGE (V) DAC CODE = 00 HEX LOAD TO VDD 1.25 5.0 MAX533-TOC1 DAC ZERO-CODE OUTPUT VOLTAGE (V) 1.50 DAC FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT MAX533-TOC2 DAC ZERO-CODE OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT 2.0 1 0.1 1 10 100 FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX533 __________________________________________Typical Operating Characteristics (VDD = +3V, TA = +25°C, unless otherwise noted.) ____________________________Typical Operating Characteristics (continued) (VDD = +3V, TA = +25°C, unless otherwise noted.) REFERENCE INPUT FREQUENCY RESPONSE REFERENCE FEEDTHROUGH vs. FREQUENCY -5 -10 -15 -20 VREF = 0.1Vp-p SINE WAVE CENTERED AT 2.5V DAC CODE = FF HEX VDD = +3.0V -25 -30 RELATIVE OUTPUT (dB) 0 MAX533-TOC12 -20 MAX533-TOC9 5 RELATIVE OUTPUT (dB) MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers VDD = +3.0V VREF = 3Vp-p SINE WAVE DAC CODE = 00 HEX -40 -50 -60 -70 -30 -80 0.01 0.1 10 1 0.01 0.1 FREQUENCY (MHz) 10 1 FREQUENCY (MHz) WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE) WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE) MAX533-TOC11 MAX533-TOC10 CS 2V/div CS 2V/div OUTA 50mV/div OUTA 50mV/div 2µs/div VDD = 3.0V VREF = 2.5V 2µs/div DAC CODE = 80 TO 7F hex NO LOAD VDD = 3.0V VREF = 2.5V CLOCK FEEDTHROUGH DAC CODE = 7F TO 80 hex NO LOAD POSITIVE SETTLING TIME MAX533-TOC13 MAX533-TOC14 SCLK 2V/div CS 2V/div OUTA 1V/div OUTA 10mV/div 2µs/div SCLK = 333kHz SCLK tR = tF = 25ns VDD = 3.0V 6 5µs/div VREF = 2.5V DAC CODE = 80 hex NO LOAD VDD = 3.0V VREF = 2.5V DAC CODE = 00 TO FF hex NO LOAD _______________________________________________________________________________________ 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers POSITIVE SETTLING TIME NEGATIVE SETTLING TIME MAX533-TOC15 MAX533-TOC16 CS 2V/div CS 2V/div OUTA 1V/div OUTA 1V/div 5µs/div VDD = 3.0V VREF = 2.5V 5µs/div VDD = 3.0V VREF = 2.5V DAC CODE = 01 TO FF hex NO LOAD DAC CODE = FF TO 00 hex NO LOAD ______________________________________________________________Pin Description PIN NAME 1 OUTB DAC B Voltage Output FUNCTION 2 OUTA DAC A Voltage Output 3 REF Reference-Voltage Input 4 UPO Software-Programmable Logic Output 5 PDE Power-Down Enable. Must be high to enter software shutdown mode. 6 LDAC Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents of each input latch to its respective DAC latch. 7 CLR Clear DAC Input (active low). Driving CLR low asynchronously clears the input and DAC registers, and sets all DAC outputs to zero. 8 DOUT Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the rising or falling edge of SCLK (Table 1). 9 CS Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are executed when CS returns high. 10 SCLK Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling (default) or rising edge (A0 = A1 = 1, see Table 1). 11 DIN 12 DGND Serial Data Input. Data is clocked in on the rising edge of SCLK. 13 VDD 14 AGND Analog Ground 15 OUTD DAC D Voltage Output 16 OUTC DAC C Voltage Output Digital Ground Power Supply, +2.7V to +3.6V _______________________________________________________________________________________ 7 MAX533 ____________________________Typical Operating Characteristics (continued) (VDD = +3V, TA = +25°C, unless otherwise noted.) MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers INSTRUCTION EXECUTED CS ••• ••• SCLK ••• DIN A1 A0 C1 C0 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 MSB D7 D6 D5 D4 D3 D2 LSB MSB DACA LSB DACD ••• DOUT MODE 1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 DATA FROM PREVIOUS DATA INPUT DOUT MODE 0 (DEFAULT) D6 D5 D4 D3 D2 D1 D0 D7 A1 DATA FROM PREVIOUS DATA INPUT ••• A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 D6 D5 D4 D3 D2 D1 D0 D7 Figure 1. 3-Wire Interface Timing CS tCSW tCS0 tCSS tCH tCSH tCP tCS1 tCL SCLK tDS tDH DIN tD02 tD01 DOUT tCLL LDAC Figure 2. Detailed Serial-Interface Timing Diagram 8 D1 D0 _______________________________________________________________________________________ tLDAC A1 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers Serial Interface At power-on, the serial interface and all digital-toanalog converters (DACs) are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK's falling edge. The MAX533 communicates with microprocessors through a synchronous, full-duplex, 3-wire interface (Figure 1). Data is sent MSB first and can be transmitted in one 4-bit and one 8-bit (byte) packet or in one 12-bit word. If a 16-bit word is used, the first four bits are ignored. A 4-wire interface adds a line for LDAC and allows asynchronous updating. The serial clock (SCLK) synchronizes the data transfer. Data is transmitted and received simultaneously. Figure 2 shows the detailed serial-interface timing. Please note that the clock should be low if it is stopped between updates. DOUT does not go into a highimpedance state if the clock idles or CS is high. Serial data is clocked into the data registers in MSB-first format, with the address and configuration information preceding the actual DAC data. Data is clocked in on SCLK’s rising edge while CS is low. Data at DOUT is clocked out 12 clock cycles later, either at SCLK’s falling edge (default or mode 0) or rising edge (mode 1). Chip select (CS) must be low to enable the DAC. If CS is high, the interface is disabled and DOUT remains unchanged. CS must go low at least 40ns before the first rising edge of the clock pulse to properly clock in the first bit. With CS low, data is clocked into the MAX533’s internal shift register on the rising edge of the external serial clock. Always clock in the full 12 bits because each time CS goes high the bits currently in the input shift register are interpreted as a command. SCLK can be driven at rates up to 10MHz. Serial Input Data Format and Control Codes The 12-bit serial input format shown in Figure 3 comprises two DAC address bits (A1, A0), two control bits (C1, C0), and eight bits of data (D7...D0). The 4-bit address/control code configures the DAC as shown in Table 1. Load Input Register, DAC Registers Unchanged (Single Update Operation) A1 A0 Address C1 0 C0 1 D7 D6 D5 D4 D3 D2 8-Bit Data D1 D0 (LDAC = H) When performing a single update operation, A1 and A0 select the respective input register. At the rising edge of CS, the selected input register is loaded with the current shift-register data. All DAC outputs remain unchanged. This preloads individual data in the input register without changing the DAC outputs. Load Input and DAC Registers A1 A0 Address C1 1 C0 1 D7 D6 D5 D4 D3 D2 8-Bit Data D1 D0 (LDAC = H) This command directly loads the selected DAC register at CS’s rising edge. A1 and A0 set the DAC address. Current shift-register data is placed in the selected input and DAC registers. For example, to load all four DAC registers simultaneously with individual settings (DAC A = 0.5V, DAC B = 1V, DAC C = 1.5V, and DAC D = 2V), four commands are required. First, perform three single input register update operations for DACs A, B, and C (C1 = 0). The final command loads input register D and updates all four DAC registers from their respective input registers. Software “LDAC ” Command THIS IS THE FIRST BIT SHIFTED IN MSB DOUT A1 A0 C1 C0 D7 D6 CONTROL AND ADDRESS BITS ... LSB D1 D0 8-BIT DAC DATA DIN A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 x x x x x x x x (LDAC = 1) All DAC registers are updated with the contents of their respective input registers at CS’s rising edge. With the exception of using CS to execute, this performs the same function as the asynchronous LDAC. Figure 3. Serial Input Format _______________________________________________________________________________________ 9 MAX533 _______________Detailed Description MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers 12-BIT SERIAL WORD A1 A0 C1 C0 D7 . . . . . . . . D0 LDAC 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 1 1 1 1 Load input register A; all DAC outputs unchanged. Load input register B; all DAC outputs unchanged. Load input register C; all DAC outputs unchanged. Load input register D; all DAC outputs unchanged. 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 1 1 1 1 Load input register A; all DAC outputs updated Load input register B; all DAC outputs updated Load input register C; all DAC outputs updated Load input register D; all DAC outputs updated. 0 1 0 0 XXXXXXXX 1 Software LDAC commands. Update all DACs from their respective input registers. Also bring the part out of shutdown mode. 1 0 0 0 8-bit DAC data X Load all DACs with shift-register data. Also bring the part out of shutdown mode. 1 1 0 0 XXXXXXXX X Software shutdown (provided PDE is high) 0 0 1 0 XXXXXXXX X UPO goes low. 0 1 1 0 XXXXXXXX X UPO goes high. 0 0 0 0 XXXXXXXX X No operation (NOP); shift data in shift registers. 1 1 1 0 XXXXXXXX X Set DOUT phase—SCLK rising (mode 1). DOUT clocked out on rising edge of SCLK. All DACs updated from their respective input registers. 1 0 1 0 XXXXXXXX X Set DOUT phase—SCLK falling (mode 0). DOUT clocked out on falling edge of SCLK. All DACs updated from their respective registers (default). FUNCTION Load All DACs with Shift-Register Data A1 1 A0 0 C1 0 C0 0 D7 D6 D5 D4 D3 D2 8-Bit Data D1 D0 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 (LDAC = X) All four DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog value within the reference range. This command can be used to substitute CLR if code 00 hex is programmed, which clears all DACs. Software Shutdown A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 x x x x x x x x (LDAC = X, PDE = H) Shuts down all output buffer amplifiers, reducing supply current to 10µA max. 10 User-Programmable Output (UPO) 0 1 1 1 0 0 x x x x x x x x x x x x x x x x UPO Output Low High (LDAC = X) User-programmable logic output for controlling another device across an isolated interface. Example devices are gain control of an amplifier, a 4mA to 20mA amplifier, and a polarity output for a motor speed control. No Operation (NOP) A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 x x x x x x x x (LDAC = X) The NOP command (no operation) allows data to be shifted through the MAX533 shift register without affecting the input or DAC registers. This is useful in daisy chaining (also see the Daisy Chaining Devices section). ______________________________________________________________________________________ 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers Set DOUT Phase—SCLK Rising (Mode 1) A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 x x x x x x x x Serial Data Output DOUT is the internal shift register’s output. DOUT can be programmed to clock out data on SCLK’s falling edge (mode 0) or rising edge (mode 1). In mode 0, output data lags input data by 12.5 clock cycles, maintaining compatibility with Microwire and SPI. In mode 1, output data lags input data by 12 clock cycles. On power-up, DOUT defaults to mode 0 timing. DOUT never three-states; it always actively drives either high or low and remains unchanged when CS is high. (LDAC = x) Mode 1 resets the serial-output DOUT to transition at SCLK’s rising edge. Once this command is issued, DOUT’s phase is latched and will not change except on power-up or if the specific command to set the phase to falling edge is issued. This command also loads all DAC registers with the contents of their respective input registers, and is identical to the “LDAC” command. SCLK SK MAX533 DIN SO MICROWIRE PORT CS I/0 Set DOUT Phase—SCLK Falling (Mode 0, Default) A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 x x x x x x x x (LDAC = x) This command resets DOUT to transition at SCLK’s falling edge. The same command also updates all DAC registers with the contents of their respective input registers, identical to the “LDAC” command. LDAC Operation (Hardware) LDAC is typically used in 4-wire interfaces (Figure 7). This command is level sensitive, and it allows asynchronous hardware control of the DAC outputs. With LDAC low, the DAC registers are transparent, and any time an input register is updated, the DAC output immediately follows. Clear DACs with CLR Strobing the CLR pin low causes an asynchronous clear of input and DAC registers and sets all DAC outputs to zero. Similar to the LDAC pin, CLR can be invoked at any time, typically when the device is not selected (CS = H). When the DAC data is all zeros, this function is equivalent to the “Update all DACs from Shift Registers” command. Figure 4. Connections for Microwire MAX533 DIN SCLK CS MOSI SPI/QSPI PORT SCK I/0 CPOL = 0, CPHA = 0 Figure 5. Connections for SPI/QSPI ______________________________________________________________________________________ 11 MAX533 For this command, the data bits are “Don't Cares.” As an example, three MAX533s are daisy chained (A, B, and C), and devices A and C need to be updated. The 36-bit-wide command would consist of one 12-bit word for device C, followed by an NOP instruction for device B and a third 12-bit word with data for device A. At CS’s rising edge, device B will not change state. MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers Interfacing to the Microprocessor The MAX533 is Microwire™ and SPI™/QSPI™ compatible. For SPI and QSPI, clear the CPOL and CPHA configuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA = 1 configuration can also be used if the DOUT output is ignored. The MAX533 can interface with Intel’s 80C5X/80C3X family in mode 0 if the SCLK clock polarity is inverted. More universally, if a serial port is not available, three lines from one of the parallel ports can be used for bit manipulation. Digital feedthrough at the voltage outputs is greatly minimized by operating the serial clock only to update the registers. Also see the Clock Feedthrough photo in the Typical Operating Characteristics section. The clock idle state is low. Daisy-Chaining Devices Any number of MAX533s can be daisy-chained by connecting DOUT of one device to DIN of the following device in the chain. The NOP instruction (Table 1) allows data to be passed from DIN to DOUT without changing the input or DAC registers of the passing device. A 3-wire interface updates daisy-chained or individual MAX533s simultaneously by bringing CS high (Figure 6). Analog Section DAC Operation The MAX533 uses a matrix decoding architecture for the DACs, which saves power in the overall system. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor string presents a code-independent input impedance to the reference and guarantees a monotonic output. Figure 8 shows a simplified diagram of the four DACs. Reference Input The voltage at REF sets the full-scale output voltage for all four DACs. The 460kΩ typical input impedance at REF is code independent. The output voltage for any DAC can be represented by a digitally programmable voltage source as follows: VOUT = (NB x VREF) / 256 where NB is the numerical value of the DAC’s binary input code. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. MAX533 MAX533 SCLK SCLK DIN DIN CS CS SCLK DOUT SCLK DIN DIN CS CS DOUT CS DEVICE A SCLK DIN MAX533 SCLK DIN DOUT CS DEVICE B DEVICE C TO OTHER SERIAL DEVICES MAX533 Figure 6. Daisy-chained or individual MAX533s are simultaneously updated by bringing CS high. Only three wires are required. 12 ______________________________________________________________________________________ 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX533 DIN SCLK LDAC CS1 TO OTHER SERIAL DEVICES CS2 CS3 CS CS CS LDAC MAX533 LDAC MAX533 LDAC MAX533 SCLK SCLK SCLK DIN DIN DIN Figure 7. Multiple MAX533s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an individual CS. Output Buffer Amplifiers All MAX533 voltage outputs are internally buffered by precision unity-gain followers that slew at about 0.6V/µs. The outputs can swing from GND to VDD. With a 0V to +2.5V (or +2.5V to 0V) output transition, the amplifier outputs will typically settle to 1/2LSB in 6µs when loaded with 10kΩ in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive (≥10kΩ) or capacitive loads. __________Applications Information DAC Linearity and Voltage Offset The output buffer can have a negative input offset voltage that would normally drive the output negative, but since there is no negative supply the output stays at 0V (Figure 9). When linearity is determined using the endpoint method, it is measured between zero code (all inputs 0) and full-scale code (all inputs 1) after offset and gain error are calibrated out. However, in singlesupply operation the next code after zero may not change the output (Figure 9), so the lowest code that produces a positive output is the lower endpoint. ______________________________________________________________________________________ 13 REF R0 R1 R15 D7 R16 D6 D5 MSB DECODER MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers OUTPUT VOLTAGE D4 R255 0V DAC CODE NEGATIVE OFFSET LSB DECODER D3 D2 D1 D0 DAC A Figure 8. DAC Simplified Circuit Diagram Power Sequencing The voltage applied to REF should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REF and VDD to ensure compliance with the absolute maximum ratings. Do not apply signals to the digital inputs before the device is fully powered up. Power-Supply Bypassing and Ground Management Connect AGND and DGND together at the IC. This ground should then return to the highest-quality ground available. Bypass VDD with a 0.1µF capacitor, located as close to VDD and DGND as possible. Careful PC board layout minimizes crosstalk among DAC outputs and digital inputs. Figure 10 shows suggested circuit board layout to minimize crosstalk. Unipolar-Output, Two-Quadrant Multiplication In unipolar operation, the output voltages and the reference input are the same polarity. Figure 11 shows the MAX533 unipolar configuration, and Table 2 shows the unipolar code. 14 Figure 9. Effect of Negative Offset (Single Supply) Table 2. Unipolar Code Table DAC CONTENTS ANALOG OUTPUT MSB LSB 1111 1111 255 +VREF –––– 256 1000 0001 129 +VREF –––– 256 1000 0000 128 = +V–REF ––– +VREF –––– 256 2 0111 1111 127 +VREF –––– 256 0000 0001 1 +VREF –––– 256 0000 0000 0V ( ) ( ) ( ) ( ( 1 ) Note: 1LSB = (VREF) (2-8) = +VREF (–––– 256 ______________________________________________________________________________________ ) ) 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers +3V 13 VDD MAX533 2 DAC A SYSTEM GND OUTC OUTB OUTD OUTA 1 OUTB DAC B SERIAL INTERFACE NOT SHOWN REF AGND OUTA 16 DAC C OUTC 15 DAC D OUTD DGND 12 AGND 14 Figure 10. Suggested PC Board Layout for Minimizing Crosstalk (Bottom View) Figure 11. Unipolar Output Circuit _________________________________________________________Functional Diagram DOUT CLR LDAC UPO PDE DECODE CONTROL VDD REF DGND AGND MAX533 OUTA INPUT REGISTER A DAC REGISTER A DAC A INPUT REGISTER B DAC REGISTER B DAC B INPUT REGISTER C DAC REGISTER C DAC C INPUT REGISTER D DAC REGISTER D DAC D OUTB 12-BIT SHIFT REGISTER OUTC OUTD SR CONTROL CS DIN SCLK ______________________________________________________________________________________ 15 MAX533 REFERENCE INPUT 3 REFAB 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX533 ___________________Chip Information TRANSISTOR COUNT: 6821 ________________________________________________________Package Information DIM A A1 A2 B C D E e H h L N S α D A e A1 B S E INCHES MILLIMETERS MAX MIN MIN MAX 0.068 0.061 1.55 1.73 0.004 0.0098 0.127 0.25 0.061 0.055 1.40 1.55 0.012 0.008 0.20 0.31 0.0075 0.0098 0.19 0.25 SEE VARIATIONS 0.157 0.150 3.81 3.99 0.25 BSC 0.635 BSC 0.244 0.230 5.84 6.20 0.016 0.010 0.25 0.41 0.035 0.016 0.41 0.89 SEE VARIATIONS SEE VARIATIONS 8° 0° 0° 8° H h x 45° α A2 N E C DIM PINS D S D S D S D S 16 16 20 20 24 24 28 28 INCHES MILLIMETERS MIN MAX MIN MAX 0.189 0.196 4.80 4.98 0.0020 0.0070 0.05 0.18 0.337 0.344 8.56 8.74 0.0500 0.0550 1.27 1.40 0.337 0.344 8.56 8.74 0.0250 0.0300 0.64 0.76 0.386 0.393 9.80 9.98 0.0250 0.0300 0.64 0.76 21-0055A QSOP QUARTER SMALL-OUTLINE PACKAGE L Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.