19-4368; Rev 0; 11/08 Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface Features The MAX5500/MAX5501 integrate four low-power, 12-bit digital-to analog converters (DACs) and four precision output amplifiers in a small, 20-pin package. Each negative input of the four precision amplifiers is externally accessible providing flexibility in gain configurations, remote sensing, and high output drive capacity, making the MAX5500/MAX5501 ideal for industrial-process-control applications. Other features include software shutdown, hardware shutdown lockout, an active-low reset which clears all registers and DACs to zero, a user-programmable logic output, and a serial-data output. Each DAC provides a double-buffered input organized as an input register followed by a DAC register. A 16-bit serial word loads data into each input register. The serial interface is compatible with SPI™/QSPI™/ MICROWIRE™. The serial interface allows the input and DAC registers to be updated independently or simultaneously with a single software command. The 3-wire interface simultaneously updates the DAC registers. All logic inputs are TTL/CMOS-logic compatible. The MAX5500 operates from a single +5V power supply, and the MAX5501 operates from a single +3V power supply. The MAX5500/MAX5501 are specified over the extended -40°C to +105°C temperature range. ♦ Four 12-Bit DACs with Configurable Output Amplifiers ♦ +5V or +3V Single-Supply Operation ♦ Low Supply Current: 0.85mA Normal Operation 10µA Shutdown Mode (MAX5500) ♦ Force-Sense Outputs ♦ Power-On Reset Clears All Registers and DACs to Zero ♦ Capable of Recalling Last State Prior to Shutdown ♦ SPI/QSPI/MICROWIRE Compatible ♦ Simultaneous or Independent Control of DACs through 3-Wire Serial Interface ♦ User-Programmable Digital Output ♦ Guaranteed Over Extended Temperature Range (-40°C to +105°C) Ordering Information PINPACKAGE PART Applications Industrial Process Controls Automatic Test Equipment Microprocessor (µP)-Controlled Systems Motion Control Digital Offset and Gain Adjustment Remote Industrial Controls INL (LSB) SUPPLY (V) MAX5500AGAP+ 20 SSOP ±0.75 +5 MAX5500BGAP+ 20 SSOP ±2 +5 MAX5501AGAP+* 20 SSOP ±0.75 +3 MAX5501BGAP+* 20 SSOP ±2 +3 +Denotes a lead-free/RoHS-compliant package. *Future product—contact factory for availability. Note: All devices are specified over the -40°C to +105°C operating temperature range. Pin Configuration appears at end of data sheet. Functional Diagram DOUT CL PDL DGND AGND VDD REFAB MAX5500 MAX5501 DECODE CONTROL 16-BIT SHIFT REGISTER SR CONTROL LOGIC OUTPUT CS DIN SCLK UPO SPI/QSPI are trademarks of Motorola, Inc. INPUT REGISTER A DAC REGISTER A DAC A INPUT REGISTER B DAC REGISTER B DAC B INPUT REGISTER C DAC REGISTER C DAC C INPUT REGISTER D DAC REGISTER D DAC D FBA OUTA FBB OUTB FBC OUTC FBD OUTD REFCD MICROWIRE is a trademark of National Semiconductor, Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5500/MAX5501 General Description MAX5500/MAX5501 Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface ABSOLUTE MAXIMUM RATINGS VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V REFAB, REFCD to AGND ...........................-0.3V to (VDD + 0.3V) OUT_, FB_ to AGND...................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND.............................................-0.3V to +6V DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V) Continuous Current into Any Pin.......................................±20mA Continuous Power Dissipation (TA = +70°C) 20-Pin SSOP (derate 8.00mW/°C above +70°C) .........640mW Operating Temperature Range .........................-40°C to +105°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (MAX5500 (VDD = +5V ±10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V ±10%, VREFAB = VREFCD = 1.5V), VAGND = VDGND = 0, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C. Output buffer connected in unitygain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX ±0.25 ±0.75 UNITS STATIC PERFORMANCE (Analog Section) Resolution N Integral Nonlinearity (Note 1) INL Differential Nonlinearity DNL Offset Error VOS 12 MAX5500A/MAX5501A ±2.0 Guaranteed monotonic ±1.0 LSB ±3.5 mV (Note 1) -0.3 Gain-Error Tempco Power-Supply Rejection Ratio ppm/ oC 6 GE LSB MAX5500B/MAX5501B Offset-Error Tempco Gain Error Bits ±2.0 PSRR LSB ppm/ oC 1 100 600 µV/V -0.3 ±2.0 LSB MATCHING PERFORMANCE (TA = +25oC) Gain Error GE Offset Error VOS Integral Nonlinearity INL (Note 1) ±1.0 ±3.5 mV ±0.35 ±1.0 LSB VDD - 1.4 V REFERENCE INPUT Reference Input Range VREF Reference Input Resistance RREF 0 Code-dependent, minimum at code 555H 8 Reference Current in Shutdown kΩ 0.01 ±1.0 µA DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIN Input Capacitance CIN 2 MAX5500A/MAX5500B 2.4 MAX5501A/MAX5501B 2.0 VIN = 0 or VDD V ±0.1 8 _______________________________________________________________________________________ 0.8 V ±1.0 µA pF Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface (MAX5500 (VDD = +5V ±10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V ±10%, VREFAB = VREFCD = 1.5V), VAGND = VDGND = 0, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C. Output buffer connected in unitygain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.13 0.4 V DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA VDD - 0.5 V DYNAMIC PERFORMANCE Voltage Output Slew Rate SR 0.6 To ±0.5 LSB, VSTEP = 2.5V MAX5500A/MAX5500B 12 To ±0.5 LSB, VSTEP = 2.5V MAX5501A/MAX5501B 16 V/µs Output Settling Time µs Output Voltage Swing Rail-to-rail (Note 2) 0 to VDD Current into FB_ V 0 0.1 µA ±0.01 ±1.0 µA OUT_ Leakage Current in Shutdown RL = ∞ Startup Time Exiting Shutdown Mode MAX5500A/MAX5500B 15 MAX5501A/MAX5501B 20 Digital Feedthrough CS =VDD, fIN = 100kHz 5 nV•s 5 nV•s Digital Crosstalk µs POWER SUPPLIES Supply Voltage VDD Supply Current IDD MAX5500A/MAX5500B 4.5 5.5 MAX5501A/MAX5501B 3.0 3.6 V (Note 3) 0.85 1.1 mA Supply Current in Shutdown (Note 3) 10 20 µA Reference Current in Shutdown (Note 3) 10 20 µA TIMING CHARACTERISTICS (Figure 6) SCLK Clock Period tCP 100 ns SCLK Pulse-Width High tCH 40 ns SCLK Pulse-Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns DIN Setup Time tDS 40 ns DIN Hold Time tDH 0 ns _______________________________________________________________________________________ 3 MAX5500/MAX5501 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (MAX5500 (VDD = +5V ±10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V ±10%, VREFAB = VREFCD = 1.5V), VAGND = VDGND = 0, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C. Output buffer connected in unitygain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLOAD = 200pF 80 ns CLOAD = 200pF 80 ns SCLK Rise to DOUT Valid Propagation Delay tD01 SCLK Fall to DOUT Valid Propagation Delay tD02 SCLK Rise to CS Fall Delay tCS0 40 ns CS Rise to SCLK Rise Hold Time tCS1 40 ns CS Pulse-Width High tCSW 100 ns Note 1: Guaranteed from code 11 to code 4095 in unity-gain configuration. Note 2: Accuracy is better than 1.0 LSB for VOUT = 6mV to (VDD - 60mV), guaranteed by PSR test on endpoints. Note 3: RL = ∞, digital inputs at DGND or VDD. Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) 0 MAX5501 VDD = 3V RL = 5kΩ 0 910 900 MAX5500 toc03 MAX5500 VDD = 5V RL = 5kΩ MAX5500 toc02 0.2 SUPPLY CURRENT vs. TEMPERATURE INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE MAX5500 toc01 INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE MAX5500 VDD = 5V -0.2 890 -0.4 -0.4 -0.6 -0.6 880 870 -0.8 -0.8 860 -1.0 -1.0 850 0.4 1.2 2.0 2.8 REFERENCE VOLTAGE (V) 4 IDD (µA) INL (LSB) -0.2 INL (LSB) MAX5500/MAX5501 Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface 3.6 4.4 CODE = FFF hex 0.4 0.9 1.4 1.9 REFERENCE VOLTAGE (V) 2.4 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) _______________________________________________________________________________________ Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500 toc06 810 MAX5500 VDD = 5V -1 0 MAX5500 toc05 MAX5501 VDD = 3V 820 0 MAX5500 toc04 830 FULL-SCALE ERROR vs. LOAD FULL-SCALE ERROR vs. LOAD SUPPLY CURRENT vs. TEMPERATURE MAX5501 VDD = 3V -1 780 -2 INL (LSB) 790 INL (LSB) IDD (µA) 800 -3 770 -2 -3 760 CODE = FFF hex 0.01 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 1 10 100 0.01 0.1 1 10 100 LOAD (kΩ) LOAD (kΩ) SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE ANALOG CROSSTALK 5V MAX5500 VDD = 5V MAX5500 toc09 798 MAX5501 VDD = 3V 796 900 OUTA 1V/div 794 IDD (µA) 880 IDD (µA) 0.1 TEMPERATURE (°C) MAX5500 toc07 920 -5 -5 730 MAX5500 toc08 740 940 -4 -4 750 MAX5500/MAX5501 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) 860 840 792 790 788 820 OUTB AC-COUPLED 10mV/div 786 800 784 780 CODE = FFF hex CODE = FFF hex 760 782 4.50 4.75 5.00 5.25 5.50 3.0 3.1 3.2 VDD (V) 3.3 VDD (V) 3.4 3.5 3.6 10µs/div VREF = 2.5V, RL = 5kΩ, CL = 100pF DACA CODE SWITCHING FROM 00C hex TO FCC hex DACB CODE SET TO 800 hex DYNAMIC RESPONSE 5V ANALOG CROSSTALK 3V MAX5500 toc11 MAX5500 toc10 OUTA 0.5V/div OUTA 1V/div OUTB AC-COUPLED 50mV/div 10µs/div VREF = 1.5V, RL = 5kΩ, CL = 100pF DACA CODE SWITCHING FROM 00C hex TO FFF hex DACB CODE SET TO 800 hex 10µs/div VREF = 2.5V, RL = 5kΩ, CL = 100pF SWITCHING FROM CODE 000 hex TO FB4 hex OUTPUT AMPLIFIER GAIN = +2 _______________________________________________________________________________________ 5 MAX5500/MAX5501 Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) DIGITAL FEEDTHROUGH 5V (SCLK = 100kHz) DIGITAL FEEDTHROUGH 3V (SCLK = 100kHz) DYNAMIC RESPONSE 3V MAX5500 toc12 MAX5500 toc14 MAX5500 toc13 OUTA 0.5V/div SCLK 2V/div SCLK 1V/div OUTA AC-COUPLED 10mV/div OUTA AC-COUPLED 10mV/div 10µs/div VREF = 1.5V, RL = 5kΩ, CL = 100pF SWITCHING FROM CODE 000 hex TO FB4 hex OUTPUT AMPLIFIER GAIN = +1 2µs/div VREF = 2.5V, RL = 5kΩ, CL = 100pF VCS = VPDL = VCL = 5V, VDIN = 0V DACA CODE SET TO 800 hex 4µs/div VREF = 1.5V, RL = 5kΩ, CL = 100pF VCS = VPDL = VCL = 3.3V, VDIN = 0V DACA CODE SET TO 800 hex Pin Description PIN NAME 1 AGND 2 FBA 3 OUTA 4 OUTB 5 FBB 6 REFAB Analog Ground DAC A Output Amplifier Feedback DAC A Output Voltage DAC B Output Voltage DAC B Output Amplifier Feedback DAC A/DAC B Reference Voltage Input CL Active-Low Clear Input. CL clears all DACs and registers. CL resets all outputs (OUT_, UPO, and DOUT) to 0. 8 CS Active-Low Chip-Select Input 9 DIN Serial Data Input 10 SCLK Serial Clock Input 11 DGND Digital Ground 12 DOUT Serial Data Output 13 UPO User-Programmable Logic Output 14 PDL Active-Low Power-Down Lockout. Drive PDL low to lock out software shutdown. 15 REFCD 16 FBC 17 OUTC 18 OUTD 19 FBD DAC D Output Amplifier Feedback 20 VDD Positive Power Supply 7 6 FUNCTION DAC C/DAC D Reference Voltage Input DAC C Output Amplifier Feedback DAC C Output Voltage DAC D Output Voltage _______________________________________________________________________________________ Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface The MAX5500/MAX5501 integrate four 12-bit, voltageoutput digital-to-analog converters (DACs) that are addressed through a simple 3-wire serial interface. The devices include a 16-bit data-in/data-out shift register. Each internal DAC provides a doubled-buffered input composed of an input register and a DAC register (see the Functional Diagram). The negative input of each amplifier is externally accessible. The DACs are inverted rail-to-rail ladder networks that convert 12-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage inputs. DACs A and B share the REFAB input, while DACs C and D share the REFCD input. The two reference inputs allow different full-scale output voltage ranges for each pair of DACs. Figure 1 shows a simplified circuit diagram of one of the four DACs. Reference Inputs The two reference inputs accept positive DC and AC signals. The voltage at each reference input sets the full-scale output voltage for the two corresponding DACs. The reference input voltage range is 0V to (VDD - 1.4V). The output voltages (VOUT_) are represented by a digitally programmable voltage source as: VOUT_ = (VREF x NB/4096) x Gain where NB is the numeric value of the binary input code (0 to 4095) of the DAC. VREF is the reference voltage. Gain is the externally set voltage gain. The impedance at each reference input is code-dependent, ranging from a low value of 10kΩ when both DACs connected to the reference accept an input code FB_ R 2R R 2R 2R D0 D9 OUT_ R 2R D10 REF_ AGND SHOWN FOR ALL 1s ON DAC 2R D11 of 555 hex, to a high value exceeding giga-ohms with an input code of 000 hex. The load regulation of the reference source affects the performance of the devices as the input impedance at the reference inputs is code dependent. The REFAB and REFCD reference inputs provide a 10kΩ guaranteed minimum input impedance. When the same voltage source drives the two reference inputs, the effective minimum impedance is 5kΩ. A voltage reference with an excellent load regulation of 0.0002mV/mA, such as the MAX6033, is capable of driving both reference inputs simultaneously at 2.5V. Driving REFAB and REFCD separately improves reference accuracy. The REFAB and REFCD inputs enter a high-impedance state, with a typical input leakage current of 0.02µA, when the MAX5500/MAX5501 are in shutdown. The reference input capacitance is also code dependent and typically ranges from 20pF with an input code of all 0s to 100pF with an input code of all 1s. Output Amplifiers All DAC outputs are internally buffered by precision amplifiers with a typical slew rate of 0.6V/µs. Access to the inverting input of each output amplifier provides the greater flexibility in output gain setting/signal conditioning (see the Applications Information section). With a full-scale transition at the output, the typical settling time to within ±0.5 LSB is 12µs when the output is loaded with 5kΩ in parallel with 100pF. A load of less than 2kΩ at the output degrades performance. See the Typical Operating Characteristics for the output dynamic responses and settling performances of the amplifiers. Power-Down Mode The MAX5500/MAX5501 feature a software-programmable shutdown that reduces supply current to a typical value of 10µA. Drive PDL high to enable the shutdown mode. Write 1100XXXXXXXXXXXX as the input-control word to put the device in power-down mode (Table 1). In power-down mode, the output amplifiers and the reference inputs enter a high-impedance state. The serial interface remains active. Data in the input registers is retained in power-down, allowing the devices to recall the output states prior to entering shutdown. Start up from power-down either by recalling the previous configuration or by updating the DACs with new data. Allow 15µs for the outputs to stabilize when powering up the devices or bringing the devices out of shutdown. Figure 1. Simplified DAC Circuit Diagram _______________________________________________________________________________________ 7 MAX5500/MAX5501 Detailed Description MAX5500/MAX5501 Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface Serial-Interface Configurations The MAX5500/MAX5501s’ 3-wire serial interface is compatible with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3). The serial input word consists of two address bits and two control bits followed by 12 data bits (MSB first), as shown in Figure 4. The 4-bit address/control code determines the MAX5500/ MAX5501s’ response outlined in Table 1. The connection between DOUT and the serial-interface port is not necessary, but may be used for data echo. Data held in the shift register can be shifted out of DOUT and returned to the µP for data verification. The digital inputs of the MAX5500/MAX5501 are double buffered. Depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all four DAC registers can be updated simultaneously from the input registers (Table 1). bits (C1, C0), followed by the 12 data bits D11–D0 (Figure 4). The 4-bit address/control code determines: • The register(s) to be updated • The clock edge on which data is to be clocked out through the serial-data output (DOUT) • The state of the user-programmable logic output (UPO) • If the device is to enter shutdown mode (assuming PDL is high) • How the device is configured when exiting out of shutdown mode +5V Serial-Interface Description DOUT* The MAX5500/MAX5501 require 16 bits of serial data. Table 1 lists the serial-interface programming commands. For certain commands, the 12 data bits are don’t-care bits. Data is sent MSB first and can be sent in two 8-bit packets or one 16-bit word (CS must remain low until 16 bits are transferred). The serial data is composed of two DAC address bits (A1, A0) and two control MISO* DIN MAX5500 MAX5501 MOSI SCLK SCK CS SCLK SS SPI/QSPI PORT I/O CPOL = 0, CPHA = 0 SK *THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5500/MAX5501, BUT CAN BE USED FOR READBACK PURPOSES. MAX5500 MAX5501 DIN SO DOUT* SI* CS I/O Figure 3. Connections for SPI/QSPI MICROWIRE PORT MSB.................................................................................................................................LSB 16 BITS OF SERIAL DATA ADDRESS CONTROL DATA BITS MSB...........................................................................................LSB BITS BITS *THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5500/MAX5501, BUT CAN BE USED FOR READBACK PURPOSES. Figure 2. Connections for MICROWIRE 8 A1 A0 C1 C0 D11..............................................................................................D0 4 ADDRESS/ CONTROL BITS 12 DATA BITS Figure 4. Serial-Data Format _______________________________________________________________________________________ Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500/MAX5501 Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD FUNCTION A1 A0 C1 C0 D11................D0 MSB LSB 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data Load input register A; DAC registers unchanged. Load input register B; DAC registers unchanged. Load input register C; DAC registers unchanged. Load input register D; DAC registers unchanged. 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data Load input register A; all DAC registers updated. Load input register B; all DAC registers updated. Load input register C; all DAC registers updated. Load input register D; all DAC registers updated. 0 1 0 0 XXXXXXXXXXXX Update all DAC registers from their respective input registers (startup). 1 0 0 0 12-bit DAC data Load all DAC registers from shift register (startup). 1 1 0 0 XXXXXXXXXXXX Shutdown (provided PDL = 1) 0 0 1 0 XXXXXXXXXXXX UPO goes low (default) 0 1 1 0 XXXXXXXXXXXX UPO goes high 0 0 0 0 XXXXXXXXXXXX No operation (NOP) to DAC registers 1 1 1 0 XXXXXXXXXXXX Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers updated. XXXXXXXXXXXX Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers updated (default). 1 0 1 0 Figure 5 shows the serial-interface timing requirements. The CS input must be low to enable the DAC’s serial interface. When CS is high, the interface control circuitry is disabled. CS must go low for at least tCSS before the rising serial clock (SCLK) edge to properly clock in the first bit. When CS is low, data is clocked into the internal shift register through the serial data input (DIN) on the rising edge of SCLK. The maximum guaranteed clock frequency is 10MHz. Data is latched into the appropriate input/DAC registers on the rising edge of CS. The programming command “load-all-dacs-from-shiftregister” allows all input and DAC registers to be simultaneously loaded with the same digital code from the input shift register. The no operation (NOP) command leaves the register contents unaffected. This feature is used in a daisy-chain configuration (see the Daisy Chaining Devices section). The command to change the clock edge on which serial data is shifted out of DOUT also loads data from all input registers to their respective DAC registers. Serial-Data Output (DOUT) The serial-data output, DOUT, is the internal shift register’s output. The MAX5500/MAX5501 can be programmed so that data is clocked out of DOUT on the rising edge of SCLK (mode 1) or the falling edge (mode 0). In mode 0, output data at DOUT lags input data at DIN by 16.5 clock cycles, maintaining compatibility with MICROWIRE, SPI/QSPI, and other serial interfaces. In mode 1, output data lags input data by 16 clock cycles. On power-up, DOUT defaults to mode 0 timing. User-Programmable Logic Output (UPO) The user-programmable logic output, UPO, allows an external device to be controlled through the MAX5500/MAX5501 serial interface (Table 1). _______________________________________________________________________________________ 9 MAX5500/MAX5501 Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface CS COMMAND EXECUTED SCLK 1 DIN 8 A0 A1 C1 D11 D10 C0 9 D8 D9 D7 16 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 DATA PACKET (N) DOUT (MODE 0) A0 A1 C1 C0 D11 D10 D8 D9 D7 A1 MSB FROM PREVIOUS WRITE DATA PACKET (N) DATA PACKET (N-1) DOUT (MODE 1) A0 A1 C1 C0 D11 D10 D8 D9 D7 D6 D5 D4 D3 D2 D1 D0 A1 MSB FROM PREVIOUS WRITE DATA PACKET (N) DATA PACKET (N-1) Figure 5. Serial-Interface Timing Diagram tCSW CS tCSO tCSS tCL tCP tCH tCSH tCS1 SCLK tDS tDH DIN tDO1 tDO2 DOUT Figure 6. Detailed Serial-Interface Timing Diagram Power-Down Lockout (PDL) Drive power-down lockout, PDL, low to disable software shutdown. When in shutdown, transitioning PDL from high to low wakes up the device with the output set to the state prior to shutdown. Use PDL to asynchronously wake up the device. Daisy Chaining Devices The MAX5500/MAX5501 can be daisy chained by connecting DOUT of one device to DIN of another device (Figure 7). 10 Each DOUT output of the MAX5500/MAX5501 includes an internal active pullup. The sink/source capability of DOUT determines the time required to discharge/charge a capacitive load. See the serial-data-out VOH and VOL specifications in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several MAX5500/MAX5501 devices. In this configuration, the data bus is common to all devices. Data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC. ______________________________________________________________________________________ Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500 MAX5500 MAX5500 SCLK MAX5501 SCLK MAX5501 SCLK MAX5501 DIN DIN CS CS DOUT DOUT DIN CS MAX5500/MAX5501 SCLK DOUT DIN CS TO OTHER SERIAL DEVICES Figure 7. Daisy Chaining MAX5500/MAX5501 DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 CS CS MAX5500 MAX5501 CS MAX5500 MAX5501 MAX5500 MAX5501 SCLK SCLK SCLK DIN DIN DIN Figure 8. Multiple MAX5500/MAX5501 Devices Sharing a Common DIN Line ______________________________________________________________________________________ 11 MAX5500/MAX5501 Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface Applications Information Unipolar Output For a unipolar output, the output voltages and the reference inputs are of the same polarity. Figure 9 shows the MAX5500/MAX5501 unipolar output circuit, which is also the typical operating circuit. Table 2 lists the unipolar output codes. See Figure 10 for rail-to-rail outputs. Figure 10 shows the MAX5500/MAX5501 with the output amplifiers configured with a closed-loop gain of +2 to provide 0 to 5V full-scale range with a 2.5V external reference voltage. Bipolar Output Figure 11 shows the MAX5500/MAX5501 configured for bipolar operation. VOUT = VREF [(2NB/4096) - 1] where NB is the numeric value of the DAC’s binary input code. Table 3 shows digital codes (offset binary) and corresponding output voltages for the circuit of Figure 11. MAX5500 MAX5501 REFERENCE INPUTS REFAB Table 2. Unipolar Code Table REFCD +5V VDD FBA DAC A OUTA DAC CONTENTS MSB LSB 1111 1000 1000 1111 0000 0000 FBB ANALOG OUTPUT DAC B 4095 +VREF ( ——— ) 4096 1111 OUTB FBC 2049 +VREF ( ——— ) 4096 0001 0000 2048 +VREF +VREF ( ——— ) = ———— 4096 2 0111 1111 1111 2047 +VREF ( ——— ) 4096 0000 0000 0001 1 +VREF ( ——— ) 4096 0000 0000 0000 0V DAC C OUTC FBD DAC D OUTD AGND Figure 9. Unipolar Output Circuit REFERENCE INPUTS MAX5500 MAX5501 Table 3. Bipolar Code Table DAC CONTENTS MSB LSB 1111 1111 REFCD +5V VDD 1111 0001 1 +VREF ( ——— ) 2048 1000 0000 0000 0V 0111 1111 1111 1 ) -VREF ( ——— 2048 0000 0000 0001 2047 ) -VREF ( ——— 2048 OUTA FBB 10kΩ 10kΩ DAC B OUTB FBC 10kΩ 10kΩ DAC C OUTC FBD 10kΩ 10kΩ DAC D OUTD AGND 2048 ) = -V -VREF ( ——— REF 2048 0000 DGND VREFAB = VREFCD = 2.5V Note: 1 LSB = (VREF) ( 12 1 4096 ) FBA 10kΩ 10kΩ DAC A 2047 +VREF ( ——— ) 2048 0000 0000 REFAB ANALOG OUTPUT 1000 0000 DGND Figure 10. Unipolar Rail-to-Rail Output Circuit ______________________________________________________________________________________ Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface Power-Supply Considerations On power-up, all input and DAC registers are cleared (set to zero code) and DOUT is in mode 0 (serial data is shifted out of DOUT on the clock’s falling edge). For rated MAX5500/MAX5501 performance, limit VREFAB/ VREFCD to 1.4V below VDD. Bypass VDD with a 4.7µF capacitor in parallel with a 0.1µF capacitor to AGND. Use short lead lengths and place the bypass capacitors as close as possible to the supply inputs. Grounding and Layout Considerations Digital or AC transient signals between AGND and DGND create noise at the analog outputs. Connect AGND and DGND together at the DAC, and then connect this point to the highest-quality ground available. Good PCB ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. Do not use wire-wrapped boards. Chip Information PROCESS: BiCMOS R1 R2 REF_ REF_ VL +5V FB_ DAC_ VOUT MAX5500 MAX5501 IOUT OUT_ 2N3904 DAC OUT_ -5V MAX5500 MAX5501 FB_ R1 = R2 = 10kΩ ± 0.1% Figure 11. Bipolar Output Circuit R Figure 12. Digitally Progammable Current Source ______________________________________________________________________________________ 13 MAX5500/MAX5501 Digitally Programmable Current Source The circuit of Figure 12 places an npn transistor (2N3904 or similar) within the op-amp feedback loop to implement a digitally programmable, unidirectional current source. This circuit drives 4mA to 20mA current loops, which are commonly used in industrial-control applications. The output current is calculated with the following equation: IOUT = (VREF/R) x (NB/4096) where NB is the numeric value of the DAC’s binary input code and R is the sense resistor shown in Figure 12. MAX5500/MAX5501 Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface Pin Configuration Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. TOP VIEW + AGND 1 20 VDD FBA 2 19 FBD OUTA 3 PACKAGE CODE DOCUMENT NO. 20 SSOP A20-2 21-0056 18 OUTD OUTB 4 FBB 5 PACKAGE TYPE 17 OUTC MAX5500 MAX5501 16 FBC 15 REFCD REFAB 6 CL 7 14 PDL CS 13 UPO 8 DIN 9 12 DOUT SCLK 10 11 DGND SSOP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.