19-1587; Rev 0; 11/99 Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface ________________________Applications ____________________________Features ♦ 12-Bit Dual DAC with Internal Gain of +2V/V ♦ Rail-to-Rail Output Swing ♦ 12µs Settling Time ♦ +5V Single-Supply Operation ♦ Low Quiescent Current 500µA (normal operation) 2µA (power-down mode) ♦ SPI/QSPI/MICROWIRE Compatible ♦ Space-Saving 16-Pin QSOP Package ♦ Power-On Reset Clears Registers and DACs to Zero ♦ Adjustable Output Offset Ordering Information PART TEMP. RANGE 0°C to +70°C -40°C to +85°C PINPACKAGE INL (LSB) 16 QSOP 16 QSOP ±4 ±4 Industrial Process Control MAX5104CEE MAX5104EEE Remote Industrial Controls Pin Configuration appears at end of data sheet. Digital Offset and Gain Adjustment Microprocessor-Controlled Systems Motion Control Automatic Test Equipment (ATE) Functional Diagram DOUT CL PDL DGND AGND VDD REFA OSA R DECODE CONTROL R INPUT REG A 16-BIT SHIFT REGISTER DAC REG A R MAX5104 SR CONTROL CS DIN OUTA OSB DAC A LOGIC OUTPUT SCLK INPUT REG B UPOH Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. DAC REG B R OUTB DAC B REFB SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX5104 General Description The MAX5104 low-power, serial, voltage-output, dual 12-bit digital-to-analog converter (DAC) consumes only 500µA from a single +5V supply. This device features Rail-to-Rail® output swing and is available in a spacesaving 16-pin QSOP package. To maximize the dynamic range, the DAC output amplifiers are configured with an internal gain of +2V/V. The 3-wire serial interface is SPI™/QSPI™/MICROWIRE™ compatible. Each DAC has a double-buffered input organized as an input register followed by a DAC register, which allows the input and DAC registers to be updated independently or simultaneously with a 16-bit serial word. Additional features include programmable powerdown (2µA), hardware power-down lockout (PDL), a separate reference voltage input for each DAC that accepts AC and DC signals, and an active-low clear input (CL) that resets all registers and DACs to zero. These devices provide a programmable logic pin for added functionality, and a serial-data output pin for daisy chaining. MAX5104 Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface ABSOLUTE MAXIMUM RATINGS VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND ..................................................................±0.3V OSA, OSB to AGND.......................(VAGND - 4V) to (VDD + 0.3V) REF_, OUT_ to AGND.................................-0.3V to (VDD + 0.3V) Digital Inputs (SCLK, DIN, CS, CL, PDL) to DGND ...........................................(-0.3V to +6V) Digital Outputs (DOUT, UPO) to DGND .....-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................±20mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.30mW/°C above +70°C).......667mW Operating Temperature Ranges MAX5104CEE ...................................................0°C to +70°C MAX5104EEE.................................................-40C° to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +5V ±10%, VREFA = VREFB = +2.048V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C (OS_ connected to AGND for a gain of +2V/V).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±4 LSB LSB STATIC PERFORMANCE 12 Resolution Bits Integral Nonlinearity INL (Note 1) Differential Nonlinearity DNL Guaranteed monotonic ±1 Offset Error VOS Code = 10 ±10 Offset Tempco TCVOS Normalized to 2.048V 4 Gain Error -0.2 Gain-Error Tempco VDD Power-Supply Rejection Ratio PSRR Normalized to 2.048V 4 4.5V ≤ VDD ≤ 5.5V 20 mV ppm/°C ±8 LSB ppm/°C 600 µV/V REFERENCE INPUT Reference Input Range REF Reference Input Resistance RREF 0 Minimum with code 1554 hex 14 VDD - 1.4 V 20 kΩ MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Input code = 1FFE hex, VREF_ = 0.67Vp-p at 2.5VDC 300 kHz Reference Feedthrough Input code = 0000 hex, VREF_ = (VDD - 1.4Vp-p), f = 1kHz -82 dB Input code = 1FFE hex, VREF_ = 1Vp-p at 1.25VDC, f = 25kHz 75 dB Signal-to-Noise plus Distortion Ratio SINAD DIGITAL INPUTS Input High Voltage VIH CL, PDL, CS, DIN, SCLK Input Low Voltage VIL CL, PDL, CS, DIN, SCLK Input Hysteresis VHYS Input Leakage Current IIN Input Capacitance CIN 2 3 V 0.8 200 VIN = 0 to VDD 0.001 8 _______________________________________________________________________________________ V mV ±1 µA pF Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface (VDD = +5V ±10%, VREFA = VREFB = +2.048V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C (OS_ connected to AGND for a gain of +2V/V).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 0.13 0.40 UNITS DIGITAL OUTPUTS (DOUT, UPO) Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA VDD - 0.5 V V DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time To 1/2LSB of full-scale, VSTEP = 4V Output Voltage Swing Rail-to-rail (Note 2) OSA or OSB Input Resistance ROS_ 24 Time Required to Exit Shutdown CS = VDD, SCLK = 100kHz, VSCLK = 5Vp-p Digital Feedthrough Digital Crosstalk 0.75 V/µs 15 µs 0 to VDD V 34 kΩ 25 µs 5 nVs 5 nVs POWER SUPPLIES Positive Supply Voltage VDD Power-Supply Current IDD Power-Supply Current in Shutdown 4.5 (Note 3) IDD(SHDN) (Note 3) Reference Current in Shutdown 5.5 V 0.5 0.65 mA 2 10 µA 0 ±1 µA TIMING CHARACTERISTICS SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH (Note 4) 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns SDI Setup Time tDS 40 ns SDI Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD = 200pF SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD = 200pF SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold tCS1 40 ns CS Pulse Width High tCSW 100 ns 80 ns 80 ns Note 1: Accuracy is specified from code 6 to code 4095. Note 2: Accuracy is better than 1LSB for VOUT_ greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end points. Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞. Note 4: SCLK minimum clock period includes the rise and fall times. _______________________________________________________________________________________ 3 MAX5104 ELECTRICAL CHARACTERISTICS (continued) __________________________________________Typical Operating Characteristics (VDD = +5V, RL = 10kΩ, CL = 100pF, OS_ pins connected to AGND, TA = +25°C, unless otherwise noted.) -10 -12 -14 -16 600 550 CODE = 0000 (HEX) 500 -20 VREF = +2.048V RL = ∞ 400 1 370 740 1110 1480 1850 -55 -35 -15 FREQUENCY (kHz) 5 25 45 65 -80 85 105 125 1 10 TEMPERATURE (°C) FREQUENCY (kHz) FULL-SCALE ERROR vs. RESISTIVE LOAD REFERENCE FEEDTHROUGH AT 1kHz -50 MAX5104 toc04 0.50 VREF = +2.048V 0.25 0 -0.25 -0.50 -0.75 VREF = +3.6Vp-p AT 1.88VDC CODE = 0000 (HEX) -60 -70 RELATIVE OUTPUT (dB) FULL-SCALE ERROR (LSB) -60 -70 450 VREF = +0.67Vp-p AT 2.5VDC CODE = 1FFE (HEX) -50 MAX5104 toc05 -8 VREF = +1Vp-p AT 2.5VDC CODE = 1FFE (HEX) -40 THD + N (dB) -6 CODE = 1FFE (HEX) 650 SUPPLY CURRENT (µA) -4 -30 MAX5104 toc02 700 MAX5104 toc01 -2 -18 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY SUPPLY CURRENT vs. TEMPERATURE -1.00 -80 -90 -100 -110 -120 -130 -1.25 -140 -1.50 -150 1 10 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 RL (kΩ) FREQUENCY (kHz) SHUTDOWN CURRENT vs. TEMPERATURE VREF = +1V 4 3 2 VREF = +2.45Vp-p AT 1.225VDC f = 1kHz CODE = 1FFE (HEX) -10 -20 RELATIVE OUTPUT (dB) 5 SHUTDOWN CURRENT (µA) OUTPUT FFT PLOT 0 MAX5104 toc06 6 MAX5104 toc07 0.1 -30 NOTE: RELATIVE TO FULL SCALE -40 -50 -60 -70 -80 1 -90 -100 0 -55 -35 -15 5 25 45 65 TEMPERATURE (°C) 4 MAX5104 toc03 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE 0 RELATIVE OUTPUT (dB) MAX5104 Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface 85 105 125 0.5 1.6 2.7 3.8 4.9 6.0 FREQUENCY (kHz) _______________________________________________________________________________________ 100 Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface DYNAMIC RESPONSE RISE TIME MAX5104 toc09 MAX5104 toc08 DYNAMIC RESPONSE FALL TIME CS 5V/div OUT_ 1V/div OUT_ 1V/div 2µs/div 2µs/div VREF = +2.048V VREF = +2.048V SUPPLY CURRENT vs. SUPPLY VOLTAGE MAJOR-CARRY TRANSITION CODE = 1FFE (HEX) MAX5104 toc11 MAX51504 toc10 0.60 0.55 CS 2V/div 0.50 CODE = OOOO (HEX) OUT_ 50mV/div AC-COUPLED 0.45 0.40 4.50 4.75 5.00 5.25 5.50 5µs/div SUPPLY VOLTAGE (V) TRANSITION FROM 1000 (HEX) TO 0FFE (HEX) ANALOG CROSSTALK DIGITAL FEEDTHROUGH MAX5104 toc13 MAX5104 toc12 SUPPLY CURRENT (mA) CS 5V/div OUTA 5V/div OUTA 500µV/div AC-COUPLED OUTB 200µV/div AC-COUPLED 250µs/div SCLK 5V/div 2.5µs/div VREF = +2.048V, GAIN = +2V/V, CODE = 1FFE HEX _______________________________________________________________________________________ 5 MAX5104 _____________________________Typical Operating Characteristics (continued) (VDD = +5V, RL = 10kΩ, CL = 100pF, OS_ pins connected to AGND, TA = +25°C, unless otherwise noted.) MAX5104 Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface _____________________Pin Description PIN NAME 1 AGND Analog Ground 2 OUTA DAC A Output Voltage 3 OSA DAC A Offset Adjustment 4 REFA Reference for DAC A OS_ R FUNCTION R 2R 2R D0 R 2R D10 OUT_ R 2R 2R D11 D12 5 CL Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V. 6 CS Chip-Select Input 7 DIN Serial-Data Input 8 SCLK Serial-Clock Input 9 DGND Digital Ground Figure 1. Simplified DAC Circuit Diagram 10 DOUT Serial-Data Output 11 UPO User-Programmable Output 12 PDL Power-Down Lockout. The device cannot be powered down when PDL is low. 13 REFB Reference for DAC B 14 OSB DAC B Offset Adjustment 15 OUTB DAC B Output Voltage VOUT = (VREF · NB / 4096) · 2 where NB is the numeric value of the DAC’s binary input code (0 to 4095) and VREF is the reference voltage. The reference input impedance ranges from 14kΩ (1554 hex) to several gigohms (with an input code of 0000 hex). The reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to 50pF with a full-scale input code. 16 VDD Positive Power Supply _______________Detailed Description The MAX5104 dual, 12-bit, voltage-output DAC is easily configured with a 3-wire serial interface. The device includes a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition, trimmed internal resistors produce an internal gain of +2V/V that maximizes output voltage swing. The amplifier’s offset-adjust pin allows for a DC shift in the DAC’s output. Both DACs use an inverted R-2R ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent full-scale values. Figure 1 depicts a simplified circuit diagram of one of the two DACs. Reference Inputs The reference inputs accept both AC and DC values with a voltage range extending from 0 to (VDD - 1.4V). Determine the output voltage using the following equation (OS_ = AGND): 6 R REF_ AGND Output Amplifier The MAX5104’s output amplifiers have internal resistors that provide for a gain of +2V/V when OS_ is connected to AGND. These resistors are trimmed to minimize gain error. The output amplifiers have a typical slew rate of 0.75V/µs and settle to 1/2LSB within 15µs, with a load of 10kΩ in parallel with 100pF. Loads less than 2kΩ degrade performance. The OS_ pin can be used to produce an adjustable offset voltage at the output. For instance, to achieve a 1V offset, apply -1V to the OS_ pin to produce an output range from 1V to (1V + VREF · 2). Note that the DAC’s output range is still limited by the maximum output voltage specification. Power-Down Mode The MAX5104 features a software-programmable shutdown mode that reduces the typical supply current to 2µA. The two DACs can be powered down independently, or simultaneously using the appropriate programming command. Enter power-down mode by writing the appropriate input-control word (Table 1). In power-down mode, the reference inputs and amplifier outputs become high impedance, and the serial interface remains active. Data in the input registers is saved, _______________________________________________________________________________________ Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface MAX5104 Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD FUNCTION A0 C1 C0 D11.......................D0 (MSB) (LSB) S0 0 0 1 12-bit DAC data 0 Load input register A; DAC registers are unchanged. 1 0 1 12-bit DAC data 0 Load input register B; DAC registers are unchanged. 0 1 0 12-bit DAC data 0 Load input register A; all DAC registers are updated. 1 1 0 12-bit DAC data 0 Load input register B; all DAC registers are updated. 0 1 1 12-bit DAC data 0 Load all DAC registers from the shift register (start up both DACs with new data). 1 0 0 XXXXXXXXXXXX 0 Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). 1 1 1 XXXXXXXXXXXX 0 Shut down both DACs (provided PDL = 1). 0 0 0 0 0 1 X XXXXXXXX 0 Update DAC register A from input register A (start up DAC A with data previously stored in input register A). 0 0 0 1 0 1 X XXXXXXXX 0 Update DAC register B from input register B (start up DAC B with data previously stored in input register B). 0 0 0 1 1 0 X XXXXXXXX 0 Power Down DAC A (provided PDL = 1). 0 0 0 1 1 1 X XXXXXXXX 0 Power Down DAC B (provided PDL = 1). 0 0 0 0 1 0 X XXXXXXXX 0 UPO goes low (default). 0 0 0 0 1 1 X XXXXXXXX 0 UPO goes high. 0 0 0 1 0 0 1 XXXXXXXX 0 Mode 1, DOUT clocked out on SCLK’s rising edge. 0 0 0 1 0 0 0 XXXXXXXX 0 Mode 0, DOUT clocked out on SCLK’s falling edge (default). 0 0 0 0 0 0 X XXXXXXXX 0 No operation (NOP). X = Don’t care Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub-bit, always zero. allowing the MAX5104 to recall the output state prior to entering power-down when returning to normal mode. Exit power-down by recalling the previous condition or by updating the DAC with new information. When returning to normal operation (exiting power-down), wait 20µs for output stabilization. Serial Interface The MAX5104’s 3-wire serial interface is compatible with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial input word consists of 1 address bit, 2 control bits, 12 bits of data (MSB to LSB), and 1 sub-bit as shown in Figure 4. The address and control bits determine the MAX5104’s response, as outlined in Table 1. MAX5104 SCLK SK DIN SO CS I/O MICROWIRE PORT Figure 2. Connections for MICROWIRE _______________________________________________________________________________________ 7 MAX5104 Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface The MAX5104’s digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow the DACs to act independently. Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI, MICROWIRE), with CS low during this period. The address and control bits determine which register will be updated, and the state of the registers when exiting power-down. The 3-bit address/control determines the following: +5V SS DIN MAX5104 MOSI SCLK SCK CS SPI/QSPI PORT • Registers to be updated • Clock edge on which data is to be clocked out via the serial-data output (DOUT) I/O CPOL = 0, CPHA = 0 • State of the user-programmable logic output • Configuration of the device after power-down The general timing diagram of Figure 5 illustrates how data is acquired. Driving CS low enables the device to receive data; otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers, depending on the address and control bits. The maximum clock frequency guaranteed for proper operation is 10MHz. Figure 6 shows a more detailed timing diagram of the serial interface. Figure 3. Connections for SPI/QSPI MSB...................................................................................LSB 16 Bits of Serial Data Address Bits Control Bits MSB...Data Bits...LSB Sub Bit A0 C1, C0 D11.......................D0 S0 12 Data Bits 0 1 Address/2 Control Bits Figure 4. Serial-Data Format CS COMMAND EXECUTED SCLK 1 DIN A0 8 C1 C0 D11 D10 D9 D8 D7 9 D6 16 D5 D4 D3 D2 D1 D0 S0 Figure 5. Serial-Interface Timing Diagram 8 _______________________________________________________________________________________ Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface MAX5104 tCSW CS tCSS tCSO tCL tCP tCH tCSH tCS1 SCLK tDS tDH DIN Figure 6. Detailed Serial-Interface Timing Diagram SCLK SCLK MAX5104 DIN SCLK MAX5104 DOUT DIN MAX5104 DOUT DOUT CS CS CS DIN TO OTHER SERIAL DEVICES Figure 7. Daisy Chaining MAX5104s DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 CS CS CS MAX5104 MAX5104 MAX5104 SCLK SCLK SCLK DIN DIN DIN Figure 8. Multiple MAX5104s Sharing a Common DIN Line _______________________________________________________________________________________ 9 MAX5104 Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface Serial-Data Output The serial-data output, DOUT, is the internal shift register’s output. DOUT allows for daisy chaining of devices and data readback. The MAX5104 can be programmed to shift data out of DOUT on SCLK’s falling edge (Mode 0) or on the rising edge (Mode 1). Mode 0 provides a lag of 16 clock cycles, which maintains compatibility with SPI/QSPI and MICROWIRE interfaces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode 0. VDD R MAX5104 R DAC_ OUT_ AGND User-Programmable Logic Output User-programmable logic output (UPO) allows an external device to be controlled through the serial interface (Table 1), thereby reducing the number of microcontroller I/O pins required. On power-up, UPO is low. OS_ +5V/+3V REF_ DGND GAIN = +2V/V Figure 9. Unipolar Output Circuit (Rail-to-Rail) Power-Down Lockout Input The power-down lockout (PDL) pin disables software shutdown when low. When in power-down, transitioning PDL from high to low wakes up the part with the output set to the state prior to power-down. PDL can also be used to asynchronously wake up the device. OS_ +5V/+3V REF_ VOS VDD R MAX5104 Daisy-Chaining Devices Any number of MAX5104s can be daisy-chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7). Since the MAX5104’s DOUT pin has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. See the digital output VOH and VOL specifications in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several MAX5104s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC. __________Applications Information Unipolar Output Figure 9 shows the MAX5104 configured for unipolar, rail-to-rail operation with a gain of +2V/V. The MAX5104 can produce a 0 to 4.096V output with a 2.048V reference (Figure 9). Table 2 lists the unipolar output codes. An offset to the output can be achieved by connecting a voltage to OS_, as shown in Figure 10. By applying VOS_ = -1V, the output values will range between 1V and (1V + VREF · 2). R DAC _ OUT_ AGND Figure 10. Setting OS_ for Output Offset Table 2. Unipolar Code Table (Gain = +2) DAC CONTENTS MSB LSB 10 ANALOG OUTPUT 1 1 1 1 1 1 1 1 11 1 1 ( 0 ) 4095 +VREF ⋅2 4096 1 0 0 0 0 0 0 0 00 0 1 ( 0 ) 2049 +VREF ⋅2 4096 1 0 0 0 0 0 0 0 00 0 0 ( 0 ) 2048 +VREF 4096 ⋅2 = VREF 0 1 1 1 1 1 1 1 11 1 1 ( 0 ) 2047 +VREF ⋅2 4096 0000 0000 0001 (0) 1 +VREF ⋅2 4096 Bipolar Output The MAX5104 can be configured for a bipolar output (Figure 11). The output voltage is given by the equation (OS_ = AGND): DGND 0 0 0 0 0 0 0 0 00 0 0 ( 0 ) Note: ( ) are for the sub-bit. ______________________________________________________________________________________ 0V Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface where NB represents the numeric value of the DAC’s binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11’s circuit. The total harmonic distortion plus noise (THD+N) is typically less than -78dB at full scale with a 1Vp-p input swing at 5kHz. Digital Calibration and Threshold Selection Using an AC Reference In applications where the reference has an AC signal component, the MAX5104 has multiplying capabilities within the reference input voltage range specifications. Figure 12 shows a technique for applying a sinusoidal input to REF_, where the AC signal is offset before being applied to the reference input. Figure 13 shows the MAX5104 in a digital calibration application. With a bright-light value applied to the photodiode (on), the DAC is digitally ramped until it trips the comparator. The microprocessor (µP) stores this “high” calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. Table 3. Bipolar Code Table DAC CONTENTS MSB LSB +5V/ +3V ANALOG OUTPUT +5V/+3V 26k AC REFERENCE INPUT 2047 2048 1111 1111 1 111 (0) +VREF 1000 0000 0 001 (0) 1 +VREF 2048 1000 0000 0 000 (0) 0V 0111 1111 1 111 (0) 1 -VREF 2048 500mVp-p MAX495 10k VDD REF R OS_ R 0000 0000 0 001 (0) 2047 +VREF ⋅2 4096 0000 0000 0 000 (0) 2048 = - VREF 2048 -VREF OUT_ DAC_ MAX5104 AGND DGND Figure 12. AC Reference Input Circuit Note: ( ) are for the sub-bit. V+ +5V/+3V REF_ 10k 10k REF_ OS_ OS_ VDD VDD R MAX5104 DAC _ AGND Figure 11. Bipolar Output Circuit MAX5104 V+ R VOUT 10k DAC _ V- DIN 10k V- VOUT OUT_ µP OUT_ DGND R V+ R PHOTODIODE +5V/+3V AGND DGND RPULLDOWN Figure 13. Digital Calibration ______________________________________________________________________________________ 11 MAX5104 Harmonic Distortion and Noise VOUT = VREF [((2 · NB) / 4096) - 1] MAX5104 Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface VDD OSA R MAX5104 VIN REFA R OUTA CS SCLK DIN VREF SHIFT REGISTER INPUT REG A DAC REG A DACA INPUT REG B DAC REG B DACB R1 R2 OUTB REFB VOUT R3 R4 R R [ ] [ ] = (V 2NA )( R2 )(1+ R4 ) (V [ 4096 R1+R2 R3 ] [ VOUT = GAIN – OFFSET OSB IN AGND REF 2NB 4096 )( R4R3 )] NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA. NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB. DGND Figure 14. Digital Control of Gain and Offset The µP then programs the DAC to set an output voltage at the midpoint of the two calibrated values. Applications include tachometers, motion sensing, automatic readers, and liquid-clarity analysis. Pin Configuration TOP VIEW Digital Control of Gain and Offset AGND 1 16 VDD The two DACs can be used to control the offset and gain for curve-fitting nonlinear functions, such as transducer linearization or analog compression/expansion applications. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 14). OUTA 2 15 OUTB Power-Supply Considerations SCLK 8 On power-up, the input and DAC registers clear (set to zero code). For rated performance, VREF_ should be at least 1.4V below VDD. Bypass the power supply with a 4.7µF capacitor in parallel with a 0.1µF capacitor to AGND. Minimize lead lengths to reduce lead inductance. Grounding and Layout Considerations Digital and AC transient signals on AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required. OSA 3 REFA 4 14 OSB MAX5104 13 REFB CL 5 12 PDL CS 6 11 UPO DIN 7 10 DOUT 9 DGND QSOP Chip Information TRANSISTOR COUNT: 3053 SUBSTRATE CONNECTED TO AGND Package Information Package information is available on Maxim’s website: www.maxim-ic.com. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.