MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
•
DESCRIPTION
The M65675FP/M65676FP is a NTSC/PAL encoder LSI that
•
converts CCIR 601 or CCIR 656 (SMPTE125M) format digital video
signals into analog component and composite video signals in
accordance with either NTSC or B/G-PAL standards.
•
•
•
The 10-bit digital luma (Y) and analog chroma (U/V) signals are
available in Y/U/V output mode.
In addition it performs the closed caption capability (TV line 21/
NTSC), CGMS*1 encoding (TV line 20/NTSC), WSS*2 encoding (TV
Controllable Picture Processing Functions
Color, TINT and Brightness
Built-in Analog Functions
Y/C Mixing
Two 10-bit DACs
Three 6-dB Amplifiers
Built-in 27 MHz System Clock Generator
Single 3.3V Supply
64-pin PQFP Package
line 23/PAL), Macrovision copy protection *3 function (Rev. 7.01) and
Note
*1: Copy Generation Management System-A (IEC1880)
on-screen display. The OSD function can be directly accessed by
*2: Wide Screen Signaling (ETS300 294)
the OSD microprocessor via built-in interface.
*3: This applies to M65675FP only.
This device is protected by U.S. patent number 4631603,
FEATURES
4577216 and 4819098 and other intellectual property rights.
•
•
The use of Macrovision's copy protection technology in the
•
•
•
•
•
•
•
•
•
NTSC and B/G-PAL Outputs
Component Y/C (S-Video), Composite (CVBS) or Y *4/U/V
Outputs
Supporting CCIR601, CCIR656 (SMPTE125M) Format Data
Processing Y/Cb/Cr and Y/U/V Pixel Data
27MHz Clock Frequency (Two-times Oversampling)
Macrovision Copy Protection*3 Processing (Revision 7.01)
Close Captioning Supporting (line 21/NTSC) (ODD Parity Operation)
V-Code Supporting (line 21/NTSC) (ODD Parity Operation)
CGMS*1 Data Insertion (line 20/NTSC) (CRCC Error Correction
Code Operation)
WSS*2 Supporting (line23/PAL)
OSD Insertion Interface and 3¥8¥4-bit Color Look-up Table
device must be authorized by Macrovision and is intend for
home and other limited pay-par-view use only, unless otherwise
authorized in writing by Macrovision. Reverse engineering or
disassembly is prohibited.
*4: Y output is 10bit digital signal.
APPLICATION
DVD Players, Digital Satellite & Cable System (Set Top Boxes/
IRDs), Video CD, Multimedia Terminals, Video Games, Digital VCR
& Camcoder etc.
33
C
CVBS
34 N.C.
35
Y
37
36 AVSS2
Y in
39
38 AVDD2
C in
40 N.C
41
DAC
42 Ccomp
44 AVDD1
DAY
46
43
Cref
47
Ycomp 49
32 N.C.
N.C. 50
31 N.C.
DVDD1 51
30 DVDD1
DVSS1 52
29
TEST
X out
53
28
SCL
X in
54
27
SDA
DVSS2 55
26
ACK
25
RESET
PXD7
56
PXD6
57
24
Master/slave
PXD5
58
23
OSD2
PXD4
59
22
OSD1
PXD3
60
21
OSD0
PXD2
61
20
OSDCK
PXD1
62
19 DVSS1
PXD0
63
18 DVDD1
DVDD2 64
17 DVDD2
15
VD0
Outline 64P6N-A
DVSS2 16
14
11
VD4
VD1
10
VD5
12
9
VD6
13
8
VD7
VD2
7
VD8
VD3
5
6
HD
VD
3
4
DVASEL
VD9
2
PXCLK
M65675FP
M65676FP
DVSS2 1
1
45 AVSS1
Yref
48
PIN CONFIGURATION (TOP VIEW)
NC : NO CONNECTION
slave
receiver
serial interface
Timing
pulse
generator
Cr/V
control
register
∗1
V
U
signal
generator
Anti Copy
Processing
Cb/Cr to U/V
Converter
Converter
sub carrier
generator
∗1: This function bloc is M65675FP only
Cb/U
Chroma
Encoder
C/V
Y/U
10bit
DAC
10bit
DAC
Analog
Y/C
MIX
CVBS
C
6dB
6dB
Y
6dB
Notice:This is not a final specification.
Some parametric limits are subject to change.
Commands
register
C-sync
generator
HD/VD
generator
Sync Processing
Oscillator
8-color
Look-up
table RAM
Video Anti Copy
signal adder (2)
CGMS/WSS
Manager
Closed Caption
Manager
Clamp
&
bias
PRELIMINARY
Muster
/Slave
VD
HD
Xout
Xin
Cb/Cr
Interpolation
filter
CLK
generator
Cr/V
Cb/U
C-sync
adder
Video Anti Copy
signal adder (1)
Burst
adder
Y
Interpolation
filter
PXCLK
VD [9:0]
Y
OSDCK
OSD
controller
Y/U/V
DAY
AVSS1
AVDD1
Y ref
C ref
PXD [7:0]
Y
Encoder
AVSS2
AVDD2
Blanking
control
Y
Y/Cb/Cr
Yin
OSD
Interface
Video signal generator
Cin
Input
Interface
OSD2
OSD1
OSD0
BPF
LPF
MITSUBISHI ICs (TV)
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
BLOCK DIAGRAM
DAC
TEST
RESET
DVSS2(X2)
DVSS1(X2)
DVDD1(X2)
DVDD2(X2)
OSD mixer
SDA
SCL
ACK
Demulti Plexer
2
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VI
VO
Ta
Tstg
Parameter
DC supply voltage
Digital input voltage
Digital output voltage
Operating temperature
Storage temperature
Min.
-0.3
-0.3
-0.3
-20
-40
Limits
Typ.
Max.
4.5
VDD+0.3
VDD+0.3
+25
+75
+125
Unit
V
V
V
°C
°C
RECOMMENDED OPERATING CONDITION (Ta=25∞C, DVDD=AVDD=3.3V, DVSS=AVSS=0V, unless otherwise noted)
Symbol
Parameter
Supply
Digital supply voltage
DVDDX
AVDDX
Analog supply voltage
DIDD
Digital current consumption
AIDD
Analog current consumption
Digital input
VIL
Input voltage
VIH
IIL
Input leakage current
CI
Input capacitance
Digital output
VOL
Output voltage
VOH
CO
Output capacitance
I2C bus
IO
Output current
IOZ
Output leakage current (off)
D/A converter
Res
Resolution
INL
Integral non-linearity error
DNL
Differential non-linearity error
VfSMAX
Maximum output amplitude
6-dB amplifier
Rbias
Bias resistor
GV_YC
Voltage gain (Y/C)
GV_CV
Voltage gain (CVBS)
DRin
Input dynamic range
DRout
Output dynamic range
3
Test conditions
Min.
3.0
3.15
0
0
DVDD=3.0V
DVDD=3.6V
DVDD=3.0V, VI=0V or VI=3.6V
f=1MHz, VDD=0V
DVDD=3.3V, | IO |<1µA
3.3
3.3
0
2.5
7
Max.
7
V
V
mA
mA
0.8
3.6
±15
15
V
V
µA
pF
0.05
15
V
V
pF
±15
mA
µA
4.0
10
Rref=2.2kΩ, RL=300Ω
Rref=2.2k Ω, RL=300Ω
000 to 3FF
Bit
±2.0
±1.0
LSB
LSB
V P-P
11.5
6.50
6.85
kΩ
dB
dB
VP-P
VP-P
1.5
7.5
5.50
5.10
0.8
1.6
10
6.00
6.00
Unit
3.6
3.45
45
55
3.25
f=1MHz, VDD=0V
DVDD=3.0V, VIL=0.4V
DVDD=3.6V, VI=0V or VI=3.6V
Limits
Typ.
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
M65675FP/M65676FP System Architecture
DIGITAL NTSC/PAL ENCODER
◊ Synchronization Control Block
C-sync and several timing control signals for internal use are
Block Diagram of M65675FP/M65676FP
generated with 3 different H/V sync signals as reference. 1st
The M65675FP/M65676FP block diagram is shown in Fig. 3.1.
reference H/V sync signal is external input, 2nd is internally
The M65675FP/M65676FP consists of 4 functional blocks: a video
generated one and 3rd is decoded one in digital blanking code
signal processing, a synchronization control, a serial interface and
(SAV, EAV etc.)
an analog signal processing blocks. The video signal processing
block includes an input interface, OSD interface, YCbCr to YUV
◊ Serial Interface Block
converter/encoder and copy protection signal generator (This
The registers can be read and written according to I 2C bus format.
function block is M65675FP only).
The data transport to the internal blocks is performed on the trailing
A sync generator and timing pulse generator are in the
edge of V-sync, except for some set-up registers.
synchronization control block. The serial interface block has an I 2C
slave register and command register. The analog signal processing
◊ Analog Signal Processing Block
block includes two 10-bit DACs, a Y/C mixing circuit and three 6-dB
The output of the 10-bit DAC is 1.2VP-P at the sampling frequency
amplifiers.
of 27.0MHz. The inputs of Yin and Cin are set up to 0.6V P-P (Typ)
and the component outputs will be amplified by 6-dB up to 1.2V P-P
General Description of Each Functional Blocks
(Typ). The analog composite signal from the mixing circuit is also
◊ Video Signal Processing Block
amplified up to 1.2VP-P (Typ)
The Y/Cb/Cr or Y/U/V are converted into digital Y/C signals in
accordance with either NTSC and B/G-PAL standards. In addition
the closed caption, CGMS/WSS and copy protection signals will be
inserted in that digital Y/C signals.
Functional Description
Video Signal processing
Input Interface
Input Format
[Input Interface]
The video encoder accepts 16/8-bit CCIR601 and CCIR656 format.
The multiplexed Y/Cb/Cr or Y/U/V pixel data are divided by the
The specifications of these format are described as follows;
individual components, then the Cb/Cr or U/V data rate is increased
◊ 16-bit CCIR601 Interface
from 6.75 Mbps up to 13.5Mbps.
PXCLK=13.5MHz
Y=8-bit/13.5Mbps
[OSD Interface]
The digital video signal in the CLT (Color Look-up Table) is overlaid
with OSD data according to the external instructions.
16-235 straight-binary-data
Cb/Cr=8-bit/13.5 Mbps (Cb=Cr=8-bit/6.75 Mbps)
16-240 128 offset-binary-data
Active video area 525/60=720-pixel¥480 line/frame
[Y/Cb/Cr to Y/U/V Converter]
It converts the Y/Cb/Cr into Y/U/V, and then c-sync and burst signals
(22/284 line-263/525 line)
625/50=720-pixel¥576 line/frame
are inserted on the converted Y and U/V signals, respectively.
(23/336 line-310/623 line)
However, the burst insertion is not done in the Y/U/V output mode.
◊ 8-bit CCIR601 Interface
[Encoder]
PXCLK=27.0MHz
The closed caption, CGMS/WSS and copy protection signals are
Cb/Y/Cr=8-bit/27.0Mbps
inserted into the Y signal and C signal is modulated into the
Y= 8-bit/13.5Mbps
appropriate standards. After that processing, both Y and C signals
will be oversampled.
16-235 straight-binary-data
Cb/Cr=8-bit/13.5Mbps (Cb=Cr=8-bit/6.75Mbps)
16-240 128 offset-binary-data
[Copy Protection Processing]
According to the copy protection setting, VBI pulse (AGC and
backporch pulse) and Advanced Split Burst are generated in
accordance with Macrovision Rev 7.01.
Active video area 525/60=720-pixel¥480 line/frame
(22/284 line-263/525 line)
625/50=720-pixel¥576 line/frame
(23/336 line-310/623 line)
4
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
◊ CCIR656 Interface
DIGITAL NTSC/PAL ENCODER
PXCLK=27.0MHz
OSD Interface
Color Look-up Table (CLT)
Cb/Y/Cr=8-bit/27.0Mbps
The built-in CLT can be equivalent to 4bit¥8 colors, so that the
Y=8-bit/27.0Mbps
reproduced colors are 8/4096.
16-235 straight-binary-data
Cb/Cr=8-bit/13.5Mbps (Cb=Cr=8-bit/6.75 Mbps)
16-240 128 offset-binary-data
Active video area 525/60=720-pixel¥480 line/frame
(22/284 line-263/525 line)
625/50=720-pixel¥576 line/frame
The setting ranges and the signal levels in the overlaying of Y, Cb
and Cr each are shown below;
Y : Setting range=1 (h) to F (h) : straight-binary data
Signal Level=10 (h) to F0 (h) : straight-binary data
Cb/Cr : Setting range=1 (h) to F (h) : 8 offset-binary data
Signal level=10 (h) to F0 (h) : 128 offset-binary data
(23/336 line-310/623 line)
Vertical blanking Interval
525/60=1/264-9/272
OSD Control
Digital field 1 (ODD)=4-265
Overlaying the appointed data on the video signal from MPEG is
Digital field 2 (EVEN)=266-3
possible by inputting the address data to the CLT in synchronization
625/50=624/311-22/335
with OSDCLK, H-sync and V-sync. The overlaying is prohibited in
Digital field 1 (ODD)=1-312
case CLT address is set to 7 (h).
Digital field 2 (EVEN)=313-625
The OSD control specifications are shown below;
Horizontal blanking Interval525/60=276CLK (0H=32CLK)
◊ OSDCLK= selectable 13.5MHz or 6.75MHz
selectable continuous or discontinuous
EAV=1-4CLK/SAV=273-276CLK
(pausing during H-sync) clock
625/50=288CLK (0H=24CLK)
EAV=1-4CLK/SAV=285-288CLK
◊ Color Signal Blend=Maximum 3 colors are allowed to be set.
The data of CLT addresses 0 (h) to 2 (h) are
The input data (X), except the active data in the above support
dedicated to color blending.
format, are clipped as shown below;
The blend ratio is fixed by 1:1 and blend
◊ 8/16-bit CCIR601 Interface
mode is selectable between Y/Cmix and Ymix
Y
mode.
: X£16 Æ 16
X≥235Æ235
(Whole period)
Cb/Cr : X£16 Æ 16
(U/V)
X≥240Æ240
(Whole period)
Y/Cb/Cr to Y/U/V Converter
C-sync Addition
The sync signal, set up in the register, is added to Y signal
◊ CCIR656 Interface
Y
according to C-sync timing generated from H-sync/V-sync. Typical
sync height, set up in the register, is calculated by the following
: X£16 Æ 16
X≥235Æ235
(Active video period)
equations;
X
(Blanking period)
Sync level={(White peak input level-16)¥2.5¥Xsync (IRE)}/100
Æ
16
In the case of NTSC : {(235-16)¥2.5¥40}/100=219 (DB H)
Cb/Cr : X£16 Æ 16
(U/V)
X≥240Æ240
(Active video period)
X
(Blanking period)
Æ
128
PAL
: {(235-16)¥2.5¥43}/100=235.4 (EB H)
Note: Xsync=Output sync level (IRE)
Digital Multiplexing
Set-up Control (NTSC)
The input pixel data described in 4.1.1.1 are de-multiplexed, then Y,
In the NTSC signal generation mode, three set-up modes are
Cb,Cr and Y, U, V signals will be converted to each 8-bit parallel
possible according to the register.
data. After the above conversion, 6.75Mbps Cb, Cr/U, V data are
Selectable set-up modes are;
interpolated at a double clock rate of 13.5Mbps.
Mode 0 : Set-upÆ0 IRE
Mode 1 : Set-upÆ+7.5 IRE
PXCLK Processing
Mode 2 : Set-upÆ-7.5 IRE
PXCLK is generated from the 27.0MHz system clock according to
the appropriate selected format and the clock signal for Y, Cb, Cr/Y,
Cb/Cr to U/V Conversion
U, V data de-multiplexing is also generated.
The Cb/Cr data are converted into the U/V data by the following
equations;
U=0.493¥Cb/0.564
V=0.877¥Cr/0.713
5
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
Burst Insertion
The burst signal, set up in the corresponding register, is inserted to
Encoder
Closed Caption Encoding
Cb/Cr according to the burst timing signal.
In the NTSC (525/60) mode, 8-bit¥2byte data, including parity bit,
The burst signal is derived from the following equations;
set in the register are converted into the format shown in fig. 1 and
NTSC=ABS (Burst level-128)¥5/5.47 (IRE)
then will be inserted in the video signal according to the register
Ex. 40IRE=54H
data of the closed captions control specification (closed caption on/
PAL={ABS (Burst level-128)¥5/5.47}¥÷2 (IRE)
off and caption data insertion mode). After the completion of
Ex. 43IRE=5EH
transmission, the new data are loaded in the register by setting the
close caption flag to "1", then the transferred data are loaded in the
Video Anticopy Signal Addition [1]
(VBI Amplitude/CSP)
register on the trailing edge of V-sync pulse by setting that flag to
This applies to M65675FP only.
halted and the caption data are not inserted in the video signals).
"0". (In case the closed caption flag is "1", the new data loading is
Sync-amplitude function and Color StripeTM control function are
carried out according to the corresponding register, in accordance
with Macrovision Video Anti Copy Process Rev. 7.0 dated
September 6 1996.
Parity Bit
CCD16
CCD17
CCD15
CCD14
CCD13
CCD11
CCD10
CCD07
CCD06
2nd. byte
CCD05
CCD04
CCD03
CCD02
CCD01
START BIT
CCD00
Color
Burst
Parity Bit
1st. byte
CCD12
7 cycles of 503kHz
(Clock Run-in )
33.764µs
12.910µs
3.972+0.2/-0.0µs
51.268+0.2/-0.0µs
10.500±0.5µs
61.331±0.5µs
63.556µs
20(283) line
21(284) line
22(285) line
Fig. 1 CLOSED CAPTION WAVEFORM
6
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
CGMS (IEC 1880) Encoding
shown in fig. 2 and then inserted in TV line 20/283, according to the
In the NTSC (525/60) mode, the 20-bit data, consisting of 14-bit
register data of CGMS control mode (CGMS on/off).
data including CRCC code and 6-bit error correction code
The transferred data are loaded to the register on the trailing edge
generated by the input data, are converted into the video format
of V-sync, after a write-enable (WE) was set to "1".
Ref Bit
70±10 IRE
bit 20
bit 19
bit 18
bit 17
bit 16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
CRCC
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
Color
Burst
bit 2
bit 1
Input Data
2.232±50µs
49.1±0.3µs
11.2±0.3µs
63.556µs
19(282) line
21(284) line
20(283) line
Fig. 2 CGMS WAVEFORM
WSS (ETS 300 294) Encoding
control mode (WSS on/off).
In the PAL (625/50) mode, 14-bit data, set in the register, is
The new register data are loaded on the trailing edge of V-sync,
modulated to the signal format shown in fig. 3 and then will be
after a write-enable (WE) was set to "1".
inserted into TV line 23, according to the register data of WSS
"0"
Run in
Input Data
Start code
Color
Burst
11.0±0.25µs
group1
Aspect
Ratio
(4bit)
group2
group3 group4
Enhanced Subtit- Others
Services les
(3bit) (3bit)
(4bit)
200±10ns
500mV±5%
200±10ns
1F1C71C7 1E3C1F
"1"
27.4±1.4µs
64.0µs
22 line
23 line
Fig. 3 WSS WAVEFORM
7
24line
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
Color Subcarrier Generation
◊Samples will then be sent to customer after MITSUBISHI's
32-bit accuracy color subcarrier is generated from 27-MHz clock
confirmation of it.
signal according to the register data.
The subcarrier frequencies are as follows;
Sales Orders
◊ In case the customer has a Macrovision license:
M-fsc mode=455fH/2
=3.579545MHz±10Hz
The customer provides MITSUBISHI Electric Corp. with a written
B-fsc_1 mode =1135fH/4
confirmation of the license.
=4.43359375±5Hz
Customer can then purchases M65675FP.
◊ In case the customer does not have a Macrovision license:
B-fsc_2 mode =1135fH/4+25Hz
=4.43361875±5Hz
The customer must obtain a license or waiver from Macrovision.
Note:The above carrier frequencies are based on the input clock frequency of
The customer must provide MITSUBISHI Electric Corp. with a
27.0MHz. So, the generated subcarrier is also fluctuated according to a drift
written confirmation of the license or waiver from Macrovision.
of the external clock frequency.
Customer can then purchases M65675FP.
Interpolation
The 13.5MHz data of Y, U and V are processed by an avarage-value
interpolation and then each data rate are increased up to two times
that of 27.0MHz.
Synchronization Control
Sync Signal Processing
The H/V sync signals are available in following 3 conditions; (1) in
synchronization with external sync signal, (2) in a slave mode which
refers to a digital blanking code and (3) in a master mode which
Chroma modulation
The selected subcarrier frequency, which generated 27.0MHz rate
U and V signals, is modulated.
refers to a internally generated sync signal, according to the
register data. The timing specifications in each modes are as
follows;
◊ The slave mode
Video Anticopy Signal Addition [2]
(Pseudo Sync/AGC/Back Porch Pulses)
H-sync input condition: 1H =63.555 - 1.5/+10ms (525/60)
=64.0 - 1.5/+10ms (625/50)
This applies to M65675FP only.
The several anticopy signals (Pseudo Sync/AGC/Back Porch
Pulses), in accordance with Macrovision Video anticopy processes
Rev.7.01 dated Sep. 6, 1996, are inserted into the appropriate
V-sync input condition : 1V =262.5H±10H (525/60)
=312.5H±10H (625/50)
Field condition
0H)
video signals according to the register data. (This applies to
Odd 1/4H£Vsync£3/4H (Typical Vsync=
M65675FP only)
1/2H)
◊ The master mode
Video Anticopy Signal Generation
H-sync generation condition: 1H =63.555±0.035ms (525/60)
This applies to M65675FP only.
Several anticopy signals in accordance with Macrovision anticopy
processes Rev. 7.01 dated Sep. 6, 1996 are added to Y/C output
signals according to the I2C register data.
For more information about Macrovision video anticopy processes,
=64.0±0.035ms (625/50)
V-sync generation condition : 1V =262.5H±1/4H (525/60)
= 312.5H±1/4H (625/50)
Field condition
Odd 1/4H£Vsync£3/4H (Typical
The video anticopy specification is provided to only those
Vsync=1/2H)
customers of MITSUBISHI Electric Corp. who have executed a
license or a non-disclosure agreement with Macrovision Corp.
Sample request and sales orders require the following procedure.
sales
&
marketing,ACP-PPV,
Timing Signal Generation
A number of internal timing signals are generated with the trailing
edge of sync signals (shown in 4.2.1) as reference. All signals can
In the case of the customers who have no license.
VP
: Even-1/4H<Vsync<1/4H (Typical
Vsync=0H)
please contact nearest MITSUBISHI Electric sales office.
◊Contact
: Even-1/4H<Vsync<1/4H (Typical Vsync=
Macrovision
Corporation.
be adjusted in 13.5MHz-step up to ±1.2ms with respect to the
reference sync signal.
Phone : USA (408) 743-8600
Fax : USA (408) 743-8610
◊Complete the appropriate agreement with Macrovision.
◊Then, inform to MITSUBISHI in writing that the agreement has
completed.
8
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
Composite-sync Generation
The timing-corrected c-sync signal, for an addition to the Y signal, is
generated in accordance with RS170A (NTSC) and CCIR (PAL)
standards, as shown in fig. 4.
IRE
133
100
90
peak level including chroma signal
white peak level
0H(reference point)
10.9±0.2µs
Equalizing pulse
0.714V
Serrated pulse
9.4±0.1µs
1.5±0.1µs
20
4
0
0.286V
set-up
7.5±2
40
±2
4.7±0.1µs
0.14±0.2µs
19 cycles
-40
0.14±0.1µs
0.14±0.2µs
0.14±0.2µs
0.14±0.2µs
9 cycles
2.3±0.1µs
27.1µs
4.7±0.1µs
31.7775µs
837
0
858
63 72
106127
0
31
429
460
cycle counts (13.5MHz)
cycle counts (13.5MHz)
31.7775µs
0
429
366
795
Fig. 4-1 NTSC HORIZONTAL SYNC SIGNAL (referred to EIARS170A)
IRE
133
peak level including chroma signal
white peak level
100
90
0H(reference point)
12±0.3µs
0.7V
Equalizing pulse
5.6±0.1µs
50
Serrated pulse
1.5±0.3µs
10
0
4.7±0.2µs
43
±10%
set-up
0-2
0.3V
0.2±0.1µs
-43
10±1cycles
0.2±0.1µs
0.3±0.1µs
844
0
864
0.2±0.1µs
0.2±0.1µs
0.2±0.1µs
2.35±0.1µs
27.3µs
62.0µs
63 76
107142
cycle counts (13.5MHz)
0
32
432
464
cycle counts (13.5MHz)
4.7±0.2µs
62.0µs
0
432
368
800
Fig. 4-2 PAL HORIZONTAL SYNC SIGNAL (referred to CCIR)
Serial Interface
data. The stored data will be loaded to the registers in each internal
The M65675FP/M65676FP has a serial data receiver, in
blocks at the timing of the first trailing edge of V-sync after the
compliance with both typical and high speed modes, based on I 2C
transmission flag (WE) have been set up.
serial bus specification. The slave-address of it also responds to
following procedure;
Analog Blocks
D-A Converter
address setting pin DVASEL (pin 3) is "L" and "H" for the address of
The M65675FP/M65676FP has two 10-bit D-A converters. A
40h and 42h, respectively.
reference current of the D-A converters is supplied directly through
The serial data are stored in the data register in the serial interface
the Yref and Cref pins. The power save mode cuts the circuit
block according to the appointed address after the receipt of the
current. The maximum output amplitude is 1.2V P-P.
two addresses of 40h and 42h. The address setting is done by
9
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
Y and C Mixing Circuit
The analog outputs of D-A converters are filtered and then input to
Operating Description
Initialize
the M65675FP again. The Y and C signals, whose maximum
After power-on, the M65675FP/M65676FP has two different
amplitude is 0.6VP-P, are combined and the resulting composite
initialize sequences in the master and slave modes, respectively.
signal (CVBS) is output. The maximum amplitude of CVBS output is
In the master mode, the internal registers are initialized responding
1.2VP-P.
to the reset signal. After reset, the serial registers are set to the
default data and an internal control clock (13.5MHz) is generated
6-dB Amplifier
from the system clock.
The M65675FP has three 6-dB amplifiers. The maximum input is
In the slave mode, the internal registers are initialized the same as
0.6VP-P and the resulting maximum output will be 1.24V P-P. The
in the master mode. The serial registers are set up to the default
maximum drivability and band width are 1mA and 6MHz,
data and the system clock generates the internal control clock (13.5
respectively.
MHz) in the synchronization with the trailing edge of the horizontal
sync signal (H-sync), after reset. (Referring to Fig. 5)
In case the serial registers are set up to data other than the default
ones, the data should be renewed according to the I 2C bus format
in both the master and slave modes, after reset.
·In the master modeÒ
System clock
(27.0MHz)
Reset
H-sync
Generation starting timing
of reference clock
·In the slave modeÒ
System clock
(27.0MHz)
Reset
H-sync
Generation starting timing
of reference clock
Fig. 5 GENERATION STARTING TIMING OF INTERNAL REFERENCE CLOCK
10
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
Serial Register
The serial address register can be addressed by I 2C bus.
In the actual use, one of two is selected and then Pin 3 (DVASEL)
The M65675FP/M65676FP has two slave addresses, 40 and 42h.
is set according to the selected address data
Slave address=40h
42h
bit7
0
0
bit6
1
1
bit5
0
0
bit4
0
0
bit3
0
0
3
2
Color
Bar
bit2
0
0
bit1
0
1
bit0
R/W
R/W
Register Mapping and Description
sub
address
00
01
02
03
04
05
06
07
08
09
0A
0B
data
Function
7
6
5
Write control
WE
P-save
UVin
Interface
525/
625
NTSC/
PAL YC/UV
CC1F
sync7
Sync level
Burst level
Sync delay
Y delay
TINT
YCINV CbCrINV
1
SCH
offset
Setup1 Setup0
CC2F
sync6
CCI/F
sync5
CCD1
sync4
CCD0
sync3
CCIR1 CCIR0
sync2 sync1
burst6
burst5
TINT6
CC106
CC116
CC206
CC216
CG08/ CG07/
WS07 WS06
TINT5
CC105
CC115
CC205
CC215
CG06/
WS05
CG14/
WS13
burst4
SD4
YD4
TINT4
CC104
CC114
CC204
CC214
CG05/
WS04
CG13/
WS12
burst2
SD2
YD2
TINT2
CC102
CC112
CC202
CC212
CG03/
WS02
CG11/
WS10
BLD
mode
CTY02
CTB02
CTR02
CTY22
CTB22
CTR22
CTY42
CTB42
CTR42
CTY62
CTB62
CTR62
N0 [2]
0
CGMS
/WSS
sync0
CTY12
CTB12
CTR12
CTY32
CTB32
CTR32
CTY52
CTB52
CTR52
CTY11
CTB11
CTR11
CTY31
CTB31
CTR31
CTY51
CTB51
CTR51
CTY10
CTB10
CTR10
CTY30
CTB30
CTR30
CTY50
CTB50
CTR50
Mode selection
N16 [0] N0 [6]
N0 [5]
N0 [4]
burst3
SD3
YD3
TINT3
CC103
CC113
CC203
CC213
CG04/
WS03
CG12/
WS11
OSD
CLK
CTY03
CTB03
CTR03
CTY23
CTB23
CTR23
CTY43
CTB43
CTR43
CTY63
CTB63
CTR63
N0 [3]
1C
Color Stripe
Definition #1
N21 [1] N21 [0] N1 [5]
N1 [4]
N1 [3]
N1 [2]
N1 [1]
N1 [0]
1D
Color Stripe
Definition #2
N2 [5]
N2 [4]
N2 [3]
N2 [2]
N2 [1]
N2 [0]
Color Stripe
Definition #3
N3 [5]
N3 [4]
N3 [3]
N3 [2]
N3 [1]
N3 [0]
N4 [6]
N4 [5]
N4 [4]
N4 [3]
N4 [2]
N4 [1]
N4 [0]
N7 [0]
N6 [2]
N6 [1]
N6 [0]
N5 [2]
N5 [1]
N5 [0]
TINT7
Closed Caption (1st field)
Closed Caption (2nd field)
0C
CGMS/WSS
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1E
11
4
OSD control
CLTEN
CTY13
CTB13
CTR13
CTY33
CTB33
CTR33
CTY53
CTB53
CTR53
Color Lookup Table
∗1
Macrovision
1F
Color Stripe
Definition #4
20
Color Stripe
Definition #5/6/7
N7 [1]
burst1
SD1
YD1
TINT1
CC101
CC111
CC201
CC211
CG02/
WS01
CG10/
WS09
burst0
SD0
YD0
TINT0
CC100
CC110
CC200
CC210
CG01/
WS00
CG09/
WS08
BLD1
BLD0
CTY01
CTB01
CTR01
CTY21
CTB21
CTR21
CTY41
CTB41
CTR41
CTY61
CTB61
CTR61
N0 [1]
CTY00
CTB00
CTR00
CTY20
CTB20
CTR20
CTY40
CTB40
CTR40
CTY60
CTB60
CTR60
N0 [0]
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
Register Mapping and Description (cont.)
sub
address
data
Function
5
4
3
2
1
0
21
Pseudo-sync
parameter #1
N8 [5]
N8 [4]
N8 [3]
N8 [2]
N8 [1]
N8 [0]
22
Pseudo-sync
parameter #2
N9 [5]
N9 [4]
N9 [3]
N9 [2]
N9 [1]
N9 [0]
23
Pseudo-sync
parameter #3
N10 [5] N10 [4] N10 [3] N10 [2] N10 [1] N10 [0]
24
25
26
27
28
7
Pseudo-sync/AGC
pulse line select
Pseudo-sync/AGC
pulse A/B select
∗1
Macrovision
29
6
N11 [7] N11 [6] N11 [5] N11 [4] N11 [3] N11 [2] N11 [1]
N11 [14] N11 [13] N11 [12] N11 [11] N11 [10] N11 [9]
N12 [7] N12 [6] N12 [5] N12 [4] N12 [3] N12 [2] N11 [1]
N12 [14] N12 [13] N12 [12] N12 [11] N12 [10] N12 [9]
N11 [0]
N11 [8]
N12 [0]
N12 [8]
Pseudo-sync/AGC
on/off FormatA
N13 [7] N13 [6] N13 [5] N13 [4] N13 [3] N13 [2] N13 [1] N13 [0]
Pseudo-sync/AGC
on/off FormatB
N14 [7] N14 [6] N14 [5] N14 [4] N14 [3] N14 [2] N14 [1] N14 [0]
Back Porch pulse
N15 [7] N15 [6] N15 [5] N15 [4] N15 [3] N15 [2] N15 [1] N15 [0]
configuration
Start to 1st/1st to 2nd
N18 [3] N18 [2] N18 [1] N18 [0] N17 [3] N17 [2] N17 [1] N17 [0]
Phase Switch Point
2A
2B
2C
2nd to End Phase
Switch Point/
Subcarrier Phase
2D
Colorstripe line
phase
N20 [2] N20 [1] N20 [0] N19 [3] N19 [2] N19 [1] N19 [0]
N21 [9] N21 [8] N21 [7] N21 [6] N21 [5] N21 [4] N21 [3] N21 [2]
*1 : These registrs are M65675FP only
Register Functional Description
Sub
address
Name
WE
P-save
UVin
00
Y/CINV
Cb/CrINV
Color Bar
525/625
NTSC/PAL
01
YC/UV
SCH
Function
Register Write Enable
"0" write disable
"1" write enable
Power Down Control
"0" power down "off"
"1" power down "on"
Input Video Data Format Selection
"0" Y/U/V input
"1" Y/Cb/Cr input
Pixel Data Sep. Timing Control (Y/C)
"0" Y/C separation in inverted timing
"1" Y/C separation in non-inverted timing
Pixel Data Sep. Timing Control (Cb/Cr)
"0" Y/C separation in inverted timing
"1" Y/C separation in non-inverted timing
Color Bar Generation Control
"0" color bar generation "off"
"1" color bar generation "on"
Input Pixel Data Field Frequency Setting
"0" 525/60 field
"1" 625/50 field
Line Phase Inversion Control in V-axis
"0" Phase Inversion "off" (NTSC)
"1" Phase Inversion "on" (PAL)
Selection of DAC Output
"0" Y/C output
"1" U/V output
SCH Phase Control
"0" SCH Phase Control "on"
"1" SCH Phase Control "off"
Remark
Default
Data
20h
Color look-up table
should be initialized.
03h
12
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
Register Functional Description (cont.)
Sub
address
Name
offset
01
setup (1:0)
CGMS/WSS
CC1F
CC2F
02
CCI/F
CCD (1:0)
02
CCIR (1:0)
03
04
05
06
07
08
09
0A
0B
0C
:
0D
sync (7:0)
burst (6:0)
SD (4:0)
YD (4:0)
TINT (7:0)
CC10 (6:0)
CC11 (6:0)
CC20 (6:0)
CC21 (6:0)
CG (14:1)
[WS (13:0)]
CLTEN
0E
OSDCLK
BLD mode
13
0E
BLD (1:0)
0F
:
1A
1B
:
2D
CTY (00:63)
CTB (00:63)
CTR (00:63)
N0
:
N21
Function
fsc Offset Frequency (25Hz) Control
"0" offset no-addition
"1" offset addition
7.5IRE Setup Control
"00" setup "off"
"01" +7.5IRE setup
"1X" -7.5IRE setup
CGMS/WSS Generation Control
"0" CGMS/WSS generation "off"
"1" CGMS/WSS generation "on"
Closed Caption Data Transmission Flag in Field 1.
Closed Caption Data Transmission Flag in Field 2.
Closed Caption Interface Setting
"0" internal generation mode
"1" external input mode
Closed Caption Generation Setting
"00" generation "off"
"01" generation for only field 1
"10" generation for only field 2
"11" reserved
Input Pixel Data Format Setting
"00" CCIR656
"01" 8bit CCIR601
"10" 16bit CCIR601
"11" reserved
Sync Signal Output Level Setting
Burst Level Setting
Composite Sync Multiplexing Timing Setting
Luma Signal Delay Setting
Chroma Output TINT Control
1st Byte Data Setting for Field 1
2nd Byte Data Setting for Field 1
1st Byte Data Setting for Field 2
2nd Byte Data Setting for Field 2
Remark
It have to set "1"
in the setting of
525/625=0
It is active in the
setting of 525/625=0.
03h
CGMS/WSS
selection is depend
on 525/62 setting.
00h
DBh
54h
19h
04h
00h
00h
00h
00h
00h
CGMS or WSS Data Setting
CLT Data Renewing Enable
"0" disable
"1" enable
OSDCLK Frequency Setting
"0" 6.75MHz
"1" 13.5MHz
Blending Mode Setting
"0" Y and C are mixing
"1" Only Y is mixing
Blending Color Address Setting
"00" blending "off"
"01" CLT0 is set for a blending color
"10" CLT(1:0) is set for a blending Color
"11" CLT(2:0) is set for a blending color
Default
Data
00h
00h
00h
In the case of "1",
C is equal to the
OSD setting color.
00h
00h
Color Look-up table RAM Setting
00h
Macrovision Setting
00h
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
DESCRIPTION OF PIN
Pin No.
1
Pin name
DVSS2
Type
Supply Digital ground for I/O.
Function
2
PXCLK
O
Reference clock for pixel data input.
The clock frequency is 27.0MHz or 13.5MHz in CCIR656/8-bit CCIR601 or 16-bit CCIR601 input
mode, respectively.
3
DVASEL
I
I2C slave address setting.
"Low" is for the slave address of 40h.
"High" is for the slave address of 42h.
4
HD
I/O
Horizontal sync signal.
It is an input or output in the slave or master mode, respectively.
5
VD
I/O
Vertical sync signal.
It is an input or output in the slave or master mode, respectively.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VD9
VD8
VD7
VD6
VD5
VD4
VD3
VD2
VD1
VD0
DVSS2
DVDD2
DVDD1
DVSS1
I/O
Video data inputs.
The input video data are the luma (Y) data as defined in CCIR Rec 601 in 16-bit CCIR601 mode.
In the Y/U/V output mode, the output is 10-bit luma signal with a composite sync.
In 16-bit CCIR601 mode, an MSB and LSB is VD7 and VD0, and in the Y/U/V output mode, VD9 and
VD0, respectively.
20
OSDCK
21
OSD0
22
23
OSD1
OSD2
I
24
Master/Slave
I
25
26
27
28
RESET
ACK
SDA
SCL
29
TEST
30
31
32
DVDD1
N.C.
N.C.
33
C
34
N.C.
35
CVBS
36
AVSS2
37
Y
38
AVDD2
39
Yin
40
N.C.
41
Cin
Supply
Supply
Supply
Supply
O
I
O
I/O
I
Digital ground for I/O.
Digital positive supply for I/O.
Digital positive supply for internal logic.
Digital Ground for internal logic.
Reference clock for the external OSD microprocessor.
The frequency is 13.5MHz or 6.25MHz, alternated by I 2C bus control.
Color Look-up table address input.
MSB and LSB is OSD2 and OSD0, respectively.
Synchronizing mode selection.
"Low" is for the slave mode.
"High" is for the master mode.
Asynchronous reset, active "LOW".
Acknowledge line (Open drain output).
Serial data line/Acknowledge line (Open drain output).
Serial clock line.
Test mode control.
It should be grounded during actual use.
Supply Digital positive supply for internal logic.
No connection.
No connection.
I
The analog chroma output signal from 6-dB amplifier.
The output amplitude is 1.0VP-P (typ.), while the input one is 0.5VP-P.
No connection.
The analog composite video output signal from 6-dB amplifier.
O
The output amplitude is 1.24VP-P (typ.).
Supply Analog ground for 6-dB amplifiers.
O
The analog luma output signal from 6-dB amplifier.
The output amplitude is 1.2VP-P (typ.), while the input one is 0.6VP-P.
Supply Analog positive supply for 6-dB amplifiers.
O
I
I
The analog luma input from an external LPF.
This input has clamp circuit. The signal must input via capacitor.
No connection
The analog chroma input from an external LPF.
This input has bias circuit. The signal must input via capacitor.
14
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
DESCRIPTION OF PIN (cont.)
Pin No.
Pin name
Type
Function
Phase compensation for chroma or V D/A converters.
I
It should be connected to the analog ground via a capacitor.
Chroma or V signal output.
O
It should be connected to the analog supply via a resistor (RL).
The output amplitude is set up by reference resistor (Rref) and RL.
Supply Analog positive supply for D/A converters.
Supply Analog ground for D/A converters.
Luma or V signal output.
O
It should be connected to the analog supply via a resistor (RL).
The output amplitude is set up by reference resistor (Rref) and RL.
42
Ccomp
43
DAC
44
45
AVDD1
AVSS1
46
DAY
47
Cref
I
Reference current control for chroma or V D/A converter.
It should be connected to the analog supply via a reference resistor (Rref).
48
Yref
I
Reference current control for luma or U D/A converter.
It should be connected to the analog supply via a reference resistor (Rref).
49
Ycomp
50
51
52
N.C.
DVDD1
DVSS1
53
Xout
54
Xin
55
56
57
58
59
60
61
62
63
64
DVSS2
PXD7
PXD6
PXD5
PXD4
PXD3
PXD2
PXD1
PXD0
DVDD2
Phase compensation for luma or U D/A converters.
It should be connected to the analog ground via a capacitor.
No connection.
Supply Digital positive power supply for internal logic.
Supply Digital ground for internal logic.
I
O
System clock output.
It should be in no connection except that it is connected to a X'tal oscillator.
System clock input.
The clock frequency is 27.0MHz only.
Supply Digital ground for I/O.
I
I
Pixel data inputs.
The acceptable video data are;
multiplexed video data (Y/Cb/Cr) including timing reference code of SAV and EAV as defined in
CCIR Rec656, and multiplexed video data (Y/Cb/Cr) as defined in CCIR Rec601, and multiplexed
Color difference signals (Cb/Cr).
An MSB and LSB is PXD7 and PXD0, respectively.
Supply Digital positive power supply for I/O
Interface
M65675FP/M65676FP through PXDATA [7:0] ports synchronizing
The M65675FP/M65676FP has two interfaces as follows;
with a pixel clock (PXCLK) generated by the LSI. In the case of
Pixel data interface
CCIR601 16-bit serial data, 8-bit color difference signals (Cb/Cr or
OSD interface
U/V) and luma signal (Y) are taken into the LSI synchronizing with
pixel clock (PXCLK) through PXD [7:0] and VD [7:0] port,
Pixel Data Interface
respectively.
The M65675FP/M65676FP accepts these 6 digital pixel data
formats as shown below;
In CCIR656
CCIR656 pixel data are accepted in only the slave mode, while
CCIR601 ones are accepted in both the master and slave modes.
Y and Cb/Cr, in a digital video transmission format
In the case of CCIR656 pixel data, H/V sync and a field
Y and U/V, in a time multiplexed 8-bit serial data format
identification signals are regenerated internally referring to SAV and
In CCIR601
EAV code multiplexed in the pixel data. In the case of CCIR601
Y and Cb/Cr, in a digital video transmission format
pixel data, H/V sync and the field identification signals are
Y and U/V, in a time multiplexed 8-bit serial data format
regenerated internally, then the H and V sync signals are available
Y, in a digital video transmission format and time multiplexed
via HD and VD ports in the master mode operation, respectively.
Cb/Cr
Moreover, in the slave mode, the M65675FP/M65676FP is in the
Y and U/V, in a time multiplexed 16-bit serial data format
slave operation synchronized with H/V sync signals via HD/VD
ports and a field identification is done using the H/V sync input
The 8-bit serial data in CCIR656 and CCIR601 are taken into the
15
signals.
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
The pixel data interface pin assignment is shown in Table 1.
Table 1 Pixel Data Interface Pin Assignment
Pin name
I/O
Function
Pixel clock output.
In the case of CCIR656 / CCIR601 8-bit data and CCIR601 16-bit inputs, this will be a free-run clock of 27MHz and
13.5MHz, respectively.
Horizontal sync signal. Input in the slave or output in the master mode.
Vertical sync signal. Input in the slave or output in the master mode.
PXCLK
O
HD (Note1)
VD (Note1)
I/O
I/O
PXD [7:0]
I
Pixel data input.
8-bit data input in CCIR656 / CCIR601 or the color differential signals (Cb/Cr) input in CCIR601 16-bit data format.
PD [7:0]
I
Pixel data input.
Luma (Y) data input in CCIR601 16-bit data format.
Note1 : In CCIR656 mode, H sync and V sync generated by EAV will be output via terminals HD and VD, respectively.
OSD Interface
The OSD data, which are storaged in the address assigned by the
clock (OSDCK) delivered from the M65675FP/M65676FP.
color look-up table RAM (CLT-RAM) address data input via OSD
[2:0] ports, are multiplexed into the Y signal synchronizing with OSD
The OSD interface pin assignment is shown in Table 2.
Table 2 The OSD interface Pin assignment
Pin name
I/O
OSDCK
O
OSD [2:0]
I
Function
OSD clock output.
13.5MHz free-run clock or 6.25MHz H-start-and-stop clock.
Color look-up table RAM address input.
16
MITSUBISHI ICs (TV)
M65675FP/M65676FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DIGITAL NTSC/PAL ENCODER
APPLICATION EXAMPLE
220µF
C
CVBS
0.1µF 75Ω
75Ω
1kΩ
220µF 75Ω
Y
A typical application diagram of the M65675FP/M65676FP together with the M65773FP 1-chip MPEG2 decoder is shown in Figure 6.
2.2µF
0.1µF
2.2µF
Audio out (R)
Rch
M35041
DIN
LRCIN
BCKIN
XTI
Audio
DAC
HSYNC
VSYNC
8
PXD
PXCLK
BDER
CLK in
BCLK
BDEN
BDREQ
27MHz
XO
16M
SDRAM
Audio out (L)
OSD micro
computer
SCL
SDA/ACK
RESET
AO0
MPEG2
AO1
System/
AO2
Video/Audio
AO3
Decoder
M65773FP LRCLK
BD
47µF
0.01µF
VSS
VDD
Lch
SDA
SCL
3
R/G/B
OSC1
VDD
VSS
2.2µF
RESET
OSD(2:0)
OSDCK
ACK
HD
VD
PXD(7:0)
PXCLK
47µF
0.01µF
VD
HD
RESET
CS
SCK
SIN
M65675FP
M65676FP
DVDD
Y
C
CVBS
Y in
Yref
Digital
NTSC/PAL
Encoder
VD(9:0)
47µF
0.01µF
TEST
Master/Slave
DVASEL
DVSS
X out
X in
DAC
300Ω
C in 0.1µF
DAY
AVDD
AVss
Ccomp
Ycomp
Cref
47µF
0.01µF
27MHz
Filter
Stage
300Ω
2.2µF
2.2µF
0.1µF
10kΩ
0.1µF
10kΩ
Filter
Stage
75Ω
Driver
DOCLK
DACCLK
ACLKO
ACLKI
RESET
CS
SCK
SIN
BDER
RCLK
BDEN
BDREQ
BD
8
3.3kΩ
Chanel
Decoder
Host
CPU
: 3.3V Supply for Analog/Digital
(Note 1) Connect a tantalum or electrolytic capacitor of 10µF or more and a ceramic
capacitor of 0.01µF each in parallel between DVDD/AVDD and DVss/AVss pins.
These capacitors should be placed as possible to the device.
(Note 2) In case several LSIs are connected to an I2C bus, SDA and ACK at power-down
should be tied externally in a situation when only M65675FP/M65676FP is power-off.
Fig. 6 TYPICAL APPLICATION DIAGRAM
17
Units Resistance : Ω
Capacitance : F