M65677FP Digital NTSC/PAL Encoder REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Description The M65677FP encodes CCIR601 or CCIR656 format Y/Cb/Cr data into analog NTSC and PAL video signals, including Digital Signal Processing functions such as Closed Caption encoding. Overlay OSD, Anti Video Copy Processing Note1 e.t.c. It also includes peripheral processing function such as 10 bit DAC e.t.c., so that low cost and compact system can be realized. Features • • • • • • • • • • • • • • • • • Macrovision’s video anti copy process Rev 7.01 supported Note1 Overlay CGMS signal online 20/283 for 525/60 Note3 Generate CRCC for CGMS Signal Overlay WSS signal online 23 for 625/50 Note4 Color adjustment (TINT/color control) NTSC, B/G PAL or MPAL Video Outputs Component Y/C Video (S-Video) and CVBS or Y/U/V Outputs Supporting CCIR601 and CCIR656 format data Closed Caption Manager online 21/284 for NTSC Generate ODD parity for Closed Caption Manager H/V Sync and Composite generating Overlay Digital OSD Supporting Y/Cb/Cr 4:4:4 Over sampling Filter 2 ch 10 bit DAC and 3 ch 6 dB Amp Note2 3.3 V I/O interface I2C Bus Interface for Controls Power down mode Notes: 1. This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. The use of Macrovision Corporation's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-par-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. 2. 6 dB Amp max. output is 1.0 Vp-p 3. Copy Generation Management System-A (IEC1880) 4. Wide Screen Signaling (ETS300 294) Application DVB, DVD, Digital CATV, Video CD REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 1 of 8 REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 2 of 8 CCIR601 or 656 pixel data from MPEG decoder From/to MPEG decoder SCL SDA ACK Muster/ slave Serial interface SYNC processing Cr Y/U/V V Anti copy processing Encode CGMS/WSS manager Closed caption manager C/V Y/U DAC DAC Y/C MIX 6 dB 6 dB 6 dB DVDD2 (× 2) DVDD1 (× 2) DVSS2 (× 2) DVSS1 (× 2) RESET TEST CVBS C Y Video output VD OSDCK OSD interface OSD2 OSD1 OSD0 Cr Cb Y AVDD1 Y ref C ref Cb Y/Cb/Cr U Y AVDD2 HD Y Input interface Y Yin VD [9:0] PXD [7:0] OSD control I/F Cin Clamp & bias BPF LPF M65677FP Block Diagram AVSS2 DAY DAC AVSS1 From micro controller M65677FP Pin Arrangement 33 34 35 Y AVSS2 CVBS N.C. C 36 37 38 39 40 41 DAC Ccomp C in N.C. Y in AVDD2 42 43 44 45 46 19 63 18 64 17 TEST SCL SDA ACK RESET Master/slave OSD2 OSD1 OSD0 OSDCK DVSS1 DVDD1 DVDD2 HD VD VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 DVSS2 DVSS2 N.C. N.C. DVDD1 16 20 62 15 21 61 14 22 60 13 23 59 12 24 58 11 25 57 10 26 56 9 27 55 8 54 7 28 6 29 53 5 30 52 4 51 3 31 2 32 50 1 49 PXCLK DVASEL Ycomp N.C. DVDD1 DVSS1 X out X in DVSS2 PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0 DVDD2 47 48 Yref Cref DAY AVSS1 AVDD1 M65677FP NC: No connection (Top view) Outline: PRQP0064GA-A (64P6N-A) REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 3 of 8 M65677FP Pin Description Pin No 1 2 Pin Name DVSS2 PXCLK Type Supply O 3 DVASEL 4 HD I/O 5 VD I/O 6 7 8 9 10 11 12 13 14 15 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 I/O 16 17 18 19 20 DVSS2 DVDD2 DVDD1 DVSS1 OSDCK 21 22 23 OSD0 OSD1 OSD2 I 24 Master/Slave I 25 26 27 28 29 RESET ACK SDA SCL TEST 30 31 32 33 DVDD1 N.C. N.C. C Supply — — O 34 35 N.C. CVBS — O 36 37 AVSS2 Y Supply O 38 AVSS2 Supply I Supply Supply Supply Supply O I O I/O I I Function Digital ground for the I/O Reference clock for input pixel data. The clock frequency is 27.0 MHz I2C slave address setting. “Low” is for the address of 40h, “High” is for the address of 42h. Horizontal sync signal input or output. It is an input and output in the slave and master mode, respectively. Vertical sync input or output. Or Odd Even signal output. It is an input and output in the slave and master mode, respectively. Video data outputs. In the Y/U/V output mode, the output is the 10-bit digital luma signal with a composite sync. VD9 is MSB and VD0 is LSB. Digital ground for the I/O. Digital supply for the I/O Digital supply for the internal logic. Digital ground for the internal logic. The reference clock for an external OSD microcontroller. 2 The frequency is 13.5 MHz or 6.25 MHz, alternated by I C bus control. The color look-up table address input. MSB and LSB are OSD2 and OSD0, respectively. Synchronizing mode selection. “Low” is for the slave mode. “High” is for the master mode. Initializing reset. ”Low” is active. Acknowledge line (Open drain output). Serial data line/acknowledge line (Open drain output). Serial clock line. For testing. Is should be grounded during an actual use. Digital supply for the internal logic. No connection. No connection. The analog chroma output from a 6 dB amplifier. The output amplitude is 1.0 VP-P (Typ), while the input is 0.5 VP-P. No connection. The analog composite video signal from a 6 dB amplifier. The output amplitude is 1.24 VP-P (Typ). Analog ground for 6 dB amplifiers. The analog luma output from a 6 dB amplifier. The output amplitude is 1.2 VP-P (Typ), while input is 0.6 VP-P. Analog supply for 6 dB amplifiers. REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 4 of 8 M65677FP Pin Description (cont.) Pin No 39 Pin Name Yin Type I 40 41 N.C. Cin 42 Ccomp I 43 DAC O 44 45 46 AVDD1 AVSS1 DAY Supply Supply O 47 Cref I 48 Yrel I 49 Ycomp I 50 51 52 53 N.C. DVDD1 DVSS1 Xout — Supply Supply O 54 Xin 55 56 57 58 59 60 61 62 63 DVSS2 Supply PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0 I 64 DVDD2 Supply Function The analog luma input from an external LPF. This input has bias circuit. The signal must input via a capacitor. No connection. The analog chroma input from an external LPF. This input has bias circuit. The signal must input via a capacitor. Phase compensation for chroma or V output DAC. It should be connected to the analog ground via a capacitor. Chroma or V signal output. The DAC output should be connected to the analog supply via a load resistor (RL). The output amplitude is set up by reference resistor (Rref) and RL. Analog supply for DACs. Analog ground for DACs. Luma or U signal output. It should be connected to the analog supply via a load resistor (RL). The output amplitude is set up by reference resistor (Rref) and RL. — I A reference current source for chroma or V signal output DAC. It should be connected to the analog supply via a reference resistor (Rref). A reference current source for Y or U DAC. It should be connected to the analog supply via a reference resistor (Rref). Phase compensation for Y or U DAC. It should be connected to the analog ground via a capacitor. No connection. Digital supply for the internal logic. Digital ground for the internal logic. System clock output. It must be in no connection except for a connection to a X′tal oscillator. System clock input. The clock frequency is only 27.0 MHz. Digital ground for the I/O. I Pixel data inputs. The acceptable video data are; • Multiplexed video data (Y/Cb/Cr) including timing reference code of SAV and EAV, defined in CCIR Rec656 • Multiplexed video data (Y/Cb/Cr) defined in CCIR Rec601 MSB and LSB are PXD7 and PXD0, respectively. Digital supply for the I/O. Absolute Maximum Ratings Item Supply voltage Digital input voltage Digital output voltage Operating temperature Storage temperature Symbol VDD VI VO Ta Tstg REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 5 of 8 Min Limits Typ Max Unit –0.3 –0.3 –0.3 –20 –40 — — — +25 — 4.5 VDD + 0.3 VDD + 0.3 +75 +125 V V V °C °C M65677FP Recommended Operating Condition (Ta = 25°C, DVDD = AVDD = 3.3 V, DVSS = AVSS = 0 V, unless otherwise noted) Item Supply Digital supply voltage Analog supply voltage Digital current consumption Analog current consumption Digital input Input voltage Input leakage current Input capacitance Digital output Output voltage Output capacitance I2C Bus Output current Output leakage current (off) Min Limits Typ Max Unit DVDDX AVDDX DIDD AIDD 3.0 3.15 0 0 3.3 3.3 — — 3.6 3.45 45 55 V V mA mA VIL VIH IIL/IIH 0 2.5 — — — — 0.8 3.6 15 V V µA CI — 7 15 pF VOL VOH CO — 3.25 — — — 7 0.05 — 15 V V pF DVDD = 3.3 V, |IO| < 1 A IO IOZ 4.0 — — — — 15 mA µA DVDD = 3.0 V, VIL = 0.4 V Symbol D/A converter Resolution Integral non-linearity error Differential non-linearity error Maximum output amplitude 6-dB amplifier Bias resistor Output gain (Y/C) Output Gain (CVBS) Input dynamic range Output dynamic range Yin clamp charge current Yin clamp discharge current Yin clamp discharge current Res INL DNL VfsMAX — — — 1.5 10 — — — — 2.0 1.0 — Bit LSB LSB Vp-p Rbias GV_YC GV_CV DRin DRout Iyich Iyids Ryicl 7.5 5.50 5.10 0.8 1.6 –12 0.26 20 10.0 6.00 6.00 — — –26 0.65 0.65 11.5 6.50 6.85 — — –50 1.80 70 kΩ dB dB Vp-p Vp-p µA µA — Yin input clamp voltage Vyicl 0.45 0.50 0.55 V Yin output clamp voltage CVBS output clamp voltage Cin input bias voltage C output bias voltage Output current Vyocl Vcvcl Vcin Vcob Iamp 0.40 0.30 0.95 0.90 1.00 0.50 0.50 1.00 1.00 — 0.60 0.70 1.05 1.10 — V V V V mA REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 6 of 8 Test Conditions DVDD = 3.0 V DVDD = 3.6 V DVDD = 3.0 V, VI = 0 V or VI = 3.6 V f = 1 MHz, VDD = 0 V f = 1 MHz, VDD = 0 V DVDD = 3.6 V, VI = 0 V or VI = 3.6 V Iyich Ryicl = – Iyids M65677FP Application Example 220 µF C 0.1 µF 75 Ω Y 220 µF 75 Ω + 75 Ω CVBS (CCIR656 I/F, Y/C/CVBS Output Mode) + 0.1 µF 2.2 µF 2.2 µF CLK in SCL SDA/ACK RESET MPEG2 System/ Video/Audio decoder M65773FP AO 0 AO 1 AO 2 AO 3 LRCLK BDER BCLK BDEN BDREQ ACLKI 3.3 kΩ BDER RCLK BDEN BDREQ BD Channel decoder : 3.3 V Power supply for analog/digital RESET CS SCK SIN BD ACLKO 8 16 M SDRAM DOCLK DACCLK REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 7 of 8 Audio out (R) Audio DAC DIN LRCIN BCKIN XTI HD VD VSYNC HSYNC PXD + 27 MHz XO VDD PXCLK 0.01 µF 47 µF VSS Audio out (L) OSD micro computer M35041 Lch VSS OSC1 Rch 3 R/G/B VD HD RESET CS SCK SIN SDA SCL PXCLK PXD (7:0) OSDCK ACK 8 VD (9:0) OSD (2:0) VDD 3.3 kΩ 0.01 µF RESET Digital NTSC/PAL encoder M65677FP + 47 µF C CVBS Y 200 Ω 2.2 µF Y in DAY 200 Ω 0.1 µF C in 10 kΩ DAC Yref 0.1 µF Cref + 0.1 µF AVDD AVSS Ccomp Ycomp 0.01 µF X out X in 27 MHz 47 µF + DVDD + TEST Master/slave DVASEL DVSS + 47 µF 0.01 µF Filter stage + 10 kΩ 75 Ω Driver Filter stage Host CPU M65677FP Package Dimensions JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GA-A Previous Code 64P6N-A MASS[Typ.] 1.1g HD *1 D 48 33 49 32 *2 E HE NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 17 1 ZD ZE Reference Symbol 64 16 c A2 Index mark A A1 F L Detail F e y D E A2 HD HE A A1 bp c *3 b p REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 8 of 8 e y ZD ZE L Dimension in Millimeters Min Nom Max 13.8 14.0 14.2 13.8 14.0 14.2 2.8 16.5 16.8 17.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0° 10° 0.65 0.8 0.95 0.10 1.0 1.0 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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