CXD1217M Synchronizing Signal Generator for Video Camera Description The CXD1217M is a synchronizing signal generator for color video cameras. 28 pin SOP (Plastic) Features • Compatible with the respective systems, NTSC, PALM, PAL and SECAM • Output is synchronized with the clock of 910fH or 908fH • 25Hz offset processing by PAL system • Color framing by the respective systems, NTSC, PALM and PAL • Possible external synchronization by H reset, V reset and line alternate reset pins Applications Synchronizing signal generator for color video cameras Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr –20 to +75 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89626A79-PS CXD1217M Block Diagram and Pin Configuration 4fscIN 10 INT-NTSC 1/4 PALM 4fscOUT 9 1/9 1/101 CLOCK ELIMINATION 2fH 1/7 VSS 14 1/81 1/2 fH PALM OSC INTNTSC 1/625, 1/525 fv/2 fv/8 1/4 PAL PAL PAL fH 1/625 1/525 PAL PALM VDD 28 19 fH SC RESET PHASE COMPARISON 24 HCOMOUT FIELD 1 RESET TEST 16 CLIN 26 1/4 SC RESET CLOUT 25 MODE2 22 HRI 23 VRI 1 1/2 DECODE EXT 20 LALTRI 15 1/625, 1/525 2fH LINE ALTERNATE RESET fH COMPOSITE SIGNAL CONTROL F.F. OUTPUT F.F. 1/454, 1/455 MODE1 21 2 OFLD1 5 OFLD 7 OLALT 3 OBF/COLB 6 OBLK 4 OSYNC HORIZONTAL RESET 12 OVD VERTICAL RESET 27 OFH 8 OHD 17 O2FH Note) Pin 19 output is (a) a signal based on Pin 26 in INT mode at NTSC. (b) each signal is based on Pin 10 in other modes. –2– CXD1217M Pin Description Symbol Pin No. I/O Description 1 VRI I Vertical reset signal 2 OFLD1 O First field output 3 OBF/COLB O Burst flag/color blanking output 4 OSYNC O Composite sync output 5 OFLD O Even and Odd output 6 OBLK O Composite blanking output 7 OLALT O Line alternate output 8 OHD O Horizontal drive output 9 4fscOUT O 4fsc output 10 4fscIN I 4fsc input 11 NC — 12 OVD O 13 NC — 14 VSS — 15 LALTRI I Line alternate reset input 16 TEST I Test input 17 O2FH O 2fH output (Double the frequency of Pin 27) 18 NC — 19 OSC O Sub carrier output 20 EXT I Internal and external synchronizing modes switchover L: Internal synchronization H: External synchronization 21 MODE1 I System selecting input 1 22 MODE2 I System selecting input 2 23 HRI I Horizontal reset input 24 HCOMOUT O Phase comparator output 25 CLOUT O Clock output 26 CLIN I Clock input 27 OFH O Horizontal frequency output 28 VDD — Power supply pin Vertical drive output GND pin –3– CXD1217M Electrical Characteristics DC characteristics Item Output voltage 1 Output voltage 2∗1 Output voltage 3∗2 Input voltage (VDD = 5V ± 10%, VSS = 0V, Topr = –20 to +75°C) Symbol Min. Conditions VOH IOH = –2mA VOL IOL = 4mA VOH IOH = –4mA VOL IOL = 4mA VOH IOH = –4mA VOL IOL = 8mA Typ. Max. Unit VDD – 0.5 VDD V VSS 0.4 V VDD – 0.5 VDD V VSS 0.4 V VDD/2 V VDD/2 VIH 0.7VDD V VIL Input current∗3 (Pull-down pin) IIH VIH = VDD Output leak current∗1 ILZ At high impedance Power current supply IDD At output pin in no-load Feedback resistance∗4 RFB VDD = 5V ∗1 ∗2 ∗3 ∗4 20 V 50 0.3VDD V 120 µA ±30 nA 8 mA 250k 2.5M Ω HCOMOUT pin 4fscOUT and CLOUT pins LALTRI, TEST, EXT, MODE1 and MODE2 pins 4fscOUT, 4fscIN, CLOUT and CLIN pins I/O capacitance Item (VDD = VI = 0V, fM = 1MHz) Symbol Conditions Min. Typ. Max. Unit Input pin CIN — — 9 pF Output pin COUT — — 11 pF –4– CXD1217M Description of Operation (See Block Diagram.) The CXD1217 is applicable to four systems; namely, NTSC, PAL, PALM and SECAM. In order to realize them, the following relative equations of Sub-carrier (4fsclN) and Clock (CLIN) are adopted . Sub carrier Clock NTSC 4fsc = 910fH 910fH PAL 4fsc = 1135fH + 2fv 908fH PALM 4fsc = 909fH 910fH SECAM — 908fH As it is obvious from the above equations, the 4fsc and clock frequency do not coincide with each other in the PAL and PALM. Therefore matching of the clock frequency is carried out by providing PLL. 1 . MODE specified input The CXD1217 provides four inputs to specify the respective modes. ∗ EXT input: Set this pin to VDD side, and it becomes into external synchronizing mode. At this time, the counters in connection with the PLL Ioop as shown in the upper part of the block diagram become into stand still state. ∗ MODE1 and MODE2 inputs: These are inputs for the system selection. MODE1 MODE2 System 0 0 NTSC 0 1 SECAM 1 0 PALM "0" → VSS 1 1 PAL "1" → VDD ∗ TEST input: An input to be used to measure IC. This input is normally kept opened. (Because it is dropped internally to Vss with MOS resistance.) 2. Reset operation The CXD1217 has three reset inputs ; namely, HRI, VRI, LALTRI, and it works to perform reset operation when it detects falling edge. These three inputs are so designed as to take in synchronization with the IC internal clock. Therefore, it is a prerequisite that both systems should have clock frequencies that are matched as a reset operation to each other (GEN Iocked). • H reset (HRI input) When the HRI input is continuous with H synchronization, resetting is activated with the initial falling edge, and for the subsequent edges they do not have to be reset unless they are deviated more than 2-bit (140ns) against the initial edge in the internal clock. That is, if the jitter of HRI input is less than 140ns, it is absorbed. The minimum resetting pulse width is over 0.3µs. The phase to be reset is the advanced point of 6.3 to 6.37µs (= 90 to 91-bit × 70ns) than the HRI input as shown in the diagram below. HRI input CXD1217 HD OUT output Reset –5– 6.3 to 6.37 [µs] CXD1217M • V reset (VRI input) When the VRI is input as shown in figure below, OSYNC can be reset at the same phase with the SYNC signal. Counter State 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SYNC Signal Falling edge permitted span a VRI Rising edge is to be behind from point a AA AA CXD1217 internal clock (2fH) (See Timing Chart Diagram) V reset pulse 9 After reset SYNC OUT 10 11 12 13 14 Reset State Since the falling edge point in the diagram above (marked with ↑) is the boundary of reset, if the falling edge of the VRI input traverses that point, it causes 1/2H deviation to the reset state. Accordingly, if resetting is applied between two similar systems whose frequency are different, the V to which resetting is applied generates jitter of 1/2H. (When the resetting is applied continuously.) • LALT reset (LALTRI input) Phase relation between LALTRI pulse polarity and 2fH is the same as in the case of V resetting. Resetting operation is basically required only in the external synchronizing mode (GEN LOCK mode). However, even in the internal synchronizing mode, it sometimes requires H and V outputs whose phases are deviated against a certain output. In that case, it suffices to use two CXD1217s and conduct the operation as follows: Clock VRI2 CXD1217 OHD1 CXD1217 VRI2 OHD2 OVD2 OVD1 Input Shift Reg. Output Clock Delay ∗ It suffices to set IC-1 and IC-2 into INT mode. By varying the Delay and Shift Reg. of the above diagram, any phases of OHD2 and OVD2 can be provided against the respective OHD1 and OVD1. 3. Color framing In the case of internal synchronization in the individual NTSC, PAL and PALM systems, the phase relationships between SYNC of the 1st field and sub-carrier are kept stable regardless of the power supply being ON or OFF. However, as the PAL and PALM systems are comprised of PLL, the absolute values concerning the phase according to variation of the ambient temperature drifts. –6– CXD1217M Timing Chart Output Timing Chart Diagram CXD1217 NTSC, PALM Field 1 ODD 2 EVEN SYNC OUT 3 ODD 4 EVEN 12H Field 1 2 BF/COLB OUT (PALM) 3 4 Field 1 2 LALT OUT (PALM) 3 4 10H ODD BF/COLB OUT (NTSC) EVEN ODD HD OUT EVEN 20H ODD BLK OUT EVEN 9H VD OUT ODD FLD OUT EVEN FLD1 OUT (fv/4) (NTSC) 3H FLD1 OUT (fv/8) (PALM) 3H CLIN (NTSC) Field 1 Field 1 4fscIN (PALM) SC OUT –7– CXD1217M CXD1217 PAL, SECAM Field 4 EVEN 1 ODD SYNC OUT 2 EVEN 3 ODD 10H Field 4 1 BF/COLB OUT (PAL) 2 3 Field 4 1 LALT OUT (PAL) 2 3 9H BF/COLB OUT (SECAM) 9H 7H EVEN 9H 8.5H 7H ODD EVEN HD OUT ODD 25H EVEN BLK OUT ODD 7.5H OVD EVEN FLD OUT ODD FLD1 OUT (fv/8) (PAL) 2.5H FLD1 OUT (fv/4) (SECAM) 2.5H 4fscIN (PAL) SC OUT –8– –9– LALT FLD1 FLD VD 2fH (Internal clock) H. R. VSYNC EQ BF HSYNC HBLK fH HD/CBLK CXD1217 fH P140 N141 P66 N68 P22 N22 P139 N140 P90 N90 P34 N32 1 H 2 P420 N423 P454 N455 P145 N145 P388 N387 P315 N315 P32 N36 P169 N169 P78 N76 P66 N68 P169 N154 P96 N96 H P: PAL SECAM N: NTSC PALM Numerical figures show number of clocks P908 N910 CXD1217M CXD1217M Application Circuit Basic connection in individual systems Basic connection in individual systems at internal synchronization mode (EXT input = "0") is as follows. See waveform diagram for each output. • NTSC 14.318MHz ( = 910fH) 19 OSC VDD 28 VDD 26 25 CLOUT CLIN 14 VSS HRI Synthesizer 27 17 12 8 6 4 OFLD OLALT 5 7 3 23 1 OFLD1 VRI OBF/COLB OBLK OVD OHD 4fscOUT 9 10 OFH 4fscIN O2FH OLALT OSYNC 1/4 2 ∗ H/2 is output for LALT OUT even in NTSC mode. ∗ MODE1, MODE2, EXT, TEST and LALTRI pins can be kept open. (If noise annoys, connect to Vss by low impedance.) • PAL 14.187MHz ( = 908fH) L. P. F VCO VDD OSC 10k 19 10 4fsc IN 26 CLIN 24 HCOMOUT 25 CLOUT 28 VDD 14 VSS 10k 21 22 MODE1 MODE2 1/4 Phase Comparison HRI 1/2 OVD OHD O2FH 1/625 OFH Field 1/8 17 27 8 12 4 6 3 7 5 23 1 OFLD1 1/81 OFLD S. C. Reset 1/7 OBF/COLB Clock Elimination VRI OLALT 4fsc OUT Synthesizer OBLK 17.734MHz (4fsc) fH f'H OSYNC 9 2 ∗ Inverter of CLIN or CLOUT pins are usable as VCO. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXD1217M • PALM 14.318MHz ( = 910fH) L. P. F VCO VDD OSC 10k 19 10 4fsc IN 26 CLIN 24 HCOMOUT 25 CLOUT 28 VDD 14 VSS 21 MODE1 1/4 Phase Comparison HRI 6 17 27 8 12 4 3 7 23 1 OFLD1 OLALT VRI OFLD OBF/COLB Field 1 OBLK 1/525 OSYNC 1/8 OVD 1/101 OHD S. C. Reset 1/9 Synthesizer OFH 14.302MHz (4fsc) 4fsc OUT O2FH 9 fH f'H 5 2 ∗ Internal inverter is usable as VCO. • SECAM VDD 14.187MHz ( = 908fH) 10k 25 CLOUT 28 VDD 14 VSS 26 CLIN 22 MODE2 4fscIN 10 HRI Synthesizer 17 27 8 12 4 6 3 7 23 1 OFLD1 OFLD OLALT OBF/COLB OBLK OSYNC OVD OHD OFH O2FH 9 VRI 5 2 ∗ COLB is output to BF/COLB OUT pin. ∗ SDR and SDB are formed in PLL using 908fH. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 11 – CXD1217M Package Outline Unit: mm 28PIN SOP (PLASTIC) + 0.4 18.8 – 0.1 + 0.4 2.3 – 0.15 28 15 1 14 0.45 ± 0.1 0.24 1.27 + 0.2 0.1 – 0.05 0.5 ± 0.2 9.3 10.3 ± 0.4 + 0.3 7.6 – 0.1 0.15 + 0.1 0.15 – 0.05 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE EPOXY RESIN SOP-28P-L02 LEAD TREATMENT SOLDER PLATING SOP028-P-0375 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.6g – 12 –