BSI Very Low Power/Voltage CMOS SRAM 64K X 16 bit FEATURES • Wide Vcc operation voltage : 2.4 ~ 5.5V • Very low power consumption : Vcc = 3.0V C-grade : 22mA (@55ns) operating current I- grade : 23mA (@55ns) operating current C-grade : 17mA (@70ns) operating current I- grade : 18mA (@70ns) operating current 0.4uA (Typ.) CMOS standby current Vcc = 5.0V C-grade : 48mA (55ns) operating current I- grade : 50mA (55ns) operating current C-grade : 36mA (70ns) operating current I- grade : 38mA (70ns) operating current 1.3uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible BS616LV1011 • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin DESCRIPTION The BS616LV1011 is a high performance , very low power CMOS Static Random Access Memory organized as 65,536 words by 16 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.4uA at 3V/25oC and maximum access time of 55ns at 3V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable(OE) and three-state output drivers. The BS616LV1011 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV1011 is available in the JEDEC standard 44-pin TSOP Type II and 48-pin BGA package. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE BS616LV1011EC O O +0 C to +70 C BS616LV1011AC BS616LV1011EI O O -40 C to +85 C BS616LV1011AI PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 A LB BS616LV1011EC BS616LV1011EI 2 OE 3 A0 4 A1 5 A2 Vcc RANGE POWER DISSIPATION STANDBY Operating SPEED (ns) (ICCSB1, Max) PKG TYPE (ICC, Max) 55ns:2.8~5.5V 70ns:2.5~5.5V Vcc=5.0V Vcc=3.0V Vcc=5.0V 70ns Vcc=3.0V 70ns 2.4V ~ 5.5V 55/70 4uA 1.3uA 36mA 17mA 2.4V ~ 5.5V 55/70 8uA 2.5uA 38mA 18mA TSOP2-44 BGA-48-0608 TSOP2-44 BGA-48-0608 BLOCK DIAGRAM 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC A8 A13 A15 A14 A12 Address A7 Buffer Input A6 A5 A4 16 DQ0 . . . . NC . . . . UB A3 A4 CE IO0 C IO9 IO10 A5 A6 IO1 IO2 D VSS IO11 NC A7 IO3 VCC E VCC IO12 NC NC IO4 VSS IO14 IO13 A14 A15 IO5 IO6 G IO15 NC A12 A13 WE IO7 H NC A8 A9 A10 A11 NC 512 x 2048 Data Input Buffer 16 Column I/O Write Driver Data Output Buffer 16 128 Column Decoder 14 CE WE OE UB LB F Memory Array Decoder Sense Amp 16 DQ15 IO8 512 Row 2048 6 B 18 Control Address Input Buffer A11 A9 A3 A2 A1 A0 A10 Vcc Gnd Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS616LV1011 1 Revision 1.0 Apr. 2004 BSI BS616LV1011 PIN DESCRIPTIONS Name Function A0-A15 Address Input These 16 address inputs select one of the 65,536 x 16-bit words in the RAM. CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0 - DQ15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read Write R0201-BS616LV1011 CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT H X X X X High Z High Z ICCSB, ICCSB1 L H H X X High Z High Z ICC L L Dout Dout ICC H L High Z Dout ICC L H Dout High Z ICC ICC L L H L L X L L Din Din H L X Din ICC L H Din X ICC 2 Revision 1.0 Apr. 2004 BSI BS616LV1011 ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER RATING OPERATING RANGE UNITS RANGE AMBIENT TEMPERATURE Vcc V Commercial 0 O C to +70 O C 2.4V ~ 5.5V V TERM Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 -0.5 to Vcc+0.5 V cc Power Supply Voltage T BIAS Temperature Under Bias -40 to +85 O C T STG Storage Temperature -60 to +150 O C PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA V O Industrial O -40 C to +85 C 2.4V ~ 5.5V CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL CIN 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) PARAMETER NAME PARAMETER TEST CONDITIONS Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(3) VIL VIH Vcc=3.0V ILO Output Leakage Current Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Output Low Voltage Output High Voltage Vcc = Min, IOH = -1mA ICC(6) Operating Power Supply Current CE = VIL, IDQ = 0mA, F = Fmax(4) Standby Current-TTL CE = VIH, IDQ = 0mA ICCSB1(5) Standby Current-CMOS V -- Vcc+0.3 V -- -- 1 uA -- -- 1 uA -- -- 0.4 V 2.4 -- -- V Vcc=3.0V -- -- 18 Vcc=5.0V -- -- 38 Vcc=3.0V -- -- 1 Vcc=5.0V -- -- 2 Vcc=3.0V -- 0.4 2.5 Vcc=5.0V -- 1.3 8 Vcc=5.0V VOH ICCSB 0.8 Vcc=3.0V Vcc = Max, IOL = 2mA Vcc=3.0V Vcc=5.0V 70ns CE ≧ Vcc-0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1. Typical characteristics are at TA = 25oC. 3. Overshoot : Vcc+1.5V in case of pulse width ≦20ns. 5. IccsB1_Max. is 1.3uA/4.0uA at Vcc=3.0V/5.0V and TA=70oC. UNITS -- Vcc=5.0V Vcc = Max, VIN = 0V to Vcc MAX. 2.0 2.2 Vcc=3.0V Input Leakage Current TYP. (1) -0.5 Vcc=5.0V IIL VOL MIN. mA mA uA 2. Undershoot : -1.5V in case of pulse width ≦20ns. 4. Fmax = 1/tRC . 6. Icc_Max. is 23mA(@3V)/ 50mA(@5V) under 55ns operation. DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC ) SYMBOL VDR ICCDR (3) tCDR tR PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Vcc for Data Retention CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V Data Retention Current CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.15 0.8 uA -- -- ns -- -- ns Chip Deselect to Data Retention Time See Retention Waveform Operation Recovery Time 0 TRC (2) 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR_MAX. is 0.45uA at TA=70OC. R0201-BS616LV1011 3 Revision 1.0 Apr. 2004 BSI BS616LV1011 LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc Vcc tR t CDR CE ≥ Vcc - 0.2V VIH CE VIH KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times WAVEFORM INPUTS OUTPUTS 1V/ns MUST BE STEADY MUST BE STEADY Input and Output Timing Reference Level 0.5Vcc MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L Output Load CL = 30pF+1TTL CL = 100pF+1TTL MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns tAVQV tAA Address Access Time -- -- 55 -- -- 70 ns tELQV tACS Chip Select Access Time tBA tBA (1) Data Byte Control Access Time CYCLE TIME : 55ns DESCRIPTION (LB,UB) CYCLE TIME : 70ns UNIT (Vcc = 2.8~5.5V) (Vcc = 2.5~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. -- -- 55 -- -- 70 ns -- -- 25 -- -- 35 ns tGLQV tOE Output Enable to Output Valid -- -- 25 -- -- 35 ns t E1LQX tCLZ Chip Select to Output Low Z 10 -- -- 10 -- -- ns tBE tBE Data Byte Control to Output Low Z tGLQX tOLZ Output Enable to Output in Low Z tEHQZ tCHZ Chip Deselect to Output in High Z tBDO tBDO Data Byte Control to Output High Z tGHQZ tOHZ Output Disable to Output in High Z tAXOX tOH Data Hold from Address Change (LB,UB) (LB,UB) 10 -- -- 10 -- -- ns 5 -- -- 5 -- -- ns -- -- 20 -- -- 25 ns -- -- 20 -- -- 25 ns -- -- 20 -- -- 25 ns 10 -- -- 10 -- -- ns NOTE : 1. tBA is 25ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle. R0201-BS616LV1011 4 Revision 1.0 Apr. 2004 BSI BS616LV1011 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE t ACS t BA LB,UB t BE t D OUT READ CYCLE3 t BDO (5) t (5) CHZ CLZ (1,4) t RC ADDRESS t AA OE t OH t OE t OLZ CE (5) t CLZ t t OHZ (5) t CHZ(1,5) ACS t BA LB,UB t BE t BDO D OUT NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS616LV1011 5 Revision 1.0 Apr. 2004 BSI BS616LV1011 AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME CYCLE TIME : 55ns PARAMETER NAME tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ tWHOX t OW DESCRIPTION (Vcc = 2.8~5.5V) MIN. TYP. MAX. CYCLE TIME : 70ns (Vcc = 2.5~5.5V) MIN. TYP. MAX. UNIT Write Cycle Time 55 -- -- 70 -- -- ns Chip Select to End of Write 55 -- -- 70 -- -- ns Address Setup Time 0 -- -- 0 -- -- ns Address Valid to End of Write 55 -- -- 70 -- -- ns Write Pulse Width 35 -- -- 45 -- -- ns Write recovery Time (CE,WE) Date Byte Control to End of Write (LB,UB) 0 -- -- 0 -- -- ns 35 -- -- 45 -- -- ns -- -- 25 -- -- 30 ns Data to Write Time Overlap 35 -- -- 40 -- -- ns Data Hold from Write Time 0 -- -- 0 -- -- ns Output Disable to Output in High Z -- -- 20 -- -- 25 ns End of Write to Output Active 5 -- -- 5 -- -- ns Write to Output in High Z NOTE : 1. tBW is 35ns/45ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS (3) t WR OE (11) t CW (5) CE t BW LB,UB t AW WE (3) t WP t AS (2) (4,10) t OHZ D OUT t DH t DW D IN R0201-BS616LV1011 6 Revision 1.0 Apr. 2004 BSI BS616LV1011 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t CW (5) CE t BW LB,UB t AW WE t WR t WP (3) (2) t AS (4,10) t WHZ D OUT t OW t DH (7) (8) t DW (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE goes low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS616LV1011 7 Revision 1.0 Apr. 2004 BSI BS616LV1011 ORDERING INFORMATION BS616LV1011 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 A: BGA-48-0608 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS TSOP2-44 R0201-BS616LV1011 8 Revision 1.0 Apr. 2004 BSI BS616LV1011 PACKAGE DIMENSIONS (continued) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.4 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D E N D1 E1 8.0 6.0 48 5.25 3.75 E1 e D1 VIEW A 48 mini-BGA (6 x 8) R0201-BS616LV1011 9 Revision 1.0 Apr. 2004