C8051F96x Ultra-Low-Power, High-Efficiency, Battery-Powered Metering MCU Ultra-Low Power @ 3.6 V High-Speed Enhanced 8051 µC Core - - Pipe-lined instruction architecture executes 70% of instructions 110 µA/MHz, Low-Power Active, DC-DC enabled in 1 or 2 system clocks 110 nA sleep current with data retention; POR monitor enabled 400 nA sleep current with smaRTClock (internal LFO) Memory 700 nA sleep current with smaRTClock (external XTAL) - Up to 128 kB Flash; In-system programmable; Full read/write/ erase functionality over the entire supply range 2 µs wake-up from any sleep mode - Up to 8 kB data retention RAM 12-Bit; 16 ch. Analog to Digital Converter - Up to 75 ksps, 12-bit mode or 300 ksps 10-bit mode - External pin or internal VREF (no external capacitor required) - On-chip PGA allows measuring voltages up to twice the reference voltage Digital Peripherals - Up to 57 port I/O; All 5 V tolerant with programmable drive strength - Hardware enhanced UART, 2 SPI and I2C serial ports available concurrently - Autonomous burst mode with 16-bit automatic averaging - Four general-purpose 16-bit counter/timers - 16-bit programmable counter array (PCA) with six capture/com- accumulator - Integrated temperature sensor pare/PWM modules and watchdog timer Two Low Current Comparators - Programmable hysteresis and response time - Configurable as interrupt or reset source Clock Sources Internal 6-Bit Current Reference - Low power internal oscillator: 20 MHz - External oscillator: Crystal, RC, C, CMOS clock - SmaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal - Precision internal oscillators: 24.5 MHz with ±2% accuracy supports UART operation; spread-spectrum mode for reduced EMI - Up to ±500 µA; source and sink capability - Enhanced resolution via PWM interpolation LFO with three independent alarms Integrated LCD Controller - Supports up to 128 segments (32x4) - Integrated charge pump for contrast control On-Chip Debug - On-chip debug circuitry facilitates full speed, non-intrusive insystem debug (no emulator required) Metering-Specific Peripherals - Provides four breakpoints, single stepping - DC-DC buck converter allows dynamic voltage scaling for Package Options maximum efficiency (250 mW output) - Sleep-mode pulse accumulator with programmable switch - de-bounce and pull-up control interfaces directly to metering sensor Data Packet Processing Engine (DPPE) includes hardware AES, DMA, CRC, and encoding blocks for acceleration of wireless protocols Manchester and Three-out-of-Six encoder hardware for powerefficient implementation of the wireless M-bus specification Wake Reset C2CK/RST Debug / Programming Hardware 128k Byte ISP Flash Program Memory UART 256 Byte SRAM Timers 0, 1, 2, 3 8092 Byte XRAM PCA/WDT DMA Analog Power VDD VDC VREG Digital Power VBATDC IND DC/DC Buck Converter LCD Charge Pump XTAL1 XTAL2 GND XTAL3 XTAL4 Low Power 20 MHz Oscillator External Oscillator Circuit Enhanced smaRTClock Oscillator EMIF Pulse Counter Analog Peripherals Internal External VREF VREF A M U X 12-bit 75ksps ADC Low-Voltage/Low-Power VDD VREF Temp Sensor P3-6 Drivers 32 P7 Driver 16 P3.0...P6.7 P7.0/C2D GND CP0, CP0A System Clock Configuration Port 2 Drivers Crossbar Control LCD (up to 4x32) SFR Bus Precision 24.5 MHz Oscillator GNDDC CAP SPI 1 (DMA Enabled) AES Engine SYSCLK P2.0/SCK1 P2.1/MISO1 P2.2/MOSI1 P2.3/NSS1 P2.4 P2.5 P2.6 P2.7 SPI 0 CRC Engine Encoder Port 1 Drivers P1.0/PC0 P1.1/PC1 P1.2/XTAL3 P1.3/XTAL4 P1.4 P1.5/INT5 P1.6/INT6 P1.7 Priority Crossbar Decoder SMBus VBAT Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 Digital Peripherals C2D VBAT Development Kit: C8051F960DK Supply Voltage: 1.8 to 3.8 V Temperature Range: –40 to +85 °C Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU - 76-pin DQFN (6x6 mm), RoHS compliant - 40-pin QFN (6x6 mm), RoHS compliant - 80-pin QFP (12x12 mm), RoHS compliant CP1, CP1A + - + - Comparators Copyright © 2011 by Silicon Laboratories 11.03.11 C8051F96x Ultra-Low-Power, High-Efficiency, Battery-Powered Metering MCU Selected Electrical Specifications Parameter Symbol Active mode current IBAT Active mode current Min Typ Max Units VBAT = 3.6 V, F = 20 MHz — 110 — uA/MHz IBAT F = 20 MHz LFO; DC-DC enabled executing code from FLASH; PCLKACT = 0x00; VBAT = 3.6 V — 2.2 — mA Sleep mode current IDD Sleep Mode, SmaRTClock running, internal LFO; 3.6 V — 0.4 — uA Sleep mode current IDD Sleep Mode, SmaRTClock running, 32.768 kHz crystal; 3.6 V — 0.7 — uA Buck regulator efficiency 3.6 V input voltage — 80 — % LCD refresh current 1 Internal LFO, LCD charge pump disabled; 60 Hz; non-multiplexed operation (static mode); 3.6 V — 0.4 — uA LCD refresh current 2 Internal LFO, LCD charge pump disabled; 60 Hz; multiplexed operation; 3.6 V — 0.8 — uA 1.8 3.6 3.8 V Supply input voltage Conditions VBAT Product Family Part Number Memory (Flash/RAM) I/O LCD Package (mm) C8051F960-A-GM 128 kB / 8 kB 57 32x4 DQFN76 (6x6) C8051F960-A-GQ 128 kB / 8 kB 57 32x4 QFP80 (12x12) C8051F961-A-GM 128 kB / 8 kB 34 9x4 QFN40 (6x6) C8051F962-A-GM 128 kB / 8 kB 57 — DQFN76 (6x6) C8051F962-A-GQ 128 kB / 8 kB 57 — QFP80 (12x12) C8051F963-A-GM 128 kB / 8 kB 34 — QFN40 (6x6) C8051F964-A-GM 64 kB / 8 kB 57 32x4 DQFN76 (6x6) C8051F964-A-GQ 64 kB / 8 kB 57 32x4 QFP80 (12x12) C8051F965-A-GM 64 kB / 8 kB 34 9x4 QFN40 (6x6) C8051F966-A-GM 32 kB / 8 kB 57 32x4 DQFN76 (6x6) C8051F966-A-GQ 32 kB / 8 kB 57 32x4 QFP80 (12x12) C8051F967-A-GM 32 kB / 8 kB 34 9x4 QFN40 (6x6) C8051F968-A-GM 16 kB / 4 kB 57 32x4 DQFN76 (6x6) C8051F968-A-GQ 16 kB / 4 kB 57 32x4 QFP80 (12x12) C8051F969-A-GM 16 kB / 4 kB 34 9x4 QFN40 (6x6) Low-Voltage/Low-Power Copyright © 2011 by Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 11.03.11