CAT25010, CAT25020, CAT25040 1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM Description The CAT25010/20/40 are 1−Kb/2−Kb/4−Kb Serial CMOS EEPROM devices internally organized as 128x8/256x8/512x8 bits. They feature a 16−byte page write buffer and support the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are a clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25010/20/40 device. These devices feature software and hardware write protection, including partial as well as full array protection. http://onsemi.com SOIC−8 V SUFFIX CASE 751BD MSOP−8 Z SUFFIX CASE 846AD TDFN−8 VP2 SUFFIX CASE 511AK Features • • • • • • • • • • • • • 10 MHz SPI Compatible 1.8 V to 5.5 V Supply Voltage Range SPI Modes (0,0) & (1,1) 16−byte Page Write Buffer Self−timed Write Cycle Hardware and Software Protection Block Write Protection − Protect 1/4, 1/2 or Entire EEPROM Array Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Range 8−lead PDIP, SOIC, TSSOP and 8−pad TDFN Packages These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS Compliant VCC SI CS WP HOLD CAT25010 CAT25020 CAT25040 PDIP−8 L SUFFIX CASE 646AA PIN CONFIGURATION CS VCC HOLD WP SCK VSS SI PDIP (L), SOIC (V), MSOP (Z) TSSOP (Y), TDFN (VP2) PIN FUNCTION Pin Name Function CS Chip Select SO Serial Data Output WP Write Protect VSS Ground Serial Data Input SCK HOLD SCK 1 SO SI SO TSSOP−8 Y SUFFIX CASE 948AL VCC Serial Clock Hold Transmission Input Power Supply VSS Figure 1. Functional Symbol ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. © Semiconductor Components Industries, LLC, 2010 February, 2010 − Rev. 21 1 Publication Order Number: CAT25010/D CAT25010, CAT25020, CAT25040 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Operating Temperature −45 to +130 °C Storage Temperature −65 to +150 °C −0.5 to VCC + 0.5 V Voltage on any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter NEND (Note 3) TDR Endurance Min Units 1,000,000 Program / Erase Cycles 100 Years Data Retention Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = −40°C to +125°C unless otherwise specified.) Symbol ICC Parameter Supply Current Test Conditions Read, Write, VCC = 5.0 V, SO open ISB1 Standby Current VIN = GND or VCC, CS = VCC, WP = VCC, VCC = 5.0 V ISB2 Standby Current VIN = GND or VCC, CS = VCC, WP = GND, VCC = 5.0 V Input Leakage Current VIN = GND or VCC Output Leakage Current CS = VCC, VOUT = GND or VCC IL ILO Min Max Units 10 MHz / −40°C to 85°C 2 mA 5 MHz / −40°C to 125°C 2 mA 2 mA 4 mA TA = −40°C to +85°C TA = −40°C to +125°C 5 mA −2 2 mA TA = −40°C to +85°C −1 1 mA TA = −40°C to +125°C −1 2 mA VIL Input Low Voltage −0.5 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOL1 Output Low Voltage VCC > 2.5 V, IOL = 3.0 mA 0.4 V VOH1 Output High Voltage VCC > 2.5 V, IOH = −1.6 mA VOL2 Output Low Voltage VCC > 1.8 V, IOL = 150 mA VOH2 Output High Voltage VCC > 1.8 V, IOH = −100 mA VCC − 0.8 V V 0.2 VCC − 0.2 V V V Table 4. PIN CAPACITANCE (Note 2) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V) Symbol COUT CIN Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) Min Typ Max Units VOUT = 0 V 8 pF VIN = 0 V 8 pF 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C. http://onsemi.com 2 CAT25010, CAT25020, CAT25040 Table 5. A.C. CHARACTERISTICS (TA = −40°C to +125°C, unless otherwise specified.) (Notes 4, 8) VCC = 2.5 V − 5.5 V VCC = 1.8 V − 5.5 V Parameter Symbol TA = −405C to +855C Min Max Min Max Units 5 DC 10 MHz fSCK Clock Frequency DC tSU Data Setup Time 40 20 ns tH Data Hold Time 40 20 ns tWH SCK High Time 75 40 ns tWL SCK Low Time 75 40 ns tLZ HOLD to Output Low Z 50 25 ns tRI (Note 5) Input Rise Time 2 2 ms tFI (Note 5) Input Fall Time 2 2 ms tHD HOLD Setup Time 0 tCD HOLD Hold Time 10 tV Output Valid from Clock Low 0 ns 10 ns 75 0 40 0 ns tHO Output Hold Time ns tDIS Output Disable Time 50 20 ns tHZ HOLD to Output High Z 100 25 ns tCS CS High Time 50 20 ns tCSS CS Setup Time 20 15 ns tCSH CS Hold Time 30 20 ns tCNS CS Inactive Setup Time 20 15 ns tCNH CS Inactive Hold Time 20 15 ns tWPS WP Setup Time 10 10 ns tWPH WP Hold Time 100 60 ns tWC (Note 7) Write Cycle Time 5 5 ms Table 6. POWER−UP TIMING (Notes 5, 6) Symbol Parameter Max Units tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms 4. AC Test Conditions: Input Pulse Voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 50 pF 5. This parameter is tested initially and after a design or process change that affects the parameter. 6. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 7. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. 8. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid for die revision D and higher. The die revision D is identified by letter “D” or a dedicated marking code on top of the package. For previous product revision (Rev. C) the tCSH is defined relative to the negative clock edge (please refer to data sheet Doc. No. MD-1006 Rev. U) http://onsemi.com 3 CAT25010, CAT25020, CAT25040 Pin Description Functional Description SI: The serial data input pin accepts op−codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used to transfer data out of the device. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of the SCK clock. SCK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAT25010/20/40. CS: The chip select input pin is used to enable/disable the CAT25010/20/40. When CS is high, the SO output is tri−stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication session between host and CAT25010/20/40 must be preceded by a high to low transition and concluded with a low to high transition of the CS input. WP: The write protect input pin will allow all write operations to the device when held high. When WP pin is tied low all write operations are inhibited. HOLD: The HOLD input pin is used to pause transmission between host and CAT25010/20/40, without having to retransmit the entire sequence at a later time. To pause, HOLD must be taken low and to resume it must be taken back high, with the SCK input low during both transitions. When not used for pausing, the HOLD input should be tied to VCC, either directly or through a resistor. The CAT25010/20/40 devices support the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8−bit instruction register. The instruction set and associated op−codes are listed in Table 7. Reading data stored in the CAT25010/20/40 is accomplished by simply providing the READ command and an address. Writing to the CAT25010/20/40, in addition to a WRITE command, address and data, also requires enabling the device for writing by first setting certain bits in a Status Register, as will be explained later. After a high to low transition on the CS input pin, the CAT25010/20/40 will accept any one of the six instruction op−codes listed in Table 7 and will ignore all other possible 8−bit combinations. The communication protocol follows the timing from Figure 2. Table 7. INSTRUCTION SET (Note 9) Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 X011 Read Data from Memory WRITE 0000 X010 Write Data to Memory 9. X = 0 for CAT25010, CAT25020. X = A8 for CAT25040 tCS CS tCSS tCNH tWH tWL tCSH tCNS SCK tSU tH tRI tFI VALID IN SI tV tV tDIS tHO SO HI−Z HI−Z VALID OUT Figure 2. Synchronous Data Timing Status Register The Status Register, as shown in Table 8, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only. The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is in a Write Enable state and when set to 0, the device is in a Write Disable state. The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non−volatile. The user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 9. The protected blocks then become read−only. http://onsemi.com 4 CAT25010, CAT25020, CAT25040 Table 8. STATUS REGISTER 7 6 5 4 3 2 1 0 1 1 1 1 BP1 BP0 WEL RDY Table 9. BLOCK PROTECTION BITS Status Register Bits BP1 BP0 0 0 None No Protection 0 1 CAT25010: 060−07F, CAT25020: 0C0−0FF, CAT25040: 180−1FF Quarter Array Protection 1 0 CAT25010: 040−07F, CAT25020: 080−0FF, CAT25040: 100−1FF Half Array Protection 1 1 CAT25010: 000−07F, CAT25020: 000−0FF, CAT25040: 000−1FF Full Array Protection Array Address Protected Protection WRITE OPERATIONS instruction to the CAT25010/20/40. Care must be taken to The CAT25010/20/40 device powers up into a write take the CS input high after the WREN instruction, as disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the otherwise the Write Enable Latch will not be properly set. memory array or to the status register. In addition, the WREN timing is illustrated in Figure 3. The WREN address of the memory location(s) to be written must be instruction must be sent prior to any WRITE or WRSR outside the protected area, as defined by BP0 and BP1 bits instruction. from the status register. The internal write enable latch is reset by sending the WRDI instruction as shown in Figure 4. Disabling write Write Enable and Write Disable operations by resetting the WEL bit, will protect the device The internal Write Enable Latch and the corresponding against inadvertent writes. Status Register WEL bit are set by sending the WREN CS SCK 0 SI SO 0 0 0 0 1 1 0 HIGH IMPEDANCE Dashed Line = mode (1, 1) Figure 3. WREN Timing CS SCK SI SO 0 0 0 0 0 1 0 HIGH IMPEDANCE Dashed Line = mode (1, 1) Figure 4. WRDI Timing http://onsemi.com 5 0 CAT25010, CAT25020, CAT25040 Byte Write Page Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 8−bit address and data as shown in Figure 5. For the CAT25040, bit 3 of the write instruction opcode contains A8 address bit. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The RDY bit will indicate if the internal write cycle is in progress (RDY high), or the device is ready to accept commands (RDY low). After sending the first data byte to the CAT25010/20/40, the host may continue sending data, up to a total of 16 bytes, according to timing shown in Figure 6. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will “roll over” to the first byte in the page, thus possibly overwriting previously loaded data. Following completion of the write cycle, the CAT25010/20/40 is automatically returned to the write disable state. CS 0 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 21 22 23 SCK OPCODE SI 0 0 0 0 X* 0 DATA IN BYTE ADDRESS 1 0 A0 D7 D6 D5 D4 D3 D2 D1 D0 A7 HIGH IMPEDANCE SO Dashed Line = mode (1, 1) * X = 0 for CAT25010, CAT25020. x = A8 for CAT25040 Figure 5. Byte WRITE Timing CS 0 1 2 3 4 5 6 7 8 13 15 16−23 24−31 16+(N−1)x8−1..16+(N−1)x8 16+Nx8−1 14 SCK BYTEADDRESS OPCODE SI SO 0 0 0 0 X* 0 1 0 A7 DATA IN A0 Data Data Data Byte 1 Byte 2 Byte 3 HIGH IMPEDANCE Dashed Line = mode (1, 1) * X = 0 for CAT25010, CAT25020. x = A8 for CAT25040 Figure 6. Page WRITE Timing http://onsemi.com 6 Data Byte N 7..1 0 CAT25010, CAT25020, CAT25040 Write Status Register Write Protection The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2 and 3 can be written using the WRSR command. When WP input is low all write operations to the memory array and Status Register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register. The WP input timing is shown in Figure 8. CS 0 1 2 3 4 5 6 7 8 9 10 11 1 7 6 5 4 12 13 14 15 2 1 0 SCK OPCODE SI 0 0 0 0 0 0 0 MSB HIGH IMPEDANCE SO Dashed Line = mode (1, 1) Figure 7. WRSR Timing tWPS tWPH CS SCK WP WP Dashed Line = mode (1, 1) Figure 8. WP Timing http://onsemi.com 7 DATA IN 3 CAT25010, CAT25020, CAT25040 READ OPERATIONS Read from Memory Array address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS high. To read from memory, the host sends a READ instruction followed by a 8−bit address (for the CAT25040, bit 3 of the read instruction opcode contains A8 address bit). After receiving the last address bit, the CAT25010/20/40 will respond by shifting out data on the SO pin (as shown in Figure 9). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAT25010/20/40 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. While the internal write cycle is in progress, the RDSR command will output the RDY (Ready) bit status only (i.e., data out = FFh). CS 0 1 2 3 4 5 6 7 8 12 13 9 14 15 16 17 18 19 20 21 22 SCK OPCODE SI 0 0 0 0 X* 0 BYTE ADDRESS 1 1 A0 A7 DATA OUT HIGH IMPEDANCE SO D7 D6 D5 D4 D3 D2 D1 D0 Dashed Line = mode (1, 1) * X = 0 for CAT25010, CAT25020. X = A8 for CAT25040 MSB Figure 9. READ Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 6 5 11 12 13 14 2 1 SCK OPCODE SI SO 0 0 0 0 0 DATA OUT HIGH IMPEDANCE 7 MSB Dashed Line = mode (1, 1) Figure 10. RDSR Timing http://onsemi.com 8 4 3 0 CAT25010, CAT25020, CAT25040 Hold Operation VCC drops below the POR trigger level. This bi−directional POR behavior protects the device against ‘brown−out’ failure following a temporary loss of power. The CAT25010/20/40 device powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued prior to any writes to the device. After power up, the CS pin must be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the device goes into a write disable mode. The CS input must be set high after the proper number of clock cycles to start the internal write cycle. Access to the memory array during an internal write cycle is ignored and programming is continued. Any invalid op−code will be ignored and the serial output pin (SO) will remain in the high impedance state. The HOLD input can be used to pause communication between host and CAT25010/20/40. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During the pause, the data output pin (SO) is tri−stated (high impedance) and SI transitions are ignored. To resume communication, HOLD must be taken high while SCK is low. Design Considerations The CAT25010/20/40 devices incorporate Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when CS tCD tCD SCK tHD tHD HOLD tHZ HIGH IMPEDANCE SO tLZ Dashed Line = mode (1, 1) Figure 11. HOLD Timing http://onsemi.com 9 CAT25010, CAT25020, CAT25040 PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e PIN # 1 IDENTIFICATION MAX 2.54 BSC eB 7.87 L 2.92 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. http://onsemi.com 10 CAT25010, CAT25020, CAT25040 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 MAX 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 11 CAT25010, CAT25020, CAT25040 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 0.15 0.90 1.05 0.30 c 0.09 D 2.90 3.00 0.20 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 12 CAT25010, CAT25020, CAT25040 PACKAGE DIMENSIONS TDFN8, 2x3 CASE 511AK−01 ISSUE A D A e b E2 E PIN#1 IDENTIFICATION A1 PIN#1 INDEX AREA D2 TOP VIEW SYMBOL MIN SIDE VIEW NOM A 0.70 0.75 0.80 0.00 0.02 0.05 A2 0.45 0.55 0.65 A2 0.20 REF A3 b 0.20 0.25 0.30 D 1.90 2.00 2.10 D2 1.30 1.40 1.50 E 2.90 3.00 3.10 E2 1.20 1.30 1.40 e L BOTTOM VIEW MAX A1 A3 FRONT VIEW 0.50 TYP 0.20 0.30 L 0.40 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. http://onsemi.com 13 CAT25010, CAT25020, CAT25040 PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD−01 ISSUE O SYMBOL MIN NOM MAX 1.10 A E A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.22 0.38 c 0.13 0.23 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 E1 e L 0.65 BSC 0.40 0.60 0.80 L1 0.95 REF L2 0.25 BSC θ 0º 6º TOP VIEW D A A2 A1 DETAIL A e b c SIDE VIEW END VIEW q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A http://onsemi.com 14 CAT25010, CAT25020, CAT25040 Example of Ordering Information (Note 12) Prefix Device # Suffix CAT 25040 V I −G Temperature Range Company ID Product Number 25010: 1−Kb 25020: 2−Kb 25040: 4−Kb I = Industrial (−40°C to +85°C) E = Extended (−40°C to +125°C) T3 Lead Finish G: NiPdAu Blank: Matte−Tin Tape & Reel (Note 15) T: Tape & Reel 3: 3,000 Units / Reel Package L: PDIP V: SOIC, JEDEC Y: TSSOP VP2: TDFN (2 x 3 mm) Z: MSOP (Note 13) 10. All packages are RoHS−compliant (Lead−free, Halogen−free). 11. The standard lead finish is NiPdAu. 12. The device used in the above example is a CAT25040VI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 13. For MSOP package availability, please contact your nearest ON Semiconductor Sales office. 14. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 15. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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