CD4034BMS December 1992 CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register Features Description • High Voltage Types (20V Rating) CD4034BMS is a static eight-stage parallel-or serial-input parallel-output register. It can be used to: • Bidirectional Parallel Data Input • Parallel or Serial Inputs/Parallel Outputs • Asynchronous or Synchronous Parallel Data Loading • Parallel Data-Input Enable on “A” Data Lines (3-State Output) • Data Recirculation for Register Expansion • Multipackage Register Expansion • Fully Static Operation DC-to-10MHz (typ.) at VDD = 10V 1) bidirectionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Inputs that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S). Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided. • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; - 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering. Pinout CD4034BMS TOP VIEW • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” 8 1 24 VDD 7 2 23 8 6 3 22 7 5 4 21 6 4 5 20 5 3 6 19 4 2 7 18 3 1 8 17 2 “A” ENABLE 9 16 1 “B” DATA LINES Applications • Parallel Input/Parallel Output, Serial Input/Parallel Output, Serial Input/Serial Output Register • Shift Right/Shift Left Register • Shift Right/Shift Left With Parallel Loading • Address Register • Buffer Register • Bus System Register with Enable Parallel Lines at Bus Side SERIAL INPUT 10 “A” DATA LINES • Standardized Symmetrical Output Characteristics 15 CLOCK A/B 11 14 A/S VSS 12 13 P/S • Double Bus Register System • Up-Down Johnson or Ring Counter • Pseudo-Random Code Generators • Sample and Hold Register (Storage, Counting, Display) • Frequency and Phase Comparator CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-837 File Number 3307 CD4034BMS Functional Diagram A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with the positive transition of the clock provided the A/S input is low. If the A/S input is high the transfer is independent of the clock. The direction of data flow is controlled by the A/B input. When this signal is high the A data lines are inputs (and B data lines are outputs); a low A/B signal reverses the direction of data flow. SI AE A/B STEERING LOGIC A/S P/S CL The AE input is an additional feature which allows many registers to feed data to a common bus. The A DATA lines are enabled only when this signal is high. A1 The serial data appears as output data on either the B lines (when A/B is high) or the A lines (when A/B is low and the AE signal is high). Register expansion can be accomplished by simply cascading CD4034BMS packages. The CD4034BMS is supplied in these 24 lead outline packages: Braze Seal DIP H4V Ceramic Flatpack H4P 7-838 6 STAGES A DATA LINES A low P/S signal allows serial data to transfer into the register synchronously with the positive transition of the clock. The A/S input is internally disabled when the register is in the serial mode (asynchronous serial operation is not allowed). B1 SI Data storage through recirculation of data in each register stage is accomplished by making the A/B signal high and the AE signal low. Serial Operation SI Q B DATA LINES Parallel Operation Q A8 SI B8 Specifications CD4034BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Except A and B Lines Input Leakage Current Except A and B Lines SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125 C - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Functional F VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V 1 +25oC -0.4 - µA Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V 2 +125oC -12 - µA VDD = 18V 3 -55oC -0.4 - µA VDD = 20V 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-839 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4034BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay Parallel In to Parallel Out TPHL TPLH GROUP A SUBGROUPS TEMPERATURE CONDITIONS VDD = 5V, VIN = VDD or GND (Notes 1, 2) Propagation Delay 3 State AE to Out ‘A’ TPLZ TPHZ VDD = 5V, VIN = VDD or GND (Notes 2, 3) Propagation Delay 3-State AE to Out ‘A’ TPZL TPZH VDD = 5V, VIN = VDD or GND (Notes 2, 3) Transition Time Maximum Clock Input Frequency TTHL TTLH VDD = 5V, VIN = VDD or GND (Notes 1, 2) FCL VDD = 5V, VIN = VDD or GND (Note 2) 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 700 ns - 945 ns - 400 ns - 540 ns 9 +25oC - 400 ns 10, 11 +125oC, -55oC - 540 ns - 200 ns - 270 ns 9 10, 11 o +25 C o o +125 C, -55 C o 9 +25 C 2 - MHz 10, 11 +125oC, -55oC 1.48 - MHz MIN MAX UNITS µA NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 7-840 +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA Specifications CD4034BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH15 CONDITIONS VDD =15V, VOUT = 13.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -2.4 mA o -55 C - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V VDD = 10V 1, 2, 3 +25oC - 240 ns VDD = 15V 1, 2, 3 +25oC - 170 ns o 700 - ns o Propagation Delay Parallel In to Parallel Out Propagation Delay Serial to Parallel Out Propagation Delay 3-State AE to Out ‘A’ TPHL TPLH TPHL TPLH TPLZ TPHZ VDD = 5V 1, 2, 3 +25 C VDD = 10V 1, 2, 3 +25 C - 240 ns VDD = 15V 1, 2, 3 +25oC - 170 ns VDD = 10V 1, 2, 3, 4 +25oC - 160 ns VDD = 15V 1, 2, 3, 4 +25oC - 120 ns 1, 2, 3, 4 +25oC - 160 ns Propagation Delay 3-State AE to Out ‘A’ TPZL TPZH VDD = 10V VDD = 15V 1, 2, 3, 4 +25 C - 120 ns Transition Time TTLH TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns VDD = 10V 1, 2, 3 +25 oC 5 - MHz VDD = 15V 1, 2, 3 +25oC 7 - MHz 1, 2, 3 o +25 C - 160 ns VDD = 10V 1, 2, 3 +25 oC - 60 ns VDD = 15V 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25 oC - 50 ns VDD = 10V 1, 2, 3 +25oC - 30 ns VDD = 15V 1, 2, 3 +25oC - 20 ns 1, 2, 3 +25 oC - 250 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 70 ns 1, 2, 3 +25oC - 15 µs VDD = 10V 1, 2, 3 +25oC - 15 µs VDD = 15V 1, 2, 3 +25oC - 15 µs VDD = 5V 1, 2, 3 +25oC - 350 ns VDD = 10V 1, 2, 3 +25oC - 140 ns 1, 2, 3 +25oC - 80 ns 1, 2 +25oC - 7.5 pF Maximum Clock Input Frequency Minimum Data Setup Time Serial Data to Clock Minimum Data Setup Time Parallel Data to Clock Minimum Clock Pulse Width Maximum Clock Rise and Fall Time (Note 5) Minimum High Level Pulse Width AE, P/S, A/S FCL TS TS TW TRCL TFCL TW VDD = 15V VDD = 5V VDD = 5V VDD = 5V VDD = 5V VDD = 15V Input Capacitance CIN Any Input o NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, tRCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. 7-841 Specifications CD4034BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Supply Current N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2, 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 7-842 Specifications CD4034BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 1-8 12, 15 - 23 9 - 11, 13, 14, 24 Static Burn-In 2 Note 1 1-8 12 9 - 11, 13 - 24 Dynamic Burn-In Note 1 - 1 - 8, 11 - 14 9, 24 1-8 12 9 - 11, 13 - 24 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 16 - 23 15 10 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram * N AB N M M M L * L K AE K VDD P/S * P/S P/S CLS * A/S CLS VSS CLM *INPUTS PROTECTED BY CMOS PROTECTION NETWORK * CLM CLOCK FLIP-FLOP TRUTH TABLE INPUTS CLM 1 = High Level OUTPUT CLS 0 = Low Level 7-843 D Q 0 0 0 0 0 Invalid Condition X 0 1 1 1 1 1 Invalid Condition X = Don’t Care CD4034BMS trCL tfCL VDD 90% 50% 10% 0 CLOCK INPUT “A” OR “B” DATA INPUTS 50% INPUT tTLH “B” OR “A” DATA OUTPUTS tPLH tTHL VDD 90% 50% 10% 0 0 ** tSLH tTLH ** tSHL tTHL OUTPUT tPHL tPLH VDD 90% 50% 10% 0 tPHL *Input refers to any of the “A” or “B” data inputs, “A” ENABLE, SERIAL INPUT, A/B, P/S, or A/S inputs **tSLH and tSHL are Set-Up times FIGURE 2. SYNCHRONOUS OPERATION PROPAGATION DELAY TIMES, TRANSITION TIMES, AND SET-UP TIMES FIGURE 1. ASYNCHRONOUS OPERATION PROPAGATION DELAY TIME AND TRANSITION TIME CLOCK A ENABLE P/S A/B A/S SERIAL DATA A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 B DATA LINES ARE OUTPUTS FIGURE 3. TIMING DIAGRAM 7-844 A DATA LINES ARE OUTPUTS CD4034BMS 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 15 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 -5 -10V POWER DISSIPATION PER GATE (PD) (µW) TRANSITION TIME (tTHL, tTLH) (ns) ) = +25oC SUPPLY VOLTAGE (VDD) = 5V 100 10V 0 0 -15 FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 200 15V 50 -10 -15V 106 150 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 8 6 4 2 SUPPLY VOLTAGE (VDD) = 15V 105 8 6 4 104 10V 2 8 6 4 10V 5V 2 103 8 6 4 CL = 50pF 2 CL = 15pF 102 20 2 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 1 FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 4 68 2 4 6 8 2 4 6 8 2 4 6 8 103 10 102 INPUT FREQUENCY (fI) (kHz) 104 2 4 6 8 105 FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY 7-845 CD4034BMS [A(B) PAR DATA IN B(A) PAR DATA OUT] PROPAGATION DELAY TIME (tPHL, tPLH) (ns) Typical Performance Characteristics (Continued) AMBIENT TEMPERATURE (TA) = +25oC 700 600 500 SUPPLY VOLTAGE (VDD) = 5V 400 300 200 10V 100 15V 0 20 50 60 70 80 90 30 40 LOAD CAPACITANCE (CL) (pF) 100 FIGURE 10. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE [A(B) PARALLEL DATA INPUT TO B(A) PARALLEL DATA OUTPUT, SYNCHRONOUS OR ASYNCHRONOUS]) 7-846 CD4034BMS 1 OF 8 STAGES K An p n M VSS Q’ K PROTECTION NETWORK ON ALL “A” AND “B” DATA INPUTS P/S CLM CLS p p p n n n P/S CLM D SERIAL DATA VDD CLM CLS Q’ M CLS p p n n CLM CLS VDD N VSS VDD Q’ L N VSS p VSS n Q (TO NEXT STAGE D) PROTECTION NETWORK ON SERIAL DATA INPUT Bn L FIGURE 11. REGISTER STAGE LOGIC DIAGRAM (1 OF 8 STAGES) TRUTH TABLE REGISTER INPUT-LEVELS AND RESULTING REGISTER OPERATION “A” ENABLE P/S A/B A/S 0 0 0 X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs Disabled 0 0 1 X Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output 0 1 0 0 Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled 0 1 0 1 Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled 0 1 1 0 Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Synch. Data Recirculation 0 1 1 1 Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Asynch. Data Recirculation 1 0 0 X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output 1 0 1 X Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output 1 1 0 0 Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data Output 1 1 0 1 Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data Output 1 1 1 0 Parallel Mode; “A” Synch, Parallel Data Input, “B” Parallel Data Output 1 1 1 1 Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data Output OPERATION* *Outputs change at positive transition of clock in the serial mode and when the A/S control input is “low” in the parallel mode. During transfer from parallel to serial operation A/S should remain low in order to prevent DS transfer into Flip Flops. 1 = High Level 0 = Low Level X = Don’t Care 7-847 CD4034BMS Applications VDD SERIAL DATA VDD VDD AE A PARALLEL SI DATA A/B CD4034 A/S CL B PARALLEL DATA P/S VDD AE A PARALLEL SI DATA A/B CD4034 A/S CL B PARALLEL DATA P/S SERIAL DATA SERIAL DATA P/S A/S CL FIGURE 12. 16-BIT PARALLEL IN/PARALLEL OUT, PARALLEL IN/SERIAL OUT, SERIAL IN/PARALLEL OUT SERIAL IN/SERIAL OUT REGISTER “A” ENABLE AE A PARALLEL SI DATA A/B CD4034 A/S CL B PARALLEL DATA P/S SERIAL DATA AE A PARALLEL SI DATA A/B CD4034 A/S CL B PARALLEL DATA P/S SERIAL DATA SERIAL DATA A/B CL FIGURE 13. 16-BIT SERIAL IN/GATED PARALLEL OUT REGISTER BUS LINES (SINGLE) DOUBLE - BUS SYSTEM (ENABLE INPUTS ON BOTH SIDES) MEMORY UNIT P/S AE 1 1 CD4034 2 2 3 W REG 3 4 4 B A 5 5 6 6 7 7 8 8 SI A/B A/S CL AE P/S 1 1 2 2 X(1) 3 3 REG 4 4 A B 5 5 CD4034 6 6 7 7 8 8 SI A/B A/S CL PERIPHERAL UNIT SI A/B A/S CL P/S AE 1 1 2 2 3 Y REG 3 4 4 B A 5 5 CD4034 6 6 7 7 8 8 P/S AE 1 1 2 2 3 Z REG 3 4 4 B A 5 5 6 CD4034 6 7 7 8 8 SI A/B A/S CL THE “A” ENABLE (AE) AND A/B SIGNALS CONTROL ALL COMBINATIONS OF TRANSFER BETWEEN THE REGISTERS AND BUS SYSTEMS FIGURE 14. SINGLE AND DOUBLE-BUS SYSTEMS 7-848 P/S AE 1 1 2 2 X(2) 3 3 REG 4 4 B A 5 5 CD4034 6 6 7 7 8 8 SI A/B A/S CL ARITHMETIC UNIT TO 2ND BUS SYSTEM CD4034BMS Applications (Continued) SHIFT LEFT OUTPUT “A” ENABLE AE SHIFT LEFT/ SHIFT RIGHT P/S “A” PARALLEL DATA “A” PARALLEL DATA SHIFT RIGHT OUTPUT SHIFT RIGHT INPUT AE 1 SI P/S REG. 1 CD4034 CLOCK 8 AE 1 SI P/S A/S CL A/B 1 A/S PARALLEL ENTRY 8 REG. 2 CD4034 A/S CL A/B 1 SHIFT LEFT INPUT* A/S CL AE AE 1 SI P/S VDD A/S CL A/B 1 A PARALLEL DATA 8 AE 1 SI P/S REG. 3 CD4034 8 8 REG. 4 CD4034 A/S CL A/B 1 VDD B PARALLEL DATA A PARALLEL DATA B PARALLEL DATA 8 FIGURE 15. SHIFT RIGHT/SHIFT LEFT WITH PARALLEL INPUTS A “High” (“Low”) on the shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register on the positive transition of the clock signal. A “high” on the “A” Enable Input disables the “A” parallel data lines Reg. 1 and 2 and enables the “A” data lines on registers 3 and 4 and allows parallel data into registers 1 and 2. Other logic schemes may be used in place of registers 3 and 4 for parallel loading. When parallel inputs are not used Reg. 3 and 4 and associated logic are not required. * Shift left input must be disabled during parallel entry. SAMPLE/HOLD AE SERIAL DATA VDD SI A/B A/S CLOCK CL AE A PARALLEL DATA SERIAL DATA CD4034 B PARALLEL DATA P/S VDD A/B A/S A/S CLOCK 8 “A” PARALLEL DATA CD4034 CL P/S CD4016 1 SI “B” PARALLEL DATA 1 8 P/S TO DISPLAY ETC N=1-8 SERIAL OUTPUT CD4016 N STAGE SELECTION FIGURE 16. N-STAGE SHIFT REGISTER WITH FIXED SERIAL OUTPUT LINE FIGURE 17. SAMPLE AND HOLD REGISTER - SERIAL/PARALLEL IN - PARALLEL OUT 7-849 CD4034BMS Chip Dimensions and Pad Layout Dimension in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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