CD4034BM/CD4034BC 8-Stage TRI-STATEÉ Bidirectional Parallel/Serial Input/Output Bus Register General Description The CD4034BM/CD4034BC is an 8-bit CMOS static shift register with two parallel bidirectional data ports (A and B) which, when combined with serial shifting operations, can be used to (1) bidirectionally transfer parallel data between two buses, (2) convert serial data to parallel form and direct them to either of two buses, (3) store (recirculate) parallel data, or (4) accept parallel data from either of two buses and convert them to serial form. These operations are controlled by five control inputs: A ENABLE (AE): ‘‘A’’ data port is enabled only when AE is at logical ‘‘1’’. This allows the use of a common bus for multiple packages. A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B): This input controls the direction of data flow. When at logical ‘’1’’, data flows from port A to B (A is input, B is output). When at logical ‘‘0’’, the data flow direction is reversed. ASYNCHRONOUS/SYNCHRONOUS (A/S): When A/S is at logical ‘‘0’’, data transfer occurs at positive transition of the CLOCK. When A/S is at logical ‘‘1’’, data transfer is independent of the CLOCK for parallel operation. In serial mode, A/S input is internally disabled such that operation is always synchronous. (Asynchronous serial operation is not possible.) PARALLEL/SERIAL (P/S): A logical ‘‘1’’ P/S input allows data transfer into the registers via A or B port (synchronous if A/S e logical ‘‘0’’, asynchronous if A/S e logical ‘‘1’’). A logical ‘‘0’’ P/S allows serial data to transfer into the register synchronously with the positive transition of the CLOCK, independent of the A/S input. CLOCK: Single phase, enabled only in synchronous mode. (Either P/S e logical ‘‘1’’ and A/S e logical ‘‘0’’ or P/S e logical ‘‘0’’. All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS. Features Y Y Y Y Wide supply voltage range 3.0V to 18V High noise immunity 0.45 VDD (typ.) Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS RCA CD4034B second source Applications Y Y Y Y Y Y Y Y Y Y Y Parallel Input/Parallel Output Parallel Input/Serial Output Serial Input/Parallel Output Serial Input/Serial Output register Shift right/shift left register Shift right/shift left with parallel loading Address register Buffer register Bus system register with enable parallel lines at bus side Double bus register system Up-down Johnson or ring counter Pseudo-random code generators Sample and hold register (storage, counting, display) Frequency and phase comparator Connection Diagram Dual-In-Line Package Order Number CD4034B Top View TL/F/5963 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/5963 RRD-B30M105/Printed in U. S. A. CD4034BM/CD4034BC 8-Stage TRI-STATE Bidirectional Parallel/Serial Input/Output Bus Register February 1988 Absolute Maximum Ratings (Notes 1 & 2) Recommended Operating Conditions (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temp. Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4034BM CD4034BC b 0.5 VDC to a 18 VDC b 0.5 VDC to VDD a 0.5 VDC b 65§ C to a 150§ C a 3 VDC to a 15 VDC 0 VDC to VDD VDC b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 260§ C DC Electrical Characteristics CD4034BM (Note 2) Symbol Parameter b 55§ C Conditions Min Max a 25§ C Min Typ a 125§ C Max Min Units Max IDD Quiescent Device Current VDD e 5V, VIN e VDD or VSS VDD e 10V, VIN e VDD or VSS VDD e 15V, VIN e VDD or VSS VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VOH High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VIL Low Level Input Voltage VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V VIH High Level Input Voltage VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V 3.5 7.0 11.0 3.5 7.0 11.0 3.5 7.0 11.0 V V V IOL Low Level Output Current (Note 3) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 mA mA mA IOH High Level Output Current VDD e 5V, VO e 4.6V (Note 3) VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.64 b 1.6 b 4.2 b 0.51 b 1.3 b 3.4 b 0.36 b 0.9 b 2.4 mA mA mA IIN Input Curent IOZ TRI-STATE Leakage Current 5 10 20 5 10 20 150 300 600 mA mA mA 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 1.5 3.0 4.0 VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V b 0.1 VDD e 15V, VO e 0V VDD e 15V, VO e 15V b 0.1 1.5 3.0 4.0 b 0.1 b 0.1 0.1 b 10-5 10-5 0.1 1.5 3.0 4.0 b 1.0 0.1 b 10-5 10-5 V V V 1.0 mA mA 1.0 mA mA b 1.0 0.1 V V V Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. 2 DC Electrical Characteristics CD4034BC (Note 2) Symbol Parameter b 40§ C Conditions Min Max a 25§ C Min a 85§ C Typ Max Min Units Max IDD Quiescent Device Current VDD e 5V, VIN e VDD or VSS VDD e 10V, VIN e VDD or VSS VDD e 15V, VIN e VDD or VSS VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VOH High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VIL Low Level Input Voltage VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V VIH High Level Input Voltage VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V 3.5 7.0 11.0 3.5 7.0 11.0 3.5 7.0 11.0 V V V IOL Low Level Output Current (Note 3) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.52 1.3 3.6 0.44 1.1 3.0 0.36 0.9 2.4 mA mA mA IOH High Level Output Current VDD e 5V, VO e 4.6V (Note 3) VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.52 b 1.3 b 3.6 b 0.44 b 1.1 b 3.0 b 0.36 b 0.9 b 2.4 mA mA mA IIN Input Current IOZ TRI-STATE Leakage Current 20 40 80 20 40 80 150 300 600 mA mA mA 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 1.5 3.0 4.0 VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V b 0.3 VDD e 15V, VO e 0V VDD e 15V, VO e 15V b 0.3 1.5 3.0 4.0 b 0.3 b 10-5 10-5 0.3 b 0.3 1.5 3.0 4.0 b 1.0 0.3 b 10-5 10-5 0.3 V V V 1.0 mA mA 1.0 mA mA b 1.0 0.3 V V V AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200k, input tr e tf e 20 ns, unless otherwise specified Symbol Parameter Typ Max Units tPHL, tPLH Propagation Delay Time, A (B) Synchronous Parallel Data or Serial Data Input, B (A) Parallel Data Output VDD e 5V VDD e 10V VDD e 15V Conditions 280 120 85 700 270 190 ns ns ns tPHL, tPLH Propagation Delay Time, A (B) A (B) Asynchronous Parallel Data Input, B (A) Parallel Data Output VDD e 5V VDD e 10V VDD e 15V 280 120 85 700 270 190 ns ns ns tPHZ, tPLZ Propagation Delay Time from A/B or AE to High Impedance State at A Outputs or from A/B to High Impedance State at B Outputs VDD e 5V, RL e 1.0 kX VDD e 10V, RL e 1.0 kX VDD e 15V, RL e 1.0 kX 95 60 45 220 130 100 ns ns ns tPZH, tPZL Propagation Delay Time from A/B or AE to Logical ‘‘1’’ or Logical ‘‘0’’ State at A Outputs or from A/B to Logical ‘‘1’’ or Logical ‘‘0’’ State at B Outputs VDD e 5V, RL e 1.0 kX VDD e 10V, RL e 1.0 kX VDD e 15V, RL e 1.0 kX 180 75 55 480 190 140 ns ns ns 3 Min AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200k, input tr e tf e 20 ns, unless otherwise specified (Continued) Symbol Parameter Conditions Min Typ Max Units 100 50 40 200 100 80 ns ns ns tTHL, tTLH Output Transition Time VDD e 5V VDD e 10V VDD e 15V fCL Maximum Clock Input Frequency VDD e 5V VDD e 10V VDD e 15V tWL, tWH Minimum Clock Pulse Width VDD e 5V VDD e 10V VDD e 15V tRCL, tFCL Maximum Clock Rise & Fall Time VDD e 5V VDD e 10V VDD e 15V tSU Parallel (A or B) and Serial Data Setup Time VDD e 5V VDD e 10V VDD e 15V 25 10 7 70 30 20 ns ns ns tSU Control Inputs AE, A/B, P/S, A/S Setup Time VDD e 5V VDD e 10V VDD e 15V 110 35 60 280 100 60 ns ns ns tWH Minimum High Level AE, A/B, P/S, A/S Pulse Width VDD e 5V VDD e 10V VDD e 15V 160 70 40 400 160 90 ns ns ns CIN Average Input Capacitance A and B Data I/O and A/B Control Input Any Other Input 7 15 pF 5 7.5 pF CPD Power Dissipation Capacitance (Note 4) 2 5 7 4 10 14 125 50 35 MHz MHz MHz 250 100 70 15 15 15 ns ns ns ms ms ms 155 pF *AC Parameters are guaranteed by DC correlated testing. Note 4: CPD determines the no-load power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note, AN-90. Logic Diagram TL/F/5963 – 2 4 Schematic Diagram TL/F/5963 – 3 5 Switching Time Waveforms and Test Circuits Synchronous Operation TL/F/5963 – 5 tr, CL e tf, CL e 20 ns Asynchronous Operation TL/F/5963 – 6 TL/F/5963–4 TL/F/5963–7 TL/F/5963 – 8 TL/F/5963 – 10 TL/F/5963–9 6 Applications 16-Bit Parallel In/Parallel Out, Parallel In/Serial Out, Serial In/Parallel Out, Serial In/Serial Out Register TL/F/5963 – 11 7 Applications (Continued) 16-Bit Serial In/Gated Parallel Out Register TL/F/5963 – 12 Frequency and Phase Comparator TL/F/5963 – 13 TL/F/5963 – 14 *When f1 e f2, tW is proportional to the phase of f1 with respect to f2. 8 Applications (Continued) Shift Right/Shift Left with Parallel Inputs TL/F/5963 – 15 Shift left input must be disabled during parallel entry. lines on Registers 3 and 4 and allows parallel data into Registers 1 and 2. Other logic schemes may be used in place of registers 3 and 4 for parallel loading. When parallel inputs are not used Registers 3 and 4 and associated logic are not required. A ‘‘High’’ (‘‘Low’’) on the Shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register on the positive transition of the clock signal. A ‘‘high’’ on the ‘‘A’’ Enable Input disables the ‘‘A’’ parallel data lines on Registers 1 and 2 and enables the ‘‘A’’ data 9 Truth Table ‘‘A’’ Enable P/S A/B A/S 0 0 0 X Serial Mode Synchronous Serial data input, A- and B-Parallel data outputs disabled. Operation* 0 0 1 X Serial Synchronous Serial data input, B-Parallel data output. 0 1 0 0 Parallel B Synchronous Parallel data inputs, A-Parallel data outputs disabled. 0 1 0 1 Parallel B Asynchronous Parallel data inputs, A-Parallel data outputs disabled. 0 1 1 0 Parallel A-Parallel data inputs disabled, B-Parallel data outputs, synchronous data recirculation. 0 1 1 1 Parallel A-Parallel data inputs disabled, B-Parallel data outputs, asynchronous data recirculation. 1 0 0 X Serial Synchronous Serial data input, A-Parallel data output. 1 0 1 X Serial Synchronous Serial data input, B-Parallel data output. 1 1 0 0 Parallel B Synchronous Parallel data input, A-Parallel data output. 1 1 0 1 Parallel B Asynchronous Parallel data input, A-Parallel data output. 1 1 1 0 Parallel A Synchronous Parallel data input, B-Parallel data output. 1 1 1 1 Parallel A Asynchronous Parallel data input, B-Parallel data output. X e Don’t Care *For synchronous operation (serial mode or when A/S e 0 in parallel mode), outputs change state at positive transition of the clock. 10 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4034BMJ or CD4034BCJ NS Package Number J24A 11 CD4034BM/CD4034BC 8-Stage TRI-STATE Bidirectional Parallel/Serial Input/Output Bus Register Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number CD4034BMN or CD4034BCN NS Package Number N24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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