CD4517BMS CMOS Dual 64-Stage Static Shift Register December 1992 Features Description • High-Voltage Types (20-Volt Rating) CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low-to-high transition. The truth table indicates how the clock and write enable inputs control the opeation of the CD4517BMS. Inputs at the intermediate taps allow entry of 64 bits into the register with 16 clock pulses. The 3-state outputs permit connection of this device to an external bus. • Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V • Clock Frequency 12MHz (Typ.) at VDD = 10V • Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock Rise and Fall Times • Capable of Driving Two Low-power TTL Loads, One Low-power Schottky TTL Load, or Two HTL Loads • 3-State Outputs • 100% Tested for Quiescent Current at 20V • Standardized, Symmetrical Output Characteristics • 5V, 10V, and 15V Parametric Ratings • Meets all Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ‘B’ Series CMOS Devices" The CD4517BMS is supplied in these 16 lead outline packages: Applications Braze Seal DIP Frit Seal DIP Ceramic Flatpack • Time-delay Circuits H4X H1F H6P • Scratch-pad Memories • General-purpose Serial Shift-register Applications Pinout Functional Diagram CD4517BMS TOP VIEW CL CL Q16A 1 16 VDD Q48A 2 15 Q16B WEA 3 14 Q48B CLA 4 13 WEB Q64A 5 12 CLB Q32A 6 11 Q64B DA 7 10 Q32B VSS 8 D WE CL CL CL Q16 Q32 Q48 Q64 D1 16 STAGES D17 16 STAGES D33 16 STAGES D49 16 STAGES WE = 0 WE = 1 STAGE 16 OUT/IN TAP STAGE32 OUT/IN TAP STAGE 48 OUT/IN TAP STAGE 64 OUT/IN TAP 9 DB CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1197 File Number 3341 Specifications CD4517BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125 C - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Functional F VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V 1 +25oC -0.4 - µA Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V 2 +125oC -12 - µA VDD = 18V 3 -55oC -0.4 - µA VDD = 20V 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1198 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4517BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to 16 Transition Time Maximum Clock Input Frequency SYMBOL TPHL TPLH CONDITIONS (Note 1, 2) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 400 ns - 540 ns - 200 ns - 270 ns 9 +25oC 3 - MHz 10, 11 +125oC, -55oC 2.22 - MHz NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 -55 C, +25 C - 10 µA +125oC - 300 µA - 10 µA o -55oC, o +25oC - 600 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA oC +125 Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V 1, 2 1, 2 +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V 7-1199 Specifications CD4517BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay Clock to Q16 Propagation Delay 3-State WE to Q16 Transition Time Maximum Clock Input Frequency Minimum Data to Clock Setup Time SYMBOL TPHL TPLH CONDITIONS VDD = 10V - 220 ns o +25 C - 180 ns - 150 ns 1, 2, 4 +25 oC - 80 ns TTHL TTLH FCL TS VDD = 15V 1, 2, 4 +25oC - 60 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns VDD = 10V 1, 2 +25o C 6 - MHz VDD = 15V 1, 2 +25oC 8 - MHz oC - 20 ns - 10 ns 1, 2, 3 o +25 C - 10 ns VDD = 5V 1, 2, 3 +25o C - 200 ns VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 50 ns VDD = 5V 1, 2, 3 +25 oC - 180 ns VDD = 10V 1, 2, 3 +25oC - 80 ns 1, 2, 3 o +25 C - 50 ns VDD = 5V 1, 2, 3 +25 oC - 100 ns VDD = 10V 1, 2, 3 +25oC - 50 ns 1, 2, 3 +25 oC - 40 ns VDD = 5V 1, 2, 3 +25oC 0 - ns VDD = 10V 1, 2, 3 +25oC 0 - ns 1, 2, 3 oC 0 - ns VDD = 5V 1, 2, 3 +25 VDD = 10V 1, 2, 3 +25oC TH TW TR TS TRCL TFCL CIN +25 VDD = 5V 1, 2, 3, 5 +25oC - 15 µs VDD = 10V 1, 2, 3, 5 +25oC - 5 µs 1, 2, 3, 5 +25oC - 5 µs - 7.5 pF VDD = 15V Input Capacitance 1, 2, 3 +25oC VDD = 15V Maximum Clock Input Rise and Fall Time UNITS 1, 2, 3 VDD = 15V Write Enable-to-Clock Setup Time MAX +25oC 1, 2, 5 VDD = 15V Minimum Write Enable to-Clock Release Time MIN VDD = 15V VDD = 15V Minimum Clock Pulse Width TEMPERATURE TPHZ, ZH VDD = 5V TPLZ, ZL VDD = 10V VDD = 15V Minimum Data to Clock Hold Time NOTES Any Input 1, 2 o +25 C NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Measured at the point of 10% change in output with an output load 50pF, RL = 1KΩ to VDD for TPZL and TPLZ and RL = 1KΩ to VSS for TPZH and TPHZ 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VSS = 0V, IDD = 10µA 1, 4 +25oC 7-1200 MIN MAX UNITS - 25 µA -2.8 -0.2 V - ±1 V 0.2 2.8 V Specifications CD4517BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL ∆VTP P Threshold Voltage Delta Functional F CONDITIONS VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL DELTA LIMIT IDD ± 1.0µA IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B IDD, IOL5, IOH5A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 1, 2, 5, 6, 10, 11, 14, 15 3, 4, 7-9, 12, 13 16 Static Burn-In 2 (Note 1) 1, 2, 5, 6, 10, 11, 14, 15 8 3, 4, 7, 9, 12, 13, 16 Dynamic BurnIn (Note 1) - 3, 8, 13 16 7-1201 9V ± -0.5V 50kHz 25kHz 1, 2, 5, 6, 10, 11, 14, 15 4, 12 7, 9 Specifications CD4517BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued) OSCILLATOR FUNCTION Irradiation (Note 2) 9V ± -0.5V OPEN GROUND VDD 1, 2, 5, 6, 10, 11, 14, 15 8 3, 4, 7, 9, 12, 13, 16 50kHz 25kHz NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram CL D * CL CL 1 D Q * CL CL 2 D Q CL CL 15 D Q Q16* CL CL 16 D Q WE WE p p n n WE WE CL CL 17 D Q CL CL 31 D Q VDD WE WE * WE WE VSS WE VDD CL CL VDD CL CL 33 D Q 32 D SAME AS STAGES Q32* 16 WE WE Q VSS CL CL 47 D Q CL CL 48 D SAME AS STAGES Q48* 16 & 32 WE WE Q CL CL 49 D Q CL CL 63 D Q CL CL 64 D SAME AS STAGES WE 16, 32, 48 EXCEPT WE FOR Q* Q VSS * All inputs protected by CMOS protection network. Q32* Q48* Q64* FIGURE 1. LOGIC BLOCK DIAGRAM TRUTH TABLE CLOCK WRITE ENABLE DATA STAGE 16 TAP STAGE 32 TAP STAGE 48 TAP STAGE 64 TAP 0 0 X Q16 Q32 Q48 Q64 0 1 X Z Z Z Z 1 0 X Q16 Q32 Q48 Q64 1 1 X Z Z Z Z 0 DI In Q16 Q32 Q48 Q64 1 DI In D17 In D33 In D49 In Z 0 X Q16 Q32 Q48 Q64 1 X Z Z Z Z 1 = HIGH LEVEL 0 = LOW LEVEL X = DON’T CARE Z = HIGH IMPEDANCE 7-1202 CD4517BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -15 -20 -25 -15V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -10 -10V FIGURE 3. MINIMUM N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -30 -5 -10V -10 -15V -15 FIGURE 5. MINIMUM P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (fTHL, fTLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) - ns 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 4. TYPICAL P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 300 250 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics SUPPLY VOLTAGE (VDD) = 5V 200 150 100 10V 50 200 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 15V 0 0 20 40 60 80 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE 0 0 100 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 7-1203 CD4517BMS Typical Performance Characteristics 105 8 6 4 POWER DISSIPATION (PD) - µW 2 104 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 8 6 4 103 (Continued) 10V 10V 5V 2 8 6 4 2 102 8 6 4 CL = 50pF 2 CL = 15pF 10 2 4 68 10 2 4 6 8 2 2 4 6 8 101 103 102 INPUT FREQUENCY (fIN) (kHz) 4 6 8 104 FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY Waveforms and Test Circuits CLK 1 2 16 17 18 33 ts trel WE ts ts tH tH D tPHL tPLH Q48/49, Q32/33, Q16/17 HIGH Z Q64 FIIGURE 9. DYNAMIC TEST WAVEFORMS VDD CL Q Q Q Q D C 16 32 48 64 WE D C D C WE Q16 Q32 Q48Q64 50µF VSS ID CL CL fo C CL VDD VSS VDD D (f = 1/2 fo) VSS REPETITIVE WAVEFORM FIGURE 10. DYNAMIC POWER DISSIPATION TEST CIRCUIT AND WAVEFORMS 7-1204 CD4517BMS Chip Dimensions and Pad Layouts 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 143 106 100 90 80 70 60 103-111 (2.617-2.819) 50 40 30 20 10 0 4-10 (0.102-0.254) 140-148 (3.556-3.759) Dimensions in parentheses are in milimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch.) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 1205 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029