CD40108BMS CMOS 4 x 4 Multiport Register December 1992 Features Description • High Voltage Type (20V Rating) The CD40108BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses. • Four 4-Bit Registers • One Input and Two Output Buses • Unlimited Expansion in Bit and Word Directions • Data Lines have latched Inputs • 3-State Outputs • Separate Control of Each Bus, Allowing Simultaneous Independent Reading of Any of Four Registers on Bus A and Bus B and Independent Writing Into Any of the Four Registers • CD40108BMS is Pin-Compatible with Industry Type MC14580 • Standardized Symmetrical Output Characteristics When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high-impedance state. The high-impedance third state provides the outputs with the capability of being connected to the bus lines in a bus-organized system without the need for interface or pull-up components. When the WRITE ENABLE input is high, all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines. When WRITE ENABLE is low, the CLOCK is inhibited and no new data is entered. In either case, the contents of any word may be accessed via the read address lines independent of the state of the CLOCK input. The CD40108BMS is supplied in these 24-lead outline packages: • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Braze Seal DIP Ceramic Flatpack H4V H4P Applications • Scratch-Pad Memories • 5V, 10V and 15V Parametric Ratings • Arithmetic Units • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” • Data Storage Pinout Functional Diagram WRITE ENABLE CD40108BMS TOP VIEW D0 Q3 B 1 24 VDD Q2 B 2 23 Q1 B 3-STATE A 3 22 Q0 B DATA INPUTS D1 D2 D3 Q0 A 4 21 3-STATE B Q1 A 5 20 D0 WRITE 0 Q2 A 6 19 D1 WRITE 1 Q3 A 7 18 D2 WRITE 0 8 17 D3 WRITE 1 9 16 CLOCK READ 1B 10 15 WRITE ENABLE READ 0B 11 14 READ 1A VSS 12 13 READ 0A READ 1A READ 0A READ 1B READ 0B VDD = 24 VSS = 12 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-25 3-STATE A 15 3 20 4 19 5 Q1 18 6 Q2 17 7 Q3 Q0 WORD A OUTPUT 8 9 22 14 23 13 2 1 10 Q0 Q1 Q2 WORD B OUTPUT Q3 11 16 CLOCK 21 3-STATE B File Number 3356 Specifications CD40108BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current SYMBOL IDD IIL TEMPERATURE MIN MAX 1 +25oC - 10 µA 2 +125oC - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VDD = 20V, VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH LIMITS GROUP A SUBGROUPS CONDITIONS (NOTE 1) VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 UNITS - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA -2.8 -0.7 V 0.7 2.8 V N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B Functional F Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V IOZH VIN = VDD or GND VOUT = VDD V -55oC +25oC, Tri-State Output Leakage VOH > VOL < VDD/2 VDD/2 +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V 1, 2, 3 +25oC, +125oC, -55oC - 4 V 1, 2, 3 +25oC, +125oC, -55oC 11 - V 1 +25oC -0.4 - µA 2 +125oC -12 - µA VDD = 18V 3 -55oC -0.4 - µA VDD = 20V 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-26 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD40108BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay Clock or Write Enable to Q TPHL1 TPLH1 GROUP A SUBGROUPS TEMPERATURE CONDITIONS VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay Read or Write Address to Q TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay 3State Disable Delay Time TPZH TPHZ VDD = 5V, VIN = VDD or GND (Note 2, 3) Propagation Delay 3State Disable Delay Time TPZL TPLZ VDD = 5V, VIN = VDD or GND (Note 2, 3) Transition Time TTHL TTLH VDD = 5V, VIN = VDD or GND (Note 1, 2) Maximum Clock Input Frequency FCL VDD = 5V, VIN = VDD or GND (Note 1, 2) 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 720 ns - 972 ns - 600 ns - 810 ns - 200 ns - 270 ns - 260 ns - 351 ns - 200 ns - 270 ns 1.5 - MHz 1.11 - MHz NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 -55 C, +25 C - 10 µA +125oC - 300 µA - 10 µA o -55oC, o +25oC - 600 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA oC +125 Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 7-27 +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA Specifications CD40108BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH10 CONDITIONS VDD = 10V, VOUT = 9.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -0.9 mA -55 C - -1.6 mA +125oC - -2.4 mA - -4.2 mA - 3 V o Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 -55 Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 oC +25oC, +125oC, -55oC Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V 1, 2, 3 +25oC - 280 ns Propagation Delay Clock or Write Enable to Q TPLH1 TPHL1 VDD = 10V VDD = 15V 1, 2, 3 +25 C - 200 ns Propagation Delay Read or Write Address to Q TPHL2 TPLH2 VDD = 10V 1, 2, 3 +25oC - 240 ns VDD = 15V 1, 2, 3 +25oC - 170 ns Propagation Delay 3-State Disable Delay Time TPZH TPHZ VDD = 10V 1, 2, 4 +25oC - 100 ns VDD = 15V 1, 2, 4 +25oC - 80 ns Propagation Delay 3-State Disable Delay Time TPZL TPLZ VDD = 10V 1, 2, 4 +25oC - 120 ns VDD = 15V 1, 2, 4 +25 C - 100 ns Transition Time TTLH TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC 3.5 - MHz VDD = 15V 1, 2, 3 +25 oC 4.5 - MHz VDD = 5V 1, 2, 3 +25oC Maximum Clock Input Frequency FCL Minimum Data Setup Time Data to Clock TS Minimum Data Setup Time Write Enable to Clock TS Minimum Data Setup Time Write Address to Clock TS Clock Rise and Fall Time Minimum Hold Time Data to Clock Hold Time Write Enable to Clock Write Address to Clock VDD = 10V VDD = 10V TH TH TH o o 0 ns 0 ns 1, 2, 3 +25 C VDD = 15V 1, 2, 3 +25 oC 0 ns VDD = 5V 1, 2, 3 +25oC 250 ns 1, 2, 3 +25 oC 100 ns VDD = 15V 1, 2, 3 +25oC 70 ns VDD = 5V 1, 2, 3 +25oC 250 ns VDD = 10V 1, 2, 3 +25oC 100 ns 70 VDD = 10V TRCL TFCL o VDD = 15V 1, 2, 3 +25oC VDD = 5V 1, 2, 3, 5 +25oC - 15 ns VDD = 10V 1, 2, 3, 5 +25oC - 5 ns VDD = 15V 1, 2, 3, 5 +25oC - 5 ns VDD = 5V 2, 3 +25oC 220 ns VDD = 10V 2, 3 +25oC 100 ns VDD = 15V 2, 3 +25oC 80 ns 2, 3 +25oC - 270 ns VDD = 10V 2, 3 +25oC - 130 ns VDD = 15V 2, 3 +25oC - 80 ns 2, 3 +25oC - 330 ns VDD = 10V 2, 3 +25oC - 140 ns VDD = 15V 2, 3 +25oC - 90 ns VDD = 5V VDD = 5V 7-28 ns Specifications CD40108BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Clock Pulse Width Clock or Write Enable Minimum Clock Pulse Width Write Address Input Capacitance SYMBOL TW CONDITIONS VDD = 5V TW TEMPERATURE MIN MAX UNITS 3 +25oC - 350 ns o VDD = 10V 3 +25 C - 130 ns VDD = 15V 3 +25oC - 90 ns 3 +25 oC - 300 ns VDD = 10V 3 +25oC - 150 ns VDD = 15V 3 +25oC - 90 ns oC - 7.5 pF VDD = 5V CIN NOTES Any Input 1, 2 +25 NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA o -2.8 -0.2 V o N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F VDD = 10V, ISS = -10µA 1, 4 +25 C VDD = 10V, ISS = -10µA 1, 4 +25 C - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND 1, 4 +25 C - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns o VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) MIL-STD-883 METHOD GROUP A SUBGROUPS 100% 5004 1, 7, 9 7-29 READ AND RECORD IDD, IOL5, IOH5A Specifications CD40108BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B READ AND RECORD IDD, IOL5, IOH5A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group D Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 1 1, 7, 9 Table 4 1, 9 Table 4 Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 1, 2, 4 - 7, 22, 23 3, 8 - 12 24 Static Burn-In 2 (Note 1) 1, 2, 4 - 7, 22, 23 2 3, 8 - 11, 13 - 21, 24 Dynamic BurnIn (Note 1) - 2 3, 15, 16, 21, 24 1, 2, 4 - 7, 22, 23 2 3, 8 - 11, 13 - 21, 24 Irradiation (Note 2) 9V ± -0.5V 50kHz 25kHz 1, 2, 4 - 7, 22, 23 8, 11, 14, 19, 20 9, 10, 13, 17, 18 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 30 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CD40108BMS Block Diagram W0 CL WE W1 DEC R0A R1A R0B R1B DEC DEC ENABLE A Q0 A Q1 A WORD A OUTPUT Q2 A 4X4 MEMORY D0 Q3 A D1 DATA INPUT D2 Q0 B D3 Q1 B WORD B OUTPUT Q2 B Q3 B ENABLE B FIGURE 1. TRUTH TABLE WRITE WRITE CLOCK ENABLE 1 WRITE 0 READ 1A READ 0A READ 1B READ 0B 1 S1 S2 S1 S2 S1 S2 X X ENABLE ENABLE A B 1 1 DN QnA QnB 1 1 1 1 S1 S2 S1 S2 S1 S2 1 1 0 0 0 X X X X X X X 0 0 X Z Z 1 0 0 0 1 1 0 1 1 Dn to word Word 1 0 out Word 2 out 0 0 0 0 1 1 0 1 1 Word 0 Word 1 not altered out Word 2 out X X X 1 0 0 1 1 1 X X X X X X X X 1 1 X 1 = High Level 0 = Low Level X = Don’t Care Word 2 out Word 1 out NC NC Z = High Impedance S! and S2 refer to input states of either 1 or 0 AMBIENT TEMPERATURE (TA) = +25oC 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MIMIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-31 CD40108BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -5 -10 -15 -10V -20 -25 -15V -30 -35 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -10 -15V FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 525 TRANSITION TIME (tTHL, tTLH) (ns) PROPAGATION DELAY TIME (tPLH, tPHL) (ns) 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 (Continued) 450 SUPPLY VOLTAGE (VDD) = 5V 375 300 225 10V 150 75 15V 200 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 10 20 30 40 50 60 70 80 90 100 0 20 40 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CL OR WE TO Q) 106 8 POWER DISSIPATION (PD) (µW) 6 4 105 60 80 FIGURE 7. TYPICAL TRANSISTION TIME AS A FUNCTION OF LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 2 8 6 4 104 2 10V 8 6 4 103 10V 5V 2 8 6 4 102 CL = 50pF CL = 15pF 2 2 1 100 LOAD CAPACITANCE (CL) (pF) 4 68 2 4 68 2 4 68 2 103 10 102 INPUT FREQUENCY (fI) (kHz) 4 68 2 4 68 104 FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY 7-32 R0A 13 * 14 R1A * R0B 11 * 10 Schematic Diagram * R1B 3-STATE C *A ENABLE 3 C *CLOCK 16 *WRITE ENABLE 15 *W0 8 A *W1 B QA D 9 W QB A B QA D W QB A B QA D W QB A B QA D W 4 Q0A 5 Q1A 6 Q2A 7 Q3A 22 Q0B 23 Q1B 2 Q2B 1 Q3B QB C 20 p n C A C B QA D p n W QB A B QA D W QB A B QA D W QB A B QA D W QB C C *D1 19 p n C C p n C A D W C *D2 18 B QA QB A B QA D W QB A B QA D W QB A B QA D W QB p n C C p n C *D3 17 C A B QA D W QB A B QA D W QB A B QA D W QB A B QA D W QB p n C 21 p n 3-STATE *B ENABLE C C *ALL INPUTS PROTECTED BY COS/MOS INPUT PROTECTION NETWORK CD40108BMS 7-33 FIGURE 9. *D0 CD40108BMS Schematic Diagram (Continued) A p n D p n ENABLE VDD QA VDD INPUT p n W OUTPUT B p n VSS VSS QB DETAIL OF MEMORY CELL DETAIL OF 3-STATE OUTPUTS FIGURE 9. (Continued) trCL tfCL tW(CL) CL tH(D) tS(D) Dn tS(WE) tH(WE) tH(WA) WE tS(WA) tW(WA) WA RA tPHL tPLH tPLH tPHL tPLH tPHL Qn tTLH tTHL FIGURE 10. TIMING DIAGRAM 0.1 µF VDD 500 µF ID CL CL CL CL CL PULSE GEN. 3 CL 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CL P.G. 1 CL (FI) P.G. 2 P.G. 3 PULSE GEN. 2 Qn A, B PULSE GEN. 1 REPETITIVE WAVEFORMS FIGURE 11. POWER-DISSIPATION TEST CIRCUIT AND WAVEFORMS 7-34 CD40108BMS Q 1kΩ TO ANY OUTPUT 50pF 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 PULSE GEN. 2 P.G. 1 CL P.G. 2 ENABLE ENABLE INPUT 50% VDD 50% VSS D tPLZ Q OUTPUTS PULSE GEN. 1 10% 90% tPHZ CHAR tPHZ tPZH tPLZ tPZL TEST VOLTAGE AT D AT Q VDD VSS VDD VSS VSS VDD VSS VDD FIGURE 12. OUTPUT-ENABLE-DELAY-TIMES TEST CIRCUIT AND WAVEFORMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-35 tPZL VDD 90% VOL VOH 10% VSS tPZH