TI CD74AC253M

CD74AC253,
CD54/74ACT253
Data sheet acquired from Harris Semiconductor
SCHS247A
Dual 4-Input Multiplexer, Three-State
August 1998 - Revised May 2000
Features
Description
• Buffered Inputs
The CD74AC253 and ’ACT253 dual 4-input multiplexers that
utilize Advanced CMOS Logic technology. One of the four
sources for each section is selected by the common Select
inputs, S0 and S1. When the Output Enable (1OE or 2OE) is
HIGH, the output is in the high-impedance state.
• Typical Propagation Delay
- 6.3ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
Ordering Information
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
PART
NUMBER
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
CD74AC253E
TEMP.
RANGE (oC)
0 to 70oC, -40 to 85,
PACKAGE
16 Ld PDIP
-55 to 125
• Balanced Propagation Delays
CD74AC253M
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
0 to 70oC, -40 to 85,
-55 to 125
CD54ACT253F3A
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
-55 to 125
16 Ld SOIC
16 Ld CERDIP
CD74ACT253E
0 to 70oC, -40 to 85,
-55 to 125
16 Ld PDIP
CD74ACT253M
0 to 70oC, -40 to 85,
-55 to 125
16 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information.
Pinout
CD54ACT253
(CERDIP)
CD74AC253, CD74ACT253
(PDIP, SOIC)
TOP VIEW
1OE 1
16 VCC
S1 2
15 2OE
1I3 3
14 S0
1I2 4
13 2I3
1I1 5
12 2I2
1I0 6
11 2I1
1Y 7
10 2I0
GND 8
9 2Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated.
1
CD74AC253, CD54/74ACT253
Functional Diagram
1
1OE
6
1I0
5
1I1
7
1Y
SEL/MUX
4
1I2
3
1I3
S0
S1
2I0
2I1
2I2
2I3
2OE
14
2
10
11
9
2Y
SEL/MUX
12
13
GND = 8
VCC = 16
15
TRUTH TABLE
SELECT INPUTS
DATA INPUTS
ENABLE
INPUTS
OUTPUT
S1
S0
nI0
nI1
nI2
nI3
nOE
nY
X
X
X
X
X
X
H
Z
L
L
L
X
X
X
L
L
L
L
H
X
X
X
L
H
L
H
X
L
X
X
L
L
L
H
X
H
X
X
L
H
H
L
X
X
L
X
L
L
H
L
X
X
H
X
L
H
H
H
X
X
X
L
L
L
H
H
X
X
X
H
L
H
Select inputs S1 and S0 are common to both sections. H = High level, L = Low inputs, X = Don’t care, Z = High impedance.
2
CD74AC253, CD54/74ACT253
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . 150C
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
3
2.1
-
2.1
-
2.1
-
V
5.5
3.85
-
3.85
-
3.85
-
V
1.5
-
0.3
-
0.3
-
0.3
V
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
1.5
1.4
-
1.4
-
1.4
-
V
AC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
VOH
-
VIH or VIL
-
-0.05
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
3
CD74AC253, CD54/74ACT253
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output Voltage
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VOL
VIH or VIL
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
Input Leakage Current
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
Three-State Leakage
Current
IOZ
VIH or VIL
VO = VCC
or GND
-
5.5
-
±0.5
-
±5
-
±10
µA
Quiescent Supply Current
MSI
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
High Level Input Voltage
VIH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
VIL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
ACT TYPES
Low Level Output Voltage
VOL
VIH or VIL
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
Three-State or Leakage
Current
IOZ
VIH or VIL
VO = VCC
or GND
-
5.5
-
±0.5
-
±5
-
±10
µA
Quiescent Supply Current
MSI
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
Input Leakage Current
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
4
CD74AC253, CD54/74ACT253
ACT Input Load Table
INPUT
UNIT LOAD
S0, S1, nI0, nI1
1
nOE
0.83
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
PARAMETER
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
227
-
-
250
ns
3.3
(Note 9)
7.2
-
25
7
-
28
ns
5
(Note 10)
5.2
-
18.2
5
-
20
ns
1.5
-
-
151
-
-
166
ns
3.3
4.8
-
16.9
4.7
-
18.6
ns
5
3.4
-
12.1
3.3
-
13.3
ns
1.5
-
-
131
-
-
144
ns
3.3
4.5
-
15.7
4.3
-
17.3
ns
5
3
-
10.5
2.9
-
11.5
ns
AC TYPES
Propagation Delay,
S0, S1, to Y
Propagation Delay,
nI to Y
Propagation Delay,
Output Enable,
Output Disable to Y
tPLH, tPHL
tPLZ, tPHZ,
tPZL, tPZH
Three-State Output
Capacitance
CO
-
-
-
15
-
-
15
pF
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
107
-
-
107
-
pF
Propagation Delay,
S0, S1, to Y
tPLH, tPHL
5
(Note 10)
5.7
-
20
5.5
-
22
ns
Propagation Delay,
nI to Y
tPLH, tPHL
5
4.6
-
16.4
4.5
-
18
ns
Propagation Delay,
Output Enable,
Output Disable to Y
tPLZ, tPHZ,
tPZL, tPZH
5
3.2
-
11.5
3.2
-
12.6
ns
Three-State Output
Capacitance
CO
-
-
-
15
-
-
15
pF
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
107
-
-
107
-
pF
Power Dissipation Capacitance
ACT TYPES
Power Dissipation Capacitance
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CPD is used to determine the dynamic power consumption per multiplexer.
AC: PD = VCC2 fi (CPD + CL)
ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
5
CD74AC253, CD54/74ACT253
tr = 3ns
tf = 3ns
INPUT LEVEL
90%
OUTPUT
DISABLE
VS
10%
GND
tPZL
tPLZ
VS
0.2VCC
OUTPUT: LOW
TO OFF TO LOW
tPHZ
tPZH
VOH (≠ VCC)
0.8 VCC
VS
OUTPUT: HIGH
TO OFF TO HIGH
OUTPUTS
ENABLED
OTHER
INPUTS
(TIED HIGH
OR LOW)
OUTPUTS
DISABLED
OUTPUT
DISABLE
OUTPUTS
ENABLED
GND (tPHZ, tPZH)
OPEN (tPHL, tPLH)
2 VCC (tPLZ, tPZL)
(OPEN DRAIN)
500Ω†
RL
DUT
WITH
THREESTATE
OUTPUT
VOL (≠ GND)
OUT
500Ω†
RL
CL
50pF
†FOR AC SERIES ONLY: WHEN VCC = 1.5V, RL = 1kΩ
FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT
tr = 3ns
tf = 3ns
INPUT
LEVEL
90%
VS
10%
I OR S
VS
OUTPUT Y
tPLH
tPHL
FIGURE 2. PROPAGATION DELAY TIMES
OUTPUT
RL (NOTE)
500Ω
DUT
OUTPUT
LOAD
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
AC
ACT
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
Input Level
FIGURE 3. PROPAGATION DELAY TIMES
6
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Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
CD54ACT253F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
CD74AC253M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC253M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC253M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC253M96G4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC253ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC253MG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT253E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74ACT253EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74ACT253M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT253M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT253M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT253M96G4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT253ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT253MG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74AC253M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD74ACT253M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74AC253M96
SOIC
D
16
2500
333.2
345.9
28.6
CD74ACT253M96
SOIC
D
16
2500
333.2
345.9
28.6
Pack Materials-Page 2
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