CD74ACT74-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCHS349A − DECEMBER 2003 − REVISED JANUARY 2008 D Qualified for Automotive Applications D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With D D D M PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current − Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q description/ordering information The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION† −40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA SOIC − M Tape and reel TOP-SIDE MARKING CD74ACT74QM96Q1 ACT74Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE (each flip-flop) INPUTS § OUTPUTS PRE CLR CLK D Q L H X X H Q L H L X X L H L L X X H§ H§ H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74ACT74-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCHS349A − DECEMBER 2003 − REVISED JANUARY 2008 logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25°C −40°C to 125°C UNIT MIN MAX MIN MAX 4.5 5.5 4.5 5.5 VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 0 VCC VO Output voltage 0 VCC IOH High-level output current −24 IOL Low-level output current ∆t/∆v Input transition rise or fall rate 2 2 0.8 V V 0.8 V 0 VCC V 0 VCC V −24 mA 24 24 mA 10 10 ns/V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74ACT74-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCHS349A − DECEMBER 2003 − REVISED JANUARY 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN VOH VOL VI = VIH or VIL VI = VIH or VIL II VI = VCC or GND ICC VI = VCC or GND, DICC‡ −40°C to 125°C TA = 25°C MAX IOH = −50 µA 4.5 V 4.4 IOH = −24 mA 4.5 V 3.94 IOH = −50 mA† 5.5 V IOL = 50 µA 4.5 V 0.1 IOL = 24 mA 4.5 V 0.36 IOL = 50 mA† 5.5 V IO = 0 UNIT MAX 4.4 3.7 V 3.85 0.1 0.5 V 1.65 5.5 V ±0.1 ±1 µA 5.5 V 4 80 µA 2.4 3 mA 10 10 pF 4.5 V to 5.5 V VI = VCC − 2.1 V MIN Ci † Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 75-Ω transmission-line drive capability at 125°C. ‡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load ACT INPUT LOAD TABLE INPUT UNIT LOAD Data 0.53 PRE or CLR 0.58 CLK 1 Unit load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) −40°C to 125°C MIN fclock Clock frequency 85 PRE or CLR low tw Pulse duration tsu th trec UNIT MAX MHz 5 ns CLK 5.7 Setup time Data 4 ns Hold time Data after CLK↑ 0 ns Recovery time, before CLK↑ CLR↑ or PRE↑ 2.7 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD74ACT74-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCHS349A − DECEMBER 2003 − REVISED JANUARY 2008 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL tPLH tPHL −40°C to 125°C MIN 85 CLK Q or Q PRE or CLR Q or Q UNIT MAX MHz 2.4 9.5 2.4 9.5 2.9 11.5 3.1 12.5 ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP UNIT 55 pF CD74ACT74-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCHS349A − DECEMBER 2003 − REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 R1 = 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) R2 = 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw 3V 1.5 V Input LOAD CIRCUIT 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input 3V Reference Input 3V 1.5 V 1.5 V 0V 0V trec Data Input 3V 1.5 V CLK th tsu 1.5 V 10% 90% 90% tr 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V 1.5 V 10% 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3V Input 1.5 V 1.5 V 0V tPLH In-Phase Output 50% 10% 90% 90% tr 90% 1.5 V 1.5 V 0V tPHL tPHL Out-of-Phase Output 3V Output Control VOH 50% VCC 10% VOL tf Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH 50% VCC 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tPZL tPLZ 20% VCC tPZH Output Waveform 2 S1 at GND (see Note B) ≈VCC 20% VCC VOL tPHZ 80% VCC VOH 80% VCC ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty 2500 CD74ACT74QM96G4Q1 ACTIVE SOIC D 14 CD74ACT74QM96Q1 OBSOLETE SOIC D 14 Eco Plan (2) Green (RoHS & no Sb/Br) TBD Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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