CD74HC20-Q1 HIGH-SPEED CMOS LOGIC DUAL 4-INPUT NAND GATE SCLS522 – AUGUST 2003 D D D D D D D D D Qualification in Accordance With AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 1000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Buffered Inputs Typical Propagation Delay 8 ns at VCC = 5 V, CL = 15 pF, TA = 25°C Fanout (Over Temperature Range) – Standard Outputs . . . 10 LSTTL Loads – Bus Driver Outputs . . . 15 LSTTL Loads D D Significant Power Reduction Compared to LSTTL Logic ICs VCC Voltage = 2 V to 6 V High Noise Immunity; NIL or NIH = 30% of VCC, VCC = 5 V D PACKAGE (TOP VIEW) 1A 1B NC 1C 1D 1Y GND Balanced Propagation Delay and Transition Times 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2D 2C NC 2B 2A 2Y NC – No internal connection † Contact factory for details. Q100 qualification data available on request. description/ordering information The CD74HC20 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates, with the low power consumption of standard CMOS integrated circuits. The device has the ability to drive 10 LSTTL loads. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING –40°C to 125°C SOIC – D Tape and reel CD74HC20QDRQ1 HC20QQ1 ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS A B C D OUTPUT Y L X X X H X L X X H X X L X H X X X L H H H H H L H = High voltage level, L = Low voltage level X = Irrelevant Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74HC20-Q1 HIGH-SPEED CMOS LOGIC DUAL 4-INPUT NAND GATE SCLS522 – AUGUST 2003 logic diagram (positive logic) nA nB nY nC nD absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < –0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < –0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Switch current per output pin, IO (VO > –0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are referenced to GND, unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V MIN MAX 2 6 UNIT V 1.5 V 3.15 4.2 0.5 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 VCC VCC 1000 Input transition (rise and fall) time VCC = 2 V VCC = 4.5 V 0 tt 0 500 VCC = 6 V 0 400 VCC = 4.5 V VCC = 6 V 1.35 V 1.8 V V ns TA Operating free-air temperature –40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74HC20-Q1 HIGH-SPEED CMOS LOGIC DUAL 4-INPUT NAND GATE SCLS522 – AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IO (mA) TEST CONDITIONS CMOS loads VOH VI = VIH or VIL TTL loads CMOS loads VOL VI = VIH or VIL TTL loads II ICC VI = VCC or GND VI = VCC or GND VCC MIN TA = 25°C TYP MAX MIN –0.02 2V 1.9 1.9 –0.02 4.5 V 4.4 4.4 –0.02 6V 5.9 5.9 3.7 MAX UNIT V –4 4.5 V 3.98 –5.2 6V 5.48 0.02 2V 0.1 0.1 0.02 4.5 V 0.1 0.1 0.02 6V 0.1 0.1 4 4.5 V 0.26 0.4 5.2 6V 0.26 0.4 6V ±0.1 ±1 µA 2 40 µA 10 10 pF 0 5.2 6V CIN V switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) A, B, C, D TO (OUTPUT) Y VCC 2V 100 150 CL = 50 pF 4.5 V 20 30 6V 17 26 2V 75 110 4.5 V 15 22 6V 13 19 CL = 15 pF tt TA = 25°C TYP MAX LOAD CAPACITANCE CL = 50 pF MIN 5V MIN MAX UNIT ns 8 ns operating characteristics, VCC = 5 V, TA = 25°C, Input tr, tf = 6 ns PARAMETER Cpd TYP Power dissipation capacitance (see Note 4) 26 UNIT pF NOTE 4: Cpd is used to determine the dynamic power consumption, per gate. PD = VCC2 fI (Cpd + CL) fI = input frequency CL = output load capacitance VCC = supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD74HC20-Q1 HIGH-SPEED CMOS LOGIC DUAL 4-INPUT NAND GATE SCLS522 – AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd VEE LOAD CIRCUIT Input 50% VCC 50% VCC tPLH tPHL VCC 0V In-Phase Output 50% 10% 90% 90% tr tPHL Out-of-Phase Output 90% VOH 50% VCC 10% VOL tf 50% VCC 10% tf 50% 10% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% VCC 0V tPLZ ≈VCC Output Waveform 1 (see Note B) 50% VCC Output Waveform 2 (see Note B) 10% VOL tPHZ tPZH VOH VOL 50% VCC tPZL tPLH 90% VCC Output Control 50% VCC 90% VOH ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CD74HC20QM96Q1 OBSOLETE SOIC D Pins Package Eco Plan (2) Qty 14 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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