CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
D
D
D
D
D
D
D
D
D
D
Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 200 MHz
Low Jitter (cyc–cyc): ±75 ps
Distributes One Differential Clock Input to
Ten Differential Outputs
Three-State Outputs When the Input
Differential Clocks Are <20 MHz
Operates From Dual 2.5-V Supplies
48-Pin TSSOP Package
Consumes < 200-µA Quiescent Current
External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
description
DGG PACKAGE
(TOP VIEW)
GND
Y0
Y0
VDDQ
Y1
Y1
GND
GND
Y2
Y2
VDDQ
VDDQ
CLK
CLK
VDDQ
AVDD
AGND
GND
Y3
Y3
VDDQ
Y4
Y4
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
GND
Y5
Y5
VDDQ
Y6
Y6
GND
GND
Y7
Y7
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
VDDQ
Y9
Y9
GND
The CDCV857 is a high-performance, low-skew,
19
30
low-jitter zero delay buffer that distributes a
20
29
differential clock input pair (CLK, CLK) to ten
21
28
differential pairs of clock outputs (Y[0:9], Y[0:9])
22
27
and one differential pair of feedback clock output
23
26
(FBOUT, FBOUT). The clock outputs are
24
25
controlled by the clock inputs (CLK, CLK), the
feedback clocks (FBIN, FBIN), and the analog
power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When
PWRDWN is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power
mode). The device also enters this low power mode when the input frequency falls below a suggested detection
frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low
frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and
enables the outputs.
When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857 is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV857 is characterized for operation from 0°C
to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
FUNCTION TABLE
(Select Functions)
INPUTS
OUTPUTS
PLL
AVDD
GND
PWRDWN
CLK
CLK
Y[0:9]
Y[0:9]
FBOUT
FBOUT
H
L
H
L
H
L
H
Bypassed/Off
GND
H
H
L
H
L
H
L
Bypassed/Off
X
L
L
H
Z
Z
Z
Z
Off
X
L
H
L
Z
Z
Z
Z
Off
2.5 V (nom)
H
L
H
L
H
L
H
On
2.5 V (nom)
H
H
L
H
L
H
L
On
2.5 V (nom)
X
<20 MHz
<20 MHz
Z
Z
Z
Z
Off
functional block diagram
3
2
PWRDWN
AVDD
5
37
16
6
Powerdown
and Test
Logic
10
9
20
19
22
23
46
47
CK
CK
FBIN
FBIN
13
44
14
36
43
PLL
39
35
40
29
30
27
26
32
33
2
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• DALLAS, TEXAS 75265
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
Terminal Functions
TERMINAL
NAME
AGND
NO.
I/O
DESCRIPTION
Ground for 2.5-V analog supply
17
2.5-V Analog supply
AVDD
CLK, CLK
13, 14
I
Differential clock input
FBIN, FBIN
35, 36
I
Feedback differential clock input
32, 33
O
Feedback differential clock output
FBOUT, FBOUT
GND
16
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
PWRDWN
37
Ground
I
Output enable for Y and Y
VDDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
2.5-V Supply
Y[0:9]
3, 5, 10,
20, 22, 27,
29, 39, 44,
46
O
Buffered output copies of input clock, CLK
Y[0:9]
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
O
Buffered output copies of input clock, CLK
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDDQ, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current to GND or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
recommended operating conditions (see Note 4)
MIN
Supply voltage, VDDQ, AVDD
TYP
PWRDWN
CLK, CLK, FBIN, FBIN
High level input voltage,
voltage VIH
PWRDWN
V
–0.3
VDDQ/2 – 0.18
0.7
V
VDDQ/2 + 0.18
1.7
DC input signal voltage (see Note 5)
VDDQ + 0.3
VDDQ
–0.3
Differential input signal voltage
voltage, VID (see Note 6)
DC
CLK, FBIN
0.36
AC
CLK, FBIN
0.7
Output differential cross-voltage, VOX (see Note 7)
Input differential pair cross-voltage, VIX (see Note 7)
UNIT
2.7
CLK, CLK, FBIN, FBIN
Low level input voltage
voltage, VIL
MAX
2.3
VDDQ/2 – 0.2
VDDQ/2 – 0.2
High-level output current, IOH
VDDQ + 0.6
VDDQ + 0.6
VDDQ/2
VDDQ/2 + 0.2
VDDQ/2 + 0.2
–12
Low-level output current, IOL
V
V
V
V
V
mA
12
mA
Input slew rate, SR
1
4
V/ns
Operating free-air temperature, TA
0
85
°C
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.
5. DC input signal voltage specifies the allowable dc execution of differential input.
6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.
7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.
4
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• DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
All inputs
VDDQ = 2.3 V,
II = –18 mA
VDDQ = min to max, IOH = –1 mA
MIN
TYP†
MAX
UNIT
–1.2
V
VIK
Input voltage
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
IOH
IOL
VO
Output voltage swing
VOX
Output differential
cross-voltagew
II
Input current
VDDQ = 2.7 V,
VI = 0 V to 2.7 V
±10
µA
IOZ
High-impedance-state
output current
VDDQ = 2.7 V,
VO= VDDQ or GND
±10
µA
IDDPD
Power down current on
VDDQ + AVDD
CLK and CLK = 0 MHz; PWRDWN = Low;
Σ of IDD and AIDD
100
200
µA
fO = 200 MHz
330
Dynamic current on VDDQ
all outputs loaded
as shown in
Figure 3
275
IDD
fO = 167 MHz
250
300
AIDD
Supply current on AVDD
fO = 200 MHz
fO = 167 MHz
10
12
8
10
VDDQ = 2.3 V,
IOH = –12 mA
VDDQ = min to max, IOL = 1 mA
High-level output current
VDDQ = 2.3 V,
VDDQ = 2.3 V,
IOL = 12 mA
VO = 1 V
Low-level output current
VDDQ = 2.3 V,
VO = 1.2 V
Differential outputs are terminated with
120 Ω
VDDQ– 0.1
1.7
V
0.1
V
0.6
–18
–32
mA
26
35
mA
1.1
VDDQ/2 – 0.2
VDDQ– 0.4
VDDQ/2
V
VDDQ/2 + 0.2
mA
mA
CI
Input capacitance
VCC = 2.5 V
VI = VCC or GND
2
2.5
3
pF
CO
Output capacitance
VCC = 2.5 V
VO = VCC or GND
2.5
3
3.5
pF
† All typical values are at respective nominal VDDQ.
‡ The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input
signal voltage and VCP is the complementary input signal voltage.
§ Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
fCK
Operating clock frequency
Application clock frequency
Input clock duty cycle
MIN
MAX
UNIT
60
200
MHz
40%
60%
Stabilization timeW (PLL mode)
10
µs
Stabilization timeW (Bypass mode)
30
ns
¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
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5
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
switching characteristics
PARAMETER
tPLH}
tPHL}
tjit(per)
jit( )w
TEST CONDITIONS
Low to high level propagation delay time
Test mode/CLK to any output
High-to low level propagation delay time
Test mode/CLK to any output
66 MHz
Jitter (period)
(period), See Figure 6
Jitter (cycle-to-cycle),
(cycle to cycle) See Figure 3
tjit(hper)
jit(h )w
Half period jitter,
jitter See Figure 7
Half-period
tslr(i)
tslr(o)
POST OFFICE BOX 655303
ps
ps
75
66 MHz
–160
160
100/133/167/200 MHz
–100
100
1
4
V/ns
V/ns
ps
ps
1
2
66 MHz
–180
180
100/133 MHz
–130
130
167/200 MHz
–90
90
66 MHz
–230
230
100/133 MHz
–170
170
167/200 MHz
–100
100
66/100/133/167 MHz
–100
100
200 MHz
–150
50
75
ps
650
900
ps
tr, tf
Output rise and fall times (20% – 80%)
Load: 120 Ω/14 pF
† All typical values are at a respective nominal VDDQ.
‡ Refers to transition of noninverting output.
§ This parameter is assured by design but can not be 100% production tested.
¶ All differential output pins are terminated with 120 Ω/14 pF.
6
ns
90
–75
100/133/167/200 MHz
SSC on
Output skew, See Figure 5
4.5
75
Dynamic
phase offset ((this includes jjitter),
y
), See
Figure 4(b)
tsk(o)W
ns
180
Output clock slew rate, See Figure 8
offset See Figure 4(a)
Static phase offset,
UNIT
–75
Input clock slew rate, See Figure 8
t(Ø)
MAX
–180
66 MHz
SSC off
td(Ø)w
TYP{
4.5
–90
100/133/167/200 MHz
tjit(cc)
jit( )w
MIN
• DALLAS, TEXAS 75265
ps
ps
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
VDD
V(CK)
R = 60 Ω
R = 60 Ω
VDD/2
V(CK)
CDCV857
GND
Figure 1. IBIS Model Output Load (used for slew rate measurement)
VDD/2
C = 14 pF
CDCV857
R = 10 Ω
Z = 60 Ω
SCOPE
–VDD/2
Z = 50 Ω
R = 50 Ω
V(TT)
Z = 60 Ω
R = 10 Ω
Z = 50 Ω
R = 50 Ω
V(TT)
C = 14 pF
–VDD/2
–VDD/2
NOTE: V(TT)= GND
Figure 2. Output Load Test Circuit
Yx, FBOUT
Yx, FBOUT
tc(n)
tc(n+1)
tjit(cc) = tc(n) – tc(n+1)
Figure 3. Cycle-to-Cycle Jitter
POST OFFICE BOX 655303
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7
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
CK
CK
FBIN
FBIN
t( ) n
∑1
t ( ) n+1
n=N
t( ) =
t( ) n
N
(N is a large number of samples)
(a) Static Phase Offset
CK
CK
FBIN
FBIN
t( )
td( )
t( )
td( )
td( )
(b) Dynamic Phase Offset
Figure 4. Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure 5. Output Skew
8
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td( )
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
tc(n)
Yx, FBOUT
Yx, FBOUT
1
fo
tjit(per) = tcn –
1
fo
Figure 6. Period Jitter
Yx, FBOUT
Yx, FBOUT
t(hper_n+1)
t(hper_n)
1
fo
tjit(hper) = t(hper_n) – 1
2xfo
Figure 7. Half-Period Jitter
80%
80%
VID, VOD
Clock Inputs
and Outputs
20%
20%
tslrr(i), tslrr(o)
tslrf(i), tslrf(o)
Figure 8. Input and Output Slew Rates
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• DALLAS, TEXAS 75265
9
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
10
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCV857DGG
ACTIVE
TSSOP
DGG
48
40
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
CDCV857DGGR
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
CDCV857DGGRG4
PREVIEW
TSSOP
DGG
48
2000
None
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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