PROCESS CP210 Central Small Signal Transistors TM Semiconductor Corp. N - Channel Silicon Amplifer J FET Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 15 x 15 MILS Die Thickness 8.0 MILS Drain Bonding Pad Area 3.2 X 4.0 MILS Source Bonding Pad Area 3.2 X 4.0 MILS Gate Bonding Pad Area 3.2 X 4.0 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Au - 6,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 53,730 PRINCIPAL DEVICE TYPES 2N4416A CMPF4416A BACKSIDE GATE 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R3 (9 -September 2003) Central CP210 PROCESS TM Typical Electrical Characteristics Semiconductor Corp. 16 5 TA = 25°C VGS = 0V TYP. VGS(OFF) = -5.0V 4 12 -1.0V TA = 25°C 4.5 TYP. VGS(OFF) = -5.0V -1.5V -0.5V 3.5 -1.0V -2.0V 3 VGS = 0V 2.5 -0.5V -2.5V 8 -1.5V -2.0V 2 -2.5V 1.5 4 -3.0V 1 -3.5V 0.5 -4.0V 0 0 4 8 12 16 -3.0V -3.5V -4.0V 0 20 0 0.2 VDS, Drain-Source Voltage (V) 0.4 0.6 0.8 1 VDS, Drain-Source Voltage (V) 1.2 1.6 TA = 25°C TA = 25°C VGS = 0V TYP. VGS(OFF) = -1.2V 1 TYP. VGS(OFF) = -1.2V VGS = 0V 1.2 -0.1V 0.8 -0.1V -0.2V 0.6 0.8 -0.2V -0.4V -0.4V 0.2 -0.5V 0 4 8 12 16 -0.5V -0.6V -0.6V 0 -0.3V 0.4 -0.3V 0.4 0 20 VDS, Drain-Source Voltage (V) 0 0.4 0.8 1.2 1.6 2 VDS, Drain-Source Voltage (V) 5 TA = -55°C 4 TA = 25°C 3 TA = 125°C 2 VDG = 15V 1 f = 1kHz VGS(OFF) = -5.0V 0 0.1 1 10 ID, Drain Current (mA) 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R3 (9 -September 2003) Central CP210 PROCESS TM Typical Electrical Characteristics Semiconductor Corp. 16 900 VDS = 15V 14 T A = 25°C 12 800 VDS = 100mV 700 VGS = 0 600 10 VGS(OFF) = -5.0V VGS(OFF) = -1.2V 500 8 400 -2.3V 300 6 -2.3V -5.0V 200 4 100 2 -1.2V 0 -50 0 0 0.8 1.6 2.4 3.2 4 0 50 100 150 TA, Ambient Temperature (°C) VGS, Gate-Source Voltage (-V) 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R3 (9 -September 2003)