CLARE CPC7592BCTR

CPC7592
Line Card Access Switch
Features
Description
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The CPC7592 is a member of Clare’s next generation
Line Card Access Switch family. This monolithic 6-pole
solid-state switch is available in either a 16-pin SOIC
or a 16-pin DFN package. It provides the necessary
functions to replace two 2-Form-C electro-mechanical
relays used on traditional analog and contemporary
integrated voice and data (IVD) line cards found in
Central Office, Access, and PBX equipment. Because
this device contains solid state switches for tip and ring
line break, ringing injection/return and test access it
requires only a +5V supply for operation and
logic-level inputs for control.
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TTL logic level inputs for 3.3V logic interfaces
Smart logic for power up / hot plug state control
Small 16-pin SOIC or 16-Pin DFN Package
DFN package printed-circuit board footprint is 60
percent smaller than the SOIC version, 70 percent
smaller than 4th generation EMR solutions.
Monolithic IC reliability
Low matched RON
Eliminates the need for zero cross switching
Flexible switch timing to transition from ringing mode
to talk mode.
Clean, bounce-free switching
Tertiary protection consisting of integrated current
limiting, voltage clamping, and thermal shutdown for
SLIC protection
5 V operation with power consumption < 10 mW
Intelligent battery monitor
Latched logic-level inputs, no external drive circuitry
required
The CPC7592 is very similar to the Clare CPC7582
with the addition of controlled start-up states and TTL
compatible logic inputs.
The CPC7592xC logic provides alternative test states
from the CPC7592xA/B and while also providing
greater protection SCR trigger and hold current
ratings.
Applications
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Ordering Information
VoIP Gateways
Central office (CO)
Digital Loop Carrier (DLC)
PBX Systems
Digitally Added Main Line (DAML)
Hybrid Fiber Coax (HFC)
Fiber in the Loop (FITL)
Pair Gain System
Channel Banks
CPC7592 part numbers are specified as shown here:
B - 16-pin SOIC delivered 50/Tube, 1000/Reel
M - 16-pin DFN delivered 52/Tube, 1000/Reel
CPC7592 x x xx
TR - Add for Tape & Reel Version
A - With Protection SCR
B - Without Protection SCR
C - With Protection SCR and “Monitor Test State”
Figure 1. CPC7592 Block Diagram
+5VDC
TTEST
5
4 TRINGING
6 VDD
CPC7592
Tip
TLINE 3
X SW5 XSW3
X
2 TBAT
SW1
Secondary
Protection
Ring
SLIC
SW2
RLINE 14
15 RBAT
X
X SW6 X SW4
VREF
12
RTEST
13 RRINGING
300Ω
(min.)
VBAT
1
FGND
SCR Trip Circuit
(CPC7592xA/C)
16
VBAT
L
A
T
C
H
Switch
Control
Logic
8
DGND
10
11
INTEST
INRINGING
LATCH
7
RINGING
DS-CPC7592 - R03
9
TSD
Pb
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RoHS
2002/95/EC
e3
1
CPC7592
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6.2 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6.3 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6.4 Test Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.7 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.8 Voltage and Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.9 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.10 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.10.1 CPC7592xA and CPC7592xB Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.10.2 CPC7592xC Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 CPC7592xA and CPC7592xB Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 CPC7592xC Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Under Voltage Switch Lock Out Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Hot Plug and Power Up Circuit Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Switch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Make-Before-Break Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 Break-Before-Make Operation - CPC7592xA/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5 Break-Before-Make Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 TSD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
11
11
11
12
12
12
12
13
13
14
14
15
15
15
15
15
15
16
16
16
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 16-Pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 16-Pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 16-Pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
18
18
18
18
19
19
19
20
20
20
20
2
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R03
CPC7592
1. Specifications
1.1 Package Pinout
1.3 Absolute Maximum Ratings
CPC7592
Parameter
+5 V power supply (VDD)
7
V
Battery Supply
-
-85
V
DGND to FGND Separation
-5
+5
V
-0.3
VDD + 0.3
V
Logic input to switch output
isolation
-
320
V
Switch open-contact
isolation (SW1, SW2, SW3,
SW5, SW6)
-
320
V
Switch open-contact
Isolation (SW4)
-
465
V
Operating relative humidity
5
95
%
Operating temperature
-40
+110
°C
Storage temperature
-40
+150
°C
1
16 VBAT
TBAT
2
15 RBAT
TLINE
3
14
RLINE
Logic input voltage
TRINGING
4
13
RRINGING
TTEST
5
12 RTEST
VDD
6
11 LATCH
TSD
7
10
INRINGING
DGND 8
9
INTEST
Pin
Name
1
FGND
Fault ground
2
TBAT
Tip lead to the SLIC
3
TLINE
Tip lead of the line side
4
Description
TRINGING Ringing generator return
5
TTEST
6
VDD
+5 V supply
7
TSD
Temperature shutdown pin
8
DGND
Digital ground
9
INTEST
Logic control input
10
INRINGING Logic control input
LATCH
Data latch enable control input
12
RTEST
Ring lead of the test bus
RRINGING Ringing generator source
14
RLINE
Ring lead of the line side
15
RBAT
Ring lead to the SLIC
16
VBAT
Battery supply
R03
Absolute maximum electrical ratings are at 25°C.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
Tip lead of the test bus
11
13
Unit
-0.3
FGND
1.2 Pinout
Minimum Maximum
1.4 ESD Rating
ESD Rating (Human Body Model)
1000 V
1.5 General Conditions
Unless otherwise specified, minimum and maximum
values are production testing requirements. Typical
values are characteristic of the device and are the
result of engineering evaluations. They are provided
for information purposes only and are not part of the
testing requirements.
Specifications cover the operating temperature range
TA = -40° C to +85° C. Also, unless otherwise specified
all testing is performed with VDD = 5Vdc, logic low input
voltage is 0Vdc and logic high voltage is 5Vdc.
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3
CPC7592
1.6 Switch Specifications
1.6.1 Break Switches, SW1 and SW2
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
μA
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
All-Off state.
Off-State
Leakage Current
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
0.1
ISW
-
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.3
0.1
ISW(on) = ±10 mA, ±40 mA,
RBAT and TBAT = -2 V
On Resistance
14.5
-
20.5
28
10.5
-
-
0.15
0.8
-
300
80
160
-
400
425
-
2.5
-
A
-
0.1
-
0.3
1
μA
-
0.1
-
500
-
V/μs
+25° C
RON
+85° C
-
-40° C
On Resistance
Matching
Per SW1 & SW2 On Resistance test
conditions.
ΔRON
VSW (on) = ±10 V, +25° C
DC current limit
ISW
VSW (on) = ±10 V, +85° C
VSW (on) = ±10 V, -40° C
Dynamic current limit
(t = <0.5 μs)
Break switches on, all other switches
off. Apply ±1 kV 10x1000 μs pulse with
appropriate protection in place.
ISW
+25° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±320 V
Logic input to switch
output isolation
+85° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±330 V
ISW
-40° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±310 V
dv/dt sensitivity
4
-
-
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-
Ω
Ω
mA
R03
CPC7592
1.6.2 Ringing Return Switch, SW3
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
μA
VSW3 (differential) = TLINE to TRINGING
All-Off state.
Off-State
Leakage Current
On Resistance
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
0.1
ISW
-
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
ISW(on) = ±0 mA, ±10 mA, +25° C
60
-
85
100
45
-
ISW(on) = ±0 mA, ±10 mA, +85° C
RON
-
ISW(on) = ±0 mA, ±10 mA, -40° C
VSW (on) = ± 10 V, +25° C
DC current limit
VSW (on) = ± 10 V, +85° C
ISW
VSW (on) = ± 10 V, -40° C
Dynamic current limit
(t = <0.5 μs)
Ringing switches on, all other switches
off. Apply ±1 kV 10x1000 μs pulse with
appropriate protection in place.
ISW
-
135
70
85
-
210
-
2.5
+25° C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±320 V
Logic input to switch
output isolation
+85° C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±330 V
R03
-
Ω
-
mA
-
A
1
μA
-
V/μs
0.1
ISW
-
-40° C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±310 V
dv/dt sensitivity
0.3
0.3
0.1
-
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500
5
CPC7592
1.6.3 Ringing Switch, SW4
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
μA
VSW4 (differential) = RLINE to RRINGING
All-Off state.
Off-State
Leakage Current
+25° C
VSW (differential) = -255 V to +210 V
VSW (differential) = +255 V to -210 V
+85° C
VSW (differential) = -270 V to +210 V
VSW (differential) = +270 V to -210 V
0.05
ISW
-
-40° C
VSW (differential) = -245 V to +210 V
VSW (differential) = +245 V to -210 V
0.1
0.05
On Resistance
ISW (on) = ±70 mA, ±80 mA
RON
-
10
15
Ω
On Voltage
ISW (on) = ± 1 mA
VON
-
1.5
3
V
On-State
Leakage Current
Inputs set for ringing -Measure ringing
generator current to ground.
IRINGING
-
0.1
0.25
mA
Steady-State Current*
Inputs set for ringing mode.
ISW
-
-
150
mA
Surge Current*
Ringing switches on, all other switches
off. Apply ±1 kV 10x1000 μs pulse with
appropriate protection in place.
ISW
-
-
2
A
Release Current
SW4 transition from on to off.
IRINGING
-
300
-
μA
1
μA
-
V/μs
+25° C, Logic inputs = gnd,
VSW (RRINGING, RLINE) = ±320 V
Logic input to switch
output isolation
+85° C, Logic inputs = gnd,
VSW (RRINGING, RLINE) = ±330 V
0.1
ISW
-
-40° C, Logic inputs = gnd,
VSW (RRINGING, RLINE) = ±310 V
dv/dt sensitivity
0.3
0.1
-
-
-
500
*Secondary protection and current limiting must prevent exceeding this parameter.
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CPC7592
1.6.4 Test Switches, SW5 and SW6
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
μA
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
All-Off state.
Off-State
Leakage Current
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
0.1
ISW
-
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.3
0.1
ISW(on) = ±10 mA, ±40 mA,
RBAT and TBAT = -2 V
On Resistance
+25° C
RON
+85° C
-
-40° C
VSW (on) = ±10 V, +25° C
DC current limit
VSW (on) = ±10 V, +85° C
ISW
VSW (on) = ±10 V, -40° C
Dynamic current limit
(t = <0.5 μs)
Break switches on, all other switches
off. Apply ±1 kV 10x1000 μs pulse with
appropriate protection in place.
ISW
+25° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±320 V
Logic input to switch
output isolation
+85° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±330 V
ISW
-40° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±310 V
dv/dt sensitivity
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-
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38
-
46
70
28
-
Ω
-
175
80
110
-
210
250
-
2.5
-
A
-
0.1
-
0.3
1
μA
-
0.1
-
500
-
V/μs
-
mA
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CPC7592
1.7 Digital I/O Electrical Specifications
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Input voltage, Logic low
Input voltage falling
VIL
0.8
1.1
-
Input voltage, Logic high
Input voltage rising
VIH
1.9
2.4
Unit
Input Characteristics
V
Input leakage current,
INRINGING and INTEST,
Logic high
VDD = 5.5 V, VBAT = -75 V, VHI = 2.4V
IIH
-
0.1
1
μA
Input leakage current,
INRINGING and INTEST,
Logic low
VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V
IIL
-
0.1
1
μA
Input leakage current,
LATCH Logic high
VDD = 4.5 V, VBAT = -75 V, VIH = 2.4V
IIH
10
28
-
μA
Input leakage current,
LATCH Logic low
VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V
IIL
-
46
125
μA
Input leakage current,
TSD Logic high
VDD = 5.5 V, VBAT = -75 V, VIH = 2.4
IIH
10
16
30
μA
Input leakage current,
TSD Logic low
VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V
IIL
10
16
30
μA
Output Characteristics
Output voltage,
TSD Logic high
VDD = 5.5 V, VBAT = -75 V, ITSD = 10μA
VTSD_off
2.4
VDD
-
V
Output voltage,
TSD Logic low
VDD = 5.5 V, VBAT = -75 V, ITSD = 1mA
VTSD_on
-
0
0.4
V
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
VDD
-
VDD
4.5
5.0
5.5
V
VBAT1
-
VBAT
-19
-48
-72
V
1.8 Voltage and Power Specifications
Parameter
Voltage Requirements
1
VBAT is used only for internal protection circuitry. If VBAT rises above-10 V, the device will enter the all-off state and will remain in the all-off state until the battery
drops below approximately -15 V
Power Specifications
Power consumption
VDD = 5 V, VBAT = -48 V, VIH = 2.4V,
VIL = 0.4V, Measure IDD and IBAT,
Talk and All-Off States
P
-
5.5
10
mW
All other states
P
-
6.5
10
mW
IDD
-
1.1
2.0
IDD
-
1.3
2.0
IBAT
-
0.1
10
VDD current in talk and
VDD = 5 V, VBAT = -48 V, VIH = 2.4V,
all-off states
VDD current in ringing VIL = 0.4V
state
V = 5V, VBAT = -48 V, VIH = 2.4V,
VBAT current in any state DD
VIL = 0.4V
8
mA
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μA
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CPC7592
1.9 Protection Circuitry Electrical Specifications
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
-
2.1
3.0
Unit
Protection Diode Bridge
Forward Voltage drop,
continuous current
(50/60 Hz)
Apply ± dc current limit of break
switches
VF
Forward Voltage drop,
surge current
Apply ± dynamic current limit of break
switches
VF
-
5
-
-
-
-
*
A
-
mA
-
mA
V
Protection SCR (CPC7592xA and CPC7592xC)
Surge current
SCR activates, +25° C
Trigger current:
Current into VBAT pin.
ITRIG
SCR activates, +85° C
35
(CPC7592xA)
40
(CPC7592xC)
SCR remains active, +25° C
100
(CPC7592xA)
135
(CPC7592xC)
Hold current: Current
through protection SCR
IHOLD
SCR remains active, +85° C
Gate trigger voltage
IGATE = ITRIGGER§
Reverse leakage current VBAT = -48 V
On-state voltage
-
60
(CPC7592xA)
70
(CPC7592xC)
0.5 A, t = 0.5 μs
2.0 A, t = 0.5 μs
70
60
(CPC7592xA) (CPC7592xA)
115
110
(CPC7592xC) (CPC7592xC)
VTBAT or
VRBAT
VBAT -4
-
VBAT -2
V
IVBAT
-
-
1.0
μA
VTBAT or
VRBAT
-
-
V
TTSD_on
110
125
150
°C
TTSD_off
10
-
25
°C
-3
-5
Temperature Shutdown Specifications
Shutdown activation
temperature
Shutdown circuit
hysteresis
Not production tested - limits are
guaranteed by design and Quality
Control sampling audits.
*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.
§
VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate.
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CPC7592
1.10 Truth Tables
1.10.1 CPC7592xA and CPC7592xB Truth Table
INRINGING
INTEST
Talk
0
0
Test
0
1
State
Ringing
1
0
LATCH
0
All-Off
1
1
Latched
X
X
1
All-Off
X
X
X
1
TSD
Z
1
Break
Switches
Ringing
Switches
Test
Switches
On
Off
Off
Off
Off
On
Off
On
Off
Off
Off
Off
Unchanged
0
Off
Off
Off
Ringing
Switches
Test
Switches
Z = High Impedance. Because TSD has an internal pull up at this pin, it should be controlled with an open-collector or open-drain type device.
1.10.2 CPC7592xC Truth Table
State
INRINGING
INTEST
LATCH
TSD
Break
Switches
Talk
0
0
On
Off
Off
Test/Monitor
0
1
On
Off
On
Ringing
1
0
Off
On
Off
Ringing Test
1
1
Off
On
On
0
Latched
X
X
1
All-Off
X
X
X
1
Z1
Unchanged
0
Off
Off
Off
Z = High Impedance. Because TSD has an internal pull up at this pin, it should be controlled with an open-collector or open-drain type device.
10
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CPC7592
2. Functional Description
2.1 Introduction
2.1.1 CPC7592xA and CPC7592xB Logic States
• Talk. Break switches SW1 and SW2 closed, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
• Ringing. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 open.
• Test. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and loop test
switches SW5 and SW6 closed.
• All-off. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
2.1.2 CPC7592xC Logic States
• Talk. Break switches SW1 and SW2 closed, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
• Ringing. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 open.
• Test/Monitor. Break switches SW1 and SW2
closed, ringing switches SW3 and SW4 open, and
test switches SW5 and SW6 closed.
• Ringing Test. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 closed.
• All-off. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
The CPC7592 offers break-before-make and
make-before-break switching from the ringing state to
the talk state with simple TTL level logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ring
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State control is via TTL
logic-level input so no additional driver circuitry is
required. The linear break switches SW1 and SW2
have exceptionally low RON and excellent matching
characteristics. The ringing switch, SW4, has a
minimum open contact breakdown voltage of 465 V at
+25°C sufficiently high with proper protection to
prevent breakdown in the presence of a transient fault
condition (i.e., passing the transient on to the ringing
generator).
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Integrated into the CPC7592 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection for the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
away from the SLIC via the protection diode bridge or
the optional integrated protection SCR. Power-cross
potentials are also reduced by the current limiting and
thermal shutdown circuits.
To protect the CPC7592 from an over-voltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the tip and ring terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC7592
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
The CPC7592 operates from a single +5 V supply.
This gives the device extremely low power
consumption in any state with virtually any range of
battery voltage. The battery voltage used by the
CPC7592 has a two fold function. It is used as a
reference and as a current source for the internal
integrated protection circuitry under surge conditions.
Second, it is used as a reference. In the event of
battery voltage loss, the CPC7592 enters the all-off
state.
2.2 Under Voltage Switch Lock Out Circuitry
2.2.1 Introduction
Smart logic in the CPC7592 now provides for switch
state control during both power up and power loss
transitions. An internal detector is used to evaluate the
VDD supply to determine when to de-assert the under
voltage switch lock out circuitry with a rising VDD and
when to assert the under voltage switch lock out
circuitry with a falling VDD. Any time unsatisfactory low
VDD conditions exist the lock out circuit overrides user
switch control by blocking the information at the
external input pins and conditioning internal switch
commands to the all off state. Upon restoration of VDD
the switches will remain in the all-off state until the
LATCH input is pulled low.
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CPC7592
The rising VDD lock out release threshold is internally
set to ensure all internal logic is properly biased and
functional before accepting external switch commands
from the inputs to control the switch states. For a
falling VDD event, the lock out threshold is set to
assure proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed.
Start up scenario 4 will start up with all switches in the
all-off state but upon the acceptance of a valid VDD the
LCAS will revert to one of the legitimate states listed in
the truth tables and there after may randomly change
states based on input pin leakage currents and
loading. Because the LCAS state after power up can
not be predicted with this start up condition it should
never be utilized.
To facilitate hot plug insertion and power up control the
LATCH pin has an integrated weak pull up resistor to
the VDD power rail that will hold a non-driven LATCH
pin at a logic high state. This enables board designers
to use the CPC7592 with FPGAs and other devices
that provide high impedance outputs during power up
and configuration. The weak pull up allows a fan out of
up to 32 when the system’s LATCH control driver has
a logic low minimum sink capability of 4mA.
On designs that do not wish to individually control the
LATCH pins of multi-port cards it is possible to bus
many (or all) of the LATCH pins together to create a
single board level input enable control.
2.2.2 Hot Plug and Power Up Circuit Design
Considerations
There are six possible start up scenarios that can
occur during power up. They are:
1.
2.
3.
4.
5.
6.
All inputs defined at power up & LATCH = 0
All inputs defined at power up & LATCH = 1
All inputs defined at power up & LATCH = Z
All inputs not defined at power up & LATCH = 0
All inputs not defined at power up & LATCH = 1
All inputs not defined at power up & LATCH = Z
Under all of the start up situations listed above the
CPC7592 will hold all of it’s switches in the all-off state
during power up. When VDD requirements have been
satisfied the LCAS will complete it’s start up procedure
in one of three conditions.
For start up scenario 1 the CPC7592 will transition
from the all off state to the state defined by the inputs
when VDD is valid.
For start up scenarios 2, 3, 5, and 6 the CPC7592 will
power up in the all-off state and remain there until the
LATCH pin is pulled low. This allows for an indefinite
all off state for boards inserted into a powered system
but are not configured for service or boards that need
to wait for other devices to be configured first.
2.3 Switch Logic
2.3.1 Start-up
The CPC7592 uses smart logic to monitor the VDD
supply. Any time the VDD is below an internally set
threshold, the smart logic places the control logic to
the all-off state. An internal pullup at the LATCH pin
locks the CPC7592 in the all-off state following
start-up until the LATCH pin is pulled down to a logic
low. Prior to the assertion of a logic low at the LATCH
pin, the switch control inputs must be properly
conditioned.
2.3.2 Switch Timing
The CPC7592 provides, when switching from the
ringing state to the talk state, the ability to control the
release timing of the ringing switches SW3 and SW4
relative to the state of the switches SW1 and SW2
using simple TTL logic-level inputs. The two available
techniques are referred to as make-before-break and
break-before-make operation. When the break switch
contacts of SW1 and SW2 are closed (made) before
the ringing switch contacts of SW3 and SW4 are
opened (broken), this is referred to as
make-before-break operation. Break-before-make
operation occurs when the ringing contacts of SW3
and SW4 are opened (broken) before the switch
contacts of SW1 and SW2 are closed (made). With
the CPC7592, make-before-break and
break-before-make operations can easily be
accomplished by applying the proper sequence of
logic-level inputs to the device.
The logic sequences for either mode of operation are
provided in “Make-Before-Break Ringing to Talk
Transition Logic Sequence for All Versions” on
page 13, “Break-Before-Make Ringing to Talk
Transition Logic Sequence CPC7592xA/B” on
page 13, and “Break-Before-Make Ringing to Talk
12
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CPC7592
Transition Logic Sequence for all Versions” on
page 14. Logic states and input control settings are
provided in “CPC7592xA and CPC7592xB Truth
Table” on page 10 and “CPC7592xC Truth Table” on
page 10.
2.3.3 Make-Before-Break Operation - All Versions
To use make-before-break operation, change the logic
inputs from the ringing state directly to the talk state.
Application of the talk state opens the ringing return
switch, SW3, as the break switches SW1 and SW2
close. The ringing switch, SW4, remains closed until
the next zero-crossing of the ringing current. While in
the make-before-break state, ringing potentials in
excess of the CPC7592 protection circuitry thresholds
will be diverted away from the SLIC.
Make-Before-Break Ringing to Talk Transition Logic Sequence for All Versions
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
0
-
Off
On
On
Off
SW4 waiting for next zero-current crossing to
turn off. Maximum time is one-half of the
ringing cycle. In this transition state current
limited by the dc break switch current limit
value will be sourced from the ring node of
the SLIC.
On
Off
On
Off
Zero-cross current has occurred
On
Off
Off
Off
State
INRINGING
INTEST
Ringing
1
Makebeforebreak
0
0
Talk
0
0
LATCH
0
TSD
Z
2.3.4 Break-Before-Make Operation - CPC7592xA/B
Break-before-make operation of the CPC7592xA/B
can be achieved using two different techniques.
The first method uses manipulation of the INRINGING
and INTEST logic inputs as shown in
“Break-Before-Make Ringing to Talk Transition Logic
Sequence CPC7592xA/B” on page 13.
1. At the end of the ringing state apply the all off
state (1,1). This releases the ringing return
switch (SW3) while the ringing switch (SW4)
remains on, waiting for the next zero current
event.
2. Hold the all off state for at least one-half of a
ringing cycle to assure that a zero crossing event
occurs and that SW4, the ringing switch, has
opened.
3. Apply inputs for the next desired state. For the
talk state, the inputs would be (0,0).
Break-before-make operation occurs when the ringing
switches open before the break switches SW1 and
SW2 close.
Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B
Timing
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
State
INRINGING
INTEST
Ringing
1
0
-
Off
On
On
Off
All-Off
1
1
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero current to
turn off.
Off
Off
On
Off
LATCH
0
TSD
Break
Switches
Z
BreakBeforeMake
1
1
Zero current has occurred.
SW4 has opened
Off
Off
Off
Off
Talk
0
0
Break switches close.
On
Off
Off
Off
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13
CPC7592
2.3.5 Break-Before-Make Operation - All Versions
The second break-before-make method for the
CPC7592xA/B is also the only method available for
the CPC7592xC. As shown in “CPC7592xA and
CPC7592xB Truth Table” on page 10 and
“CPC7592xC Truth Table” on page 10, the
bi-directional TSD interface disables all of the
CPC7592 switches when pulled to a logic low.
Although logically disabled, an active (closed) ringing
switch (SW4) will remain closed until the next zero
crossing current event.
As shown in the table “Break-Before-Make Ringing to
Talk Transition Logic Sequence for all Versions” on
page 14, this operation is similar to the one shown in
“Break-Before-Make Operation - All Versions” on
page 14, except in the method used to select the all off
state, and in when the INRINGING and INTEST inputs
are reconfigured for the talk state.
1. Pull TSD to a logic low to end the ringing state.
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
2. Keep TSD low for at least one-half the duration of
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break-before-make state.
3. During the TSD low period, set the INRINGING and
INTEST inputs to the talk state (0, 0).
4. Release TSD, allowing the internal pull-up to
activate the break switches.
When using TSD as an input, the two recommended
states are “0” which overrides the logic input pins and
forces an all off state and “Z” which allows normal
switch control via the logic input pins. This requires the
use of an open-collector or open-drain type buffer.
Forcing TSD to a logic high disables the thermal
shutdown circuit and is therefore not recommended as
this could lead to device damage or destruction in the
presence of excessive tip or ring potentials.
Break-Before-Make Ringing to Talk Transition Logic Sequence for all Versions
State
INRINGING
INTEST
LATCH
TSD
Ringing
1
0
0
Z
All-Off
1
0
X
BreakBeforeMake
0
0
Talk
0
0
0
0
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
-
Off
On
On
Off
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero current to
turn off.
Off
Off
On
Off
SW4 has opened
Off
Off
Off
Off
Close Break Switches
On
Off
Off
Off
Z
2.4 Data Latch
The CPC7592 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch is via the input pins INRINGING and INTEST while
the output of the data latch are internal nodes used for
state control. When the LATCH enable control pin is at
a logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch state.
14
Timing
Break
Switches
Whenever the LATCH enable control pin is at logic 1,
the data latch is active and data is locked. Subsequent
changes to the input controls INRINGING and INTEST
will not result in a change to the control logic or affect
the existing switch state.
The switches will remain in the state they were in
when the LATCH changes from logic 0 to logic 1 and
will not respond to changes in input as long as the
LATCH is at logic 1. However, neither the TSD input
nor the TSD output control functions are affected by
the latch function. Since internal thermal shutdown
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CPC7592
control and external “All-off” control is not affected by
the state of the LATCH enable input, TSD will override
state control.
2.5 TSD Pin Description
The TSD pin is a bi-directional I/O structure with an
internal pull-up current source with a nominal value of
16 μA biased from VDD. As an output, this pin
indicates the status of the thermal shutdown circuitry.
Typically, during normal operation, this pin will be
pulled up to VDD but under fault conditions that create
excess thermal loading the CPC7592 will enter
thermal shutdown and a logic low will be output.
As an input, the TSD pin is utilized to place the
CPC7592 into the “All-Off” state by simply pulling the
input low. For applications using low-voltage logic
devices (lower than VDD), Clare recommends the use
of an open-collector or an open-drain type output to
control TSD. This avoids sinking the TSD pull up bias
current to ground during normal operation when the
all-off state is not required. In general, Clare
recommends all applications use an open-collector or
open-drain type device to drive this pin.
Setting TSD to a logic 1 or tying this pin to VCC allows
switch control using the logic inputs. This setting,
however, also disables the thermal shutdown circuit
and is therefore not recommended. As a result the
TSD pin has two recommended operating states when
it is used as an input control. A logic 0, which forces
the device to the all-off state and a high impedance (Z)
state for normal operation. This requires the use of an
open-collector or open-drain type buffer.
2.6 Ringing Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ringing switch is designed to delay the change in
state until the next zero-crossing. Once on, the switch
requires a zero-current cross to turn off, and therefore
should not be used to switch a pure DC signal. The
switch will remain in the on state no matter the logic
input until the next zero crossing. These switching
characteristics will reduce and possibly eliminate
overall system impulse noise normally associated with
ringing switches. See Clare’s application note AN-144,
Impulse Noise Benefits of Line Card Access Switches for
more information. The attributes of ringing switch SW4
may make it possible to eliminate the need for a
zero-cross switching scheme. A minimum impedance
of 300 Ω in series with the ringing generator is
recommended.
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2.7 Power Supplies
Both a +5 V supply and battery voltage are connected
to the CPC7592. Switch state control is powered
exclusively by the +5 V supply. As a result, the
CPC7592 exhibits extremely low power consumption
during active and idle states.
Although battery power is not used for switch control, it
is required to supply trigger current for the integrated
internal protection circuitry SCR during fault
conditions. This integrated SCR is designed to
activate whenever the voltage at TBAT or RBAT drops 2
to 4 V below the applied voltage on the VBAT pin.
Because the battery supply at this pin is required to
source trigger current during negative overvoltage
fault conditions at tip and ring, it is important that the
net supplying this current be a low impedance path for
high speed transients such as lightning. This will
permit trigger currents to flow enabling the SCR to
activate and thereby prevent a fault induced negative
overvoltage event at the TBAT or RBAT nodes.
2.8 Battery Voltage Monitor
The CPC7592 also uses the VBAT voltage to monitor
battery voltage. If system battery voltage is lost, the
CPC7592 immediately enters the all-off state. It
remains in this state until the battery voltage is
restored. The device also enters the all-off state if the
battery voltage rises more positive than about –10 V
with respect to ground and remains in the all-off state
until the battery voltage drops below approximately
–15 V with respect to ground. This battery monitor
feature draws a small current from the battery (less
than 1 μA typical) and will add slightly to the device’s
overall power dissipation.
This monitor function performs properly if the
CPC7592 and SLIC share a common battery supply
origin. Otherwise, if battery is lost to the CPC7592 but
not to the SLIC, then the VBAT pin will be internally
biased by the potential applied at the TBAT or RBAT
pins via the internal protection circuitry SCR trigger
current path.
2.9 Protection
2.9.1 Diode Bridge/SCR
The CPC7592 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient events such as lightning. During a
positive transient condition, the fault current is
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15
CPC7592
conducted through the diode bridge to ground via
FGND. Voltage is clamped to a diode drop above
ground. During a negative transient of 2 to 4 V more
negative than the voltage source at VBAT, the SCR
conducts and faults are shunted to FGND via the SCR
or the diode bridge.
In order for the SCR to crowbar (or foldback), the
SCR’s on-voltage (see “Protection Circuitry Electrical
Specifications” on page 9) must be less than the
applied voltage at the VBAT pin. If the VBAT voltage is
less negative than the SCR on-voltage or if the VBAT
supply is unable to source the trigger current, the SCR
will not crowbar.
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to a diode
drop above ground and the fault current directed to
ground. The negative cycle of the transient will cause
the SCR to conduct when the voltage exceeds the
VBAT reference voltage by two to four volts, steering
the fault current to ground.
Note: The CPC7592xB does not contain the
protection SCR but instead uses diodes to clamp both
polarities of a transient fault. These diodes direct the
negative potential’s fault current to the VBAT pin.
2.9.2 Current Limiting function
If a lightning strike transient occurs when the device is
in the talk state, the current is passed along the line to
the integrated protection circuitry and restricted by the
dynamic current limit response of the active switches.
During the talk state, when a 1000V 10x1000 μs
lightning pulse (GR-1089-CORE) is applied to the line
though a properly clamped external protector, the
current seen at TLINE and RLINE will be a pulse with a
typical magnitude of 2.5 A and a duration less than
0.5 μs.
If a power-cross fault occurs with the device in the talk
state, the current is passed though break switches
SW1 and SW2 on to the integrated protection circuit
but is limited by the dynamic DC current limit response
of the two break switches. The DC current limit
specified over temperature is between 80 mA and
425 mA and the circuitry has a negative temperature
coefficient. As a result, if the device is subjected to
extended heating due to a power cross fault condition,
the measured current at TLINE and RLINE will decrease
as the device temperature increases. If the device
16
temperature rises sufficiently, the temperature
shutdown mechanism will activate and the device will
enter the all-off state.
2.10 Thermal Shutdown
The thermal shutdown mechanism activates when the
device die temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown events the TSD
pin will output a logic low with a nominal 0 V level. A
logic high is output from the TSD pin during normal
operation with a typical output level equal to VDD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown mechanism will activate forcing the switches
to the all-off state. At this point the current measured
into TLINE or RLINE will drop to zero. Once the device
enters thermal shutdown it will remain in the all-off
state until the temperature of the device drops below
the de-activation level of the thermal shutdown circuit.
This permits the device to autonomously return to
normal operation. If the transient has not passed,
current will again flow up to the value allowed by the
dynamic DC current limiting of the switches and
heating will resume, reactivating the thermal shutdown
mechanism. This cycle of entering and exiting the
thermal shutdown mode will continue as long as the
fault condition persists. If the magnitude of the fault
condition is great enough, the external secondary
protector will activate shunting the fault current to
ground.
2.11 External Protection Elements
The CPC7592 requires only over voltage secondary
protection on the loop side of the device. The
integrated protection feature described above negates
the need for additional external protection on the SLIC
side. The secondary protector must limit voltage
transients to levels that do not exceed the breakdown
voltage or input-output isolation barrier of the
CPC7592. A foldback or crowbar type protector is
recommended to minimize stresses on the CPC7592.
Consult Clare’s application note, AN-100, “Designing
Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces” for equations related
to the specifications of external secondary protectors,
fused resistors and PTCs.
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CPC7592
3. Manufacturing Information
3.1 Mechanical Dimensions
3.1.1 16-Pin SOIC
10.211 ± 0.254
(0.402 ± 0.010)
NOTES:
1. Coplanarity = 0.1016 (0.004) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
PIN 16
10.312 ± 0.381
(0.406 ± 0.015)
7.493 ± 0.127
(0.295 ± 0.005)
DIMENSIONS
mm
(inches)
PIN 1
1.270 TYP
(0.050 TYP)
2.337 ± 0.051
(0.092 ± 0.002)
0.649 ± 0.102
(0.026 ± 0.004)
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0.406 ± 0.076
(0.016 ± 0.003)
2.540 ± 0.152
(0.100 ± 0.006)
0.203 ± 0.102
(0.008 ± 0.004)
0.889 ± 0.178
(0.035 ± 0.007)
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0.254 MIN / 0.737 MAX X 45°
(0.010 MIN / 0.029 MAX X 45°)
0.2311 MIN / 0.3175 MAX
(0.0091 MIN / 0.0125 MAX)
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CPC7592
3.1.2 16-Pin DFN
7.00 ± 0.25
(0.276 ± 0.01)
6.00 ± 0.25
(0.236 ± 0.01)
INDEX AREA
TOP VIEW
0.90 ± 0.10
(0.035 ± 0.004)
0.02, + 0.03, - 0.02
(0.0008, + 0.0012, - 0.0008)
SEATING
PLANE
SIDE VIEW
0.20
(0.008)
0.30 ± 0.05
(0.012 ± 0.002)
1
EXPOSED
METALLIC PAD
4.25 ± 0.05
(0.167 ± 0.002)
Terminal Tip
0.80
(0.032)
16
0.55 ± 0.10
(0.022 ± 0.004)
6.00 ± 0.05
(0.236 ± 0.002)
BOTTOM VIEW
Dimensions
mm
(inch)
3.2 Printed-Circuit Board Layout
3.2.1 16-Pin SOIC
3.2.2 16-Pin DFN
1.27
(0.050)
0.35
(0.014)
1.05
(0.041)
5.80
(0.228)
9.40
(0.370)
2.00
(0.079)
0.80
(0.031)
0.60
(0.024)
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DIMENSIONS
mm
(inches)
DIMENSIONS
mm
(inches)
NOTE: As the metallic pad on the bottom of the DFN
package is connected to the substrate of the die, Clare
recommends that no printed circuit board traces or
vias be placed under this area to maintain minimum
creepage and clearance values.
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CPC7592
3.3 Tape and Reel Packaging
3.3.1 16-Pin SOIC
330.2 Dia
(13.00 Dia)
B0=10.70 + 0.15
(0.421 + 0.01)
Pin 1
Top Cover
Tape Thickness
0.102 Max
(0.004 Max)
W=16.00 + 0.30
(0.630 + 0.010)
Top Cover
Tape
K0=3.20 + 0.15
(0.193 + 0.01)
P=12.00
(0.47)
K1=2.70 + 0.15
(0.106 + 0.01)
Embossed
Carrier
A0=10.90 + 0.15
(0.429 + 0.010)
Dimensions
mm
(inches)
User Direction of Feed
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
Embossment
3.3.2 16-Pin DFN
B0=7.24 + 0.10
(0.285 + 0.004)
330.2 Dia
(13.00 Dia)
Pin 1
Top Cover
Tape Thickness
0.102 Max
(0.004 Max)
K0=1.61 + 0.10
(0.063 + 0.004)
Embossed
Carrier
P=12.00 + 0.10
(0.472 + 0.004)
A0=6.24 + 0.10
(0.246 + 0.004)
User Direction of Feed
Embossment
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W=16.00 + 0.30
(0.630 + 0.012)
Dimensions
mm
(inches)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
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19
CPC7592
3.4.2 Reflow Profile
3.4 Soldering
3.4.1 Moisture Reflow Sensitivity
Clare has characterized the moisture reflow sensitivity
for this product using IPC/JEDEC standard
J-STD-020. Moisture uptake from atmospheric
humidity occurs by diffusion. During the solder reflow
process, in which the component is attached to the
PCB, the whole body of the component is exposed to
high process temperatures. The combination of
moisture uptake and high reflow soldering
temperatures may lead to moisture induced
delamination and cracking of the component. To
prevent this, this component must be handled in
accordance with IPC/JEDEC standard J-STD-033 per
the labeled moisture sensitivity level (MSL), level 1 for
the SOIC package, and level 3 for the DFN package.
For proper assembly, this component must be
processed in accordance with the current revision of
IPC/JEDEC standard J-STD-020. Failure to follow the
recommended guidelines may cause permanent
damage to the device resulting in impaired
performance and/or a reduced lifetime expectancy.
3.5 Washing
Clare does not recommend ultrasonic cleaning of this
part.
Pb
RoHS
2002/95/EC
e3
For additional information please visit www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a
person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specifications: DS-CPC7592 - R03
© Copyright 2009, Clare, Inc.
All rights reserved. Printed in USA.
10/14/09
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