CT1820
Data Terminal Bit Processor
for MIL-STD-1553 A & B
Features
General Description
E
I NC .
C
1
ISO
S
A E RO
B
• Performs Encoder, Decoder, Logic and Control functions of a Data Bus Terminal to
MIL-STD-1553 specifications, including Address, Mode Code and Broadcast Decoding and
Terminal Fail Safe
• Flexibility - all control lines accessible
• Parallel tri-state subsystem l/O bus compatible with both 16 bit and 8 bit systems
• Dual rank l/O registers for versatile subsystem tlmlng
X LA
LE
• Operates from +5VDC @ 40mA typical (25mA CT1820)
F
• Self-contained oscillator and clock driver
• Look-ahead serial receive data output
• Self-test, on-line wraparound, plus off-line capability
9001
RTIFIED
43
43
43
LOAD
DATA 2
SECOND
RANK
XMT
REG
DO - D7
LOAD DATA 1
FIRST
RANK
XMT
REG
DO - D7
LATCH DATA 1
53
LATCH
DATA
2
56
54
6
5
4
3
2
42
41
44
50
48
47
46
45
56
(OPTIONAL)
SERIAL
INPUT
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
(MSB) D15
SECOND
RANK
REC’V
REG
DO - D7
(LSB) D0
FIRST
RANK
REC’V
REG
DO - D7
DATA SELECT 1
7
43
DATA
SELECT 2
The CT1555-3/CT1820 Bit Processor Unit (BPU) is an advanced Hybrid Microcircuit that provides the interface between a
MIL-STD-1553 Transceiver such as CT3231M or CT3232M, and the subsystem internal parallel data bus. The unit can be
employed as the mux bus interface for Remote Subsystems or Master Terminal Bus Controllers, thus providing a common
interface for all systems communicating over the bus.
The unit places no restrictions on Command, Response or polling operations as it transfers all Command, Status and Data
words from the bus to parallel output lines, together with error information, bus status and handshaking signals. It also
contains 5 Bit Address Recognition, Broadcast and Mode Code Decode, Terminal Fail Safe Signal and Self Test.
In the transmit mode, it accepts parallel data from the user and transmits Command, Status and Data words, under
subsystem control, to the data bus. Positive handshaking signals provide logic control synchronisation between the unit
and the subsystem for direct data flow.
The hybrid is completely compatible with all the electrical and functional spec requirements of MIL-STD-1553 A & B.
Vcc
1
+5V
GND
GND
11
34
FIRST
RANK
REC’V
REG
D8 - D15
{
5 BIT
ADDRESS
SECOND
RANK
XMT
REG
D8 - D15
BUILT IN
TEST
SELECT
(MSB) A4
A3
ADDRESS
DECODE
A1
(LSB) A0
BROADCAST
DATA OUT
MANCHESTER
DECODER
&
CONTROL LOGIC
10
39
DATA IN
BIT SELECT
A2
9
13
20
DATA IN
RT ENABLE
12
8
CASE
SERIAL DATA OUT
36
32
FIRST
RANK
XMT
REG
D8 - D15
SECOND
RANK
REC’V
REG
D8 - D15
MANCHESTER
ENCODER
&
CONTROL LOGIC
BROADCAST
DECODE
DATA OUT
FAIL SAFE
TIMER
&
CONTROL
FAIL SAFE
SEND DATA
ESCOUT
SYNC SEL
40
14
16
33
37
31
MODE CODE
ENC ENA
MODE
CODE
DECODE
OUTPUT INH
MRST
VALID WORD
COMM/DATA SYNC
DEC RST
TAKE DATA
+5V OSC / CLOCK POWER
OSC
&
CLOCK
DRIVER
XTAL
CLOCK OUT
21
22
19
25
26
15
27
28
24
23
35
38
30
29
18
DSC OUT
CLOCK IN
17
Figure 1 – Functional Diagram
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RX
DATA
IN
32
DATA
OUT
25
TX
DATA
OUT
26
DATA
25
33
DATA
IN
1
TX
DATA
OUT
CT1820
OR
CT1553
BIT
PROCESSOR
CT3231
T/R
HYBRID
DATA
BUS
TX
DATA
OUT
TX
DATA
IN
7
2
RX
DATA
OUT
RX
DATA
10
OUT
26
RX
DATA
IN
DATA
IN
21
DATA
IN
29
16 BIT
OR
8 BIT
SUBSYSYEM
XTAL
12
MHz
22
CONTROL
31
TX
INHIBIT
Figure 2 – Typical MIL-STD-1553 Data Terminal
Absolute Maximum Ratings
Parameter
Units
+7.0
V
Logic Input Voltage
-0.3 to +5.5
V
Logic Input Current
-20 to +4
mA
15
mA
-0.3 to VCC +0.3V
V
Storage Temperature Range
-65 to +150
°C
Operating Case Temperature Range
-55 to +125
°C
Supply Voltage
Clock Output Current (Pin 18)
Clock In (Pin 17)
Electrical Characteristics
(VCC = 5.0V ±5%)
Sym
Parameter / Conditions
Min
Typ
VIH
Logic "1" Input Voltage
2.0
-
-
V
VIL
Logic "0" Input Voltage
-
-
0.7
V
VOH
Logic "1" Output Voltage
See Pin assignments and Loading
VOL
Logic "0" Output Voltage
See Pin assignments and Loading
VIHC
Logic "1" Input Voltage (CLOCK)
VCC-0.5
-
V
VILC
Logic "0" Input Voltage (CLOCK)
-
GND+0.5
V
VOHC
Logic "1" Output Voltage (CLOCK)
VCC-0.3
-
V
VOLC
Logic "0" Output Voltage (CLOCK)
-
GND+0.3
V
lOC
Logic Supply Current
-
40
-
mA
lOSC
Oscillator / Clock Supply Current
8
13
mA
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2
Max
Units
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
PIN ASSIGNMENTS AND LOADING
In the following table, the symbols are defined as follows:
IIH= maximum input HIGH current with V IN = 2.5 volts
IIL = maximum input LOW current with VIN = 0.4 volts
IOH = maximum output HIGH current for VOUT = 2.5 volts minimum
IOL = maximum output LOW current for VOUT = 0.4 volts maximum
* Indicates use of an internal pull-up resistor
Pin
No
Name
CT1555-3
CT1820
CT1820-2
I IH
(µA)
IIL
(µA)
IOH IOL
IIH
IIL
IOH
(µA) (mA (µA) (µA) (µA)
40
-0.4
-1000 2.4
20
Description
IOL
(mA
IOL
(mA)
20
-0.4 -1000 6.0
10.0
-0.4
20
-0.4
A LOW on this input applies the contents of the SECOND
RANK REC’V REG to the D8-D15 I/O pins
-1500
-3.2
20
-0.4
Part of 5 Bit ADDRESS INPUT
-1500
-3.2
20
-0.4
1
VCC
2
D8
+5V Power Input
3
D9
4
D10
5
D11
6
D12
7
DATA SELECT 1
8
A3*
9
A2*
10
A1*
11
GROUND
12
A4*
13
A0*
14
VALID WORD
-400
2.4
-400
4.0
4.0
A LOW on this output indicates receipt of avalid word
15
FAIL SAFE
-400
2.4
-400
4.0
4.0
A HIGH on this output indicates termination of a
transmitted message that exceeds 768µs.
16
COMM / DATA SYNC
- 380
2.4
-400
4.0
4.0
A HIGH on this output indicates COMMAND (or STATUS)
word reception. A LOW indicates DATA word reception.
17
CLOCK IN
18
CLOCK OUT
19
S / T SELECT
20
CASE
21
Part of 16 Bit TRI-STATE l/O
Logic and power return
MSB of 5 Bit ADDRESS INPUT
LSB of 5 Bit ADDRESS INPUT
±30 ±0.003
+100 +100
-3
-3
-1000 1.0
Input for 12MHz clock (20pf load).
-1000 1.0
1.0
Output of OSCILLATOR AND CLOCK DRIVER.
40
-0.8
20
-0.4
DATA IN
20
-0.4
20
-0.4
A HIGH on this input represents a positive state on the
bus.
22
DATA IN
20
-0.4
20
-0.4
A HIGH on this input represents a negative state on the
bus. (Pins 21 and 22 must both be high when the bus is
inactive.)
23
ENC ENA
20
-0.4
20
-0.4
A LOW on this input initiates a transmit cycle.
24
SYNC SEL
20
-0.4
20
-0.4
Actuates COMMAND (or STATUS) sync for an input LOW
and DATA sync for an input HIGH.
25
DATA OUT
360
2.4
-400
4.0
4.0
A HIGH on this output produces a positive state on the
bus.
26
DATA OUT
360
2.4
-400
4.0
4.0
A HIGH on this output produces a negative state on the
bus.
27
SEND DATA
380
2.4
-400
4.0
4.0
A HlGH on this output indicates data shifting during the
transmit cycle.
28
ESC OUT
1000
1.2
-1000 1.2
1.2
LOW to HIGH transitions on thls output during HIGH
SEND DATA cause the transmit cycle data shifting to
occur.
29
XTAL
30
+5V OSC
POWER
31
DSC OUT
-1000 1.2
-1000 1.2
1.2
LOW to HIGH transitions on this output during LOW TAKE
DATA cause receive cycle data shifting to occur.
32
RT ENABLE
-400
-400
4.0
A HIGH on this output indicates reception of a valid
COMMAND (or STATUS) word containing the terminalís
address. It also resets the FAIL SAFE.
Aeroflex Circuit Technology
A HIGH on this input sets the unit in the self test mode.
CASE CONNECTION
A 12MHz (parallel resonant) crystal is connected between
this pin and ground.
/
CLOCK
+5V power for OSCILLATOR AND CLOCK POWER
DRIVER.
2.4
3
4.0
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
Pin
No
Name
CT1555-3
CT1820
CT1820-2
I IH
(µA)
IIL
(µA)
IOH IOL
IIH
IIL
IOH
(µA) (mA (µA) (µA) (µA)
20
-0.4
20
-0.4
20
-0.4
20
-0.4
IOL
(mA
Description
IOL
(mA)
33
DEC RST
A LOW on this input (for 1µs minimum) resets the decoder
to a condition ready for a new word, resets the COMM /
DATA SYNC output LOW, and resets the VALID WORD
output HIGH.
34
GROUND
35
OUTPUT INH
36
SERIAL DATA OUT
-400
1.6
-400
4.0
4.0
The received serial data in NRZ format is available at this
pin during LOW TAKE DATA.
37
TAKE DATA
-360
2.4
-400
4.0
4.0
A LOW on this output indicates data shifting during the
receive cycle.
38
MRST
39
BROADCAST*
-300
1.6
-400
4.0
4.0
A HIGH on this output indicates reception of a valid
COMMAND (or STATUS) word containing all ONES in the
address field.
40
MODE CODE*
-600
2.4
-600
6.0
6.0
A LOW on this output indicates reception of a valid
COMMAND (or STATUS) word containing all ONES or all
ZEROS in the sub-address field.
41
D6
20
-0.4 -1000 6.0
10.0
Part of 16 Bit TRI-STATE l/O
42
D7
43
20
-0.4
20
-0.4 -1000 6.0
Logic and Power Return.
60
-1.2
20
-0.4
A LOW on this input (for 1µs minimum) interrupts and
clears the transmit cycle, resets the FAIL SAFE, and also
performs the same functions as DEC RST.
40
-0.4
DATA SELECT 2
20
-0.4
44
D5
40
-0.4
45
D0
LSB of 16BIT TRI-STATE I/O
46
D1
Part of 16 Bit TRI-STATE l/O
47
D2
Part of 16 Bit TRI-STATE l/O
48
D3
49
LATCH DATA 2
20
-0.4
50
D4
40
-0.4
51
LOAD DATA 2
60
-1.2
A LOW on this input loads the D0-D7 data into the
SECOND RANK XMT REG. A HIGH on this input then
locks out the data inputs to permit serial shifting.
52
LATCH DATA 1
20
-0.4
A HIGH on this input allows the l/O data on D8-D15 to
appear at the output of the FIRST RANK XMT REG. A
LOW on this input holds the register outputs in their last
state.
53
LOAD DATA 1
60
-1.2
54
D13
40
-0.4
55
D14
56
D15
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-1000 2.4
A LOW on this input holds output pins 25 and 26 LOW.
-1000 2.4
A LOW on this input applies the contents of the SECOND
RANK REC’V REG to the D0-D7 I/O pins.
10.0
Part of 16 Bit TRI-STATE l/O
Part of 16 Bit TRI-STATE l/O
A HIGH on this input allows the l/O data on D0-D7 to
appear at the output of the FIRST RANK XMT REG. A
LOW on this input holds the register outputs in their last
state.
-1000 2.4
-1000 6.0
20
-1000 2.4
Part of 16 Bit TRl-STATE l/O
-0.4
A LOW on this input loads the D8-D15 data into the
SECOND RANK XMT REG. A HIGH on this input then
locks out the data inputs to permit serial shifting.
-1000 6.0
4
10.0
Part of 16 Bit TRl-STATE l/O.
OPTIONAL SERIAL INPUT.
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
TRANSMIT CYCLE OPERATION
SEND DATA remains high for 16 ESC periods,
during which the parallel transmit data is clocked to
the MANCHESTER ENCODER ③ to ④. After the
sync and Manchester coded data are transmitted
through the DATA OUT and DATA OUT outputs, the
ENCODER adds on the parity bit for that word ⑤.
ENCODER SHIFT CLOCK (ESC) (see Figure 3)
operates at the data rate (1MHz). A low at
ENCODER ENABLE (ENC ENA) during a falling
edge of ESC ① starts the Transmit cycle, which
lasts for twenty ESC clock periods. The SYNC
SELECT (SYNC SEL) input is valid at the next
low-to-high transition of ESC ②. A high at SYNC
SEL will produce a data sync, or a low will produce
a command sync for that word.
If the transmitted word is to be the last word of the
transmission, ENC ENA must go high by ⑤ to
prevent initiation of another transmit cycle.
At any time, a low applied to OUTPUT INHIBIT will
force both DATA OUT and DATA OUT to a low state
without affecting any other operations.
Parallel data must be stable at the second rank
transmit register before SEND DATA goes high ③.
Since ENC ENA is not synchronous with ESC, the
minimum time to ③ is 3µsec from ENC ENA leading
edge.
The entire transmit cycle may be interrupted and
cleared by applying a minimum of 1µsec negative
pulse to the MASTER RESET (MRST) input.
For 8-BlT I/O subsystems, D0 is tied to D8, D1 to
D9, etc., through D7 tied to D15, and data is
inputted in 8-BlT bytes by using LATCH DATA 1 and
LATCH DATA 2 and / or LOAD DATA 1 and LOAD
DATA 2 independently.
The first-rank transmit register may be operated
transparently (LATCH DATA always high), or may be
used to hold data ready for transmission,
independent of the activity on the 16-line subsystem
l/O bus. As long as LATCH DATA is held high, data
present on the subsystem l/O bus appears at the
output of the first rank transmit register. Stable data
may be latched and held at the first rank register
output by bringing LATCH DATA low. Data to be
transmitted may be latched any time before the
low-to high transition of SEND DATA (SEND DATA,
when appled to the LOAD DATA inputs, locks out
the data inputs to the second rank transmit
register.) For multiple word transmissions, the next
word may be inputted and latched any time after ③,
but before the next low to-high transition of SEND
DATA.
0
1
2
3
4
5
16
17
For serial data applications, D15 input serves as the
serial transmit input. With LOAD DATA 1 held low
and LATCH DATA 1 held high, D15 input is applied
to the ENCODERís serial data input. Inputted data
must be at the ESC rate with the MSB starting at
the low-to-high transition of SEND DATA.
If a message length ever exceeds 768µsec, the
768µsec TIME OUT (FAIL SAFE) flag goes high,
and DATA OUT and DATA OUT are both forced to a
low state. This condition will remain until a valid
command word (containing the terminalís address)
is received or until MRST goes low.
18
19
0
1
2
3
4
5
16
17
18
19
ESC
ENC ENA
SYNC SEL
DON’T CARE
VALID
VALID
DON’T CARE
DATA SELECT
LATCH DATA
DON’T CARE
DON’T CARE
DEPENDS ON "LATCH" TIMING
DON’T CARE
SEE
TEXT
DEPENDS ON "LATCH" TIMING
SEE
TEXT
OPTIONAL NEXT-WORD LATCH
OPTIONAL NEXT-WORD LATCH
SEND DATA
& LOAD DATA
DATA OUT
½ SYNC
½ SYNC
15
14
13
2
1
0
P
½ SYNC
½ SYNC
15
14
13
2
1
0
P
DATA OUT
½ SYNC
½ SYNC
15
14
13
2
1
0
P
½ SYNC
½ SYNC
15
14
13
2
1
0
P
IF USED
1
2
3
4
5
Figure 3 – Transmit Cycle Timing
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5
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
0
2
1
ENCODER
SHIFT CLOCK
TE1
ENCODER
ENABLE
TE 3
TE2
SYNC
SELECT
VALID
TE 5
TE 4
SEND DATA
& LOAD DATA
TE6
LATCH DATA
(IF USED)
TE7
TE8
PARALLEL
DATA IN
TE 9
TE10
DATA
SELECT
TE11
Symbol
Description
Min
Max
Units
TE1
ENCODER ENABLE SET-UP TIME
100
-
ns
TE2
ENCODER ENABLE PULSE WIDTH
180
-
ns
TE3
SYNC SELECT SET-UP TIME
190
-
ns
TE4
SYNC SELECT 'VALID' PULSE WIDTH
150
-
ns
TE5
SEND DATA DELAY
-
70
ns
TE6
LATCH DATA HOLD TIME
25
-
ns
TE7
LATCH DATA SET UP TIME
50
-
ns
TE8
LATCH DATA PULSE WIDTH LOW
50
-
ns
TE9
PARALLEL DATA 'VALID' WIDTH
75
-
ns
TE10
DATA SELECT DISABLE TIME
25
-
ns
TE11
DATA SELECT PULSE WIDTH HIGH
100
-
ns
Figure 4 – Encoder Timing Detail
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6
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
RECEIVE CYCLE OPERATION
bus by setting DATA SELECT lines low.
DECODER SHIFT CLOCK (DSC) (see Figure 5)
operates at the data rate (1MHz). When the
DECODER recognises a valid sync and two valid
Manchester data bits ①, a receive cycle is initiated.
The new sync is indicated at the COMMAND/DATA
SYNC (C/D SYNC) output and the TAKE DATA
output goes low ②. The C/D sync output will remain
in its valid state until a new sync is detected on a
subsequent word or until DECODER RESET (DEC
RST) or MRST goes low. A low at DEC RST or
MRST causes C/D SYNC to go low.
After all data has been loaded into the receive
registers, the data is checked for odd parity. A low
on VALID WORD (VW) output ③, indicates
successful reception of a word without any
Manchester or parity errors. For consecutive word
receptions, VW will go high again in 3 to 3.5µs. In
the absence of succeeding valid syncs, VW will
return high in 20µs. A DEC RST (low) at any time
will reset VW high.
All decoded commands, including RT ENABLE
(address recognition), BROADCAST and MODE
CODE are enabled internally by VW and remain
valid only as long as VW is low.
TAKE DATA remains low for 16 DSC periods during
which time the 16 serial data bits appear at the
SERIAL DATA OUTPUT (SDO). This data is
simultaneously loaded into the first-rank receive
register. The low-to-high transition of TAKE DATA ③
makes the new data available at the output of the
second-rank receive register. This data remains
available until the next low-to-high transitions of
TAKE DATA. It is not reset or cleared by any other
signals. This data is applied to the D0 to D15 I/O
0
1
2
3
4
5
16
17
18
19
For 8-BIT l/O subsystems (D0 tied to D8, through
D7 tied to D15), data may be extracted in 8 BIT
bytes by selectively activating DATA SELECT 1 and
DATA SEL.ECT 2.
For serial data systems, SERIAL DATA OUTPUT is
available at the DSC rate from ② to ③.
0
1
2
3
4
5
16
17
18
19
OSC
DATA IN
½ SYNC
½ SYNC
15
14
13
2
1
0
P
½ SYNC
½ SYNC
15
14
13
2
1
0
P
DATA IN
½ SYNC
½ SYNC
15
14
13
2
1
0
P
½ SYNC
½ SYNC
15
14
13
2
1
0
P
TAKE DATA
C/D SYNC
SDO
VW
VALID FOR CURRENT WORD
FROM PREVIOUS WORD
15
UNDEFINED
4
3
2
1
0
VALID FOR CURRENT WORD
UNDEFINED
15
4
3
2
1
0
FROM PREVIOUS WORD
DECODE COMMANDS
(see text)
SECOND-RANK REC’V
REGISTER CONTENT
DATA SELECT
VALID
NOT VALID
FROM PREVIOUS WORD
NEW DATA
OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15
1
NOT VALID
VALID
NEW DATA
OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15
3
2
4
Figure 5 – Receive Cycle Timing
Aeroflex Circuit Technology
7
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
4
5
19
DECODER
SHIFT CLOCK
TD1
TD 2
TAKE
DATA
TD 3
C/D SYNC
LAST STATE
NEW SYNC
TD4
VALID
WORD
LAST STATE
TD 5
BROADCAST
TD 6
RT ENABLE
TD 7
MODE
CODE
TD8
DATA
SELECT
TD 9
PARALLEL
DATA OUT
Symbol
NEW DATA
Description
Min
Max
Units
TD1
TAKE DATA RELAY ON
-
125
ns
TD2
TAKE DATA DELAY OFF
-
125
ns
TD3
SYNC DELAY
-
50
ns
TD4
VALID WORD DELAY
-
125
ns
TD5
BROADCAST DELAY
-
70
ns
TD6
RT ENABLE DELAY
-
100
ns
TD7
MODE CODE DELAY
-
100
ns
TD8
DATA SELECT INPUT DELAY
0 (Note 1)
-
ns
TD9
PARALLEL DATA OUTPUT DELAY
-
50 (Note 2)
ns
Notes: 1. DATA SELECT may be applied at any tlme that the 16 line I/O is otherwise free.
The parallel DATA OUT, however, is not ’NEWDATA’ until 50ns after TAKE DATA goes high.
2. 180ns max for CT1555-3.
Figure 6 – Decoding Timing Detail
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SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
SELF TEST FUNCTION
clock or an external clock source.
A high on the S/T SELECT input sets the hybrid in
the SELF TEST mode. In this mode, the DATA and
DATA output lines are connected to the Decoder
inputs so that the unit may operate in the
"wraparound" mode without actually going through
the data bus transceiver. Note that the DATA and
DATA output lines are active in this mode and the
S/T SELECT command must also be used to inhibit
the data bus transmitter to prevent arbitrary
transmission on the data bus.
For
internal
clock
operation,
a
12MHz
parallel-resonant fundamental-mode crystal must
be connected from XTAL to ground. Power (+5V)
must be applied to +5V OSC/CLOCK POWER and
CLOCK OUT must be connected to CLOCK IN.
For external clock operation, no power is applied to
+5V OSC/CLOCK POWER and the external clock is
applied to CLOCK IN (CLOCK OUT not connected).
The external clock must be capable of driving a 20
picofarad load to within 0.5 volts of VCC and within
0.5 volts of ground with rise and fall times of less
than 10 nanoseconds. Standard TTL levels are not
satisfactory. For a normal 1MHz data rate, the clock
frequency must be 12MHz.
TERMINAL FAIL SAFE
In order to satisfy the Terminal Fail Safe
requirements of MIL-STD-1553B, the DATA and
DATA output lines are continuously monitored for
length of message. A transmitted message in
excess of 768µs sets the FAIL SAFE output high
and terminates the transmission by setting both
DATA and DATA output lines low. As a redundant
safety factor, the FAlLSAFE output may be applied
to the lNHlBlT input of the data bus transmitter (if so
equipped). Further transmissions are prevented
until the FAIL SAFE flag is reset either by reception
of a valid command word containing the terminal
address or by a negative pulse on the MRST input.
Note: Transmissions containing gaps of 3µs or less
are considered continuous, even if the gap is
caused by a MRST pulse.
FALSE RT ENABLE
Terminals that continuously monitor their own
transmissions are subject to "END-AROUND"
operation due to a false RT ENABLE. The terminal
can erroneously interpret its own status word as a
new command word. If no measures are taken to
prevent or re-set RT ENABLE, it will remain high for
20µs or until the DECODER recognises a new valid
sync (whichever time is shorter).
RT ENABLE may be inhibited by interrupting the
RECEIVE CYCLE during a status word
transmission. Inverted SEND DATA applied to DEC
RST will prevent reception of the status word.
If continuous monitoring is required, RT ENABLE
may be reset immediately after it goes high by a 1µs
(minimum) low at DEC RST. The status word will
then be available at the second-rank receive
register.
TERMINAL ADDRESS LINES
The five-bit terminal address is set by hard wiring
the 5-BlT ADDRESS lines. The hybrid contains
internal pull-up resistors so that logic "1" lines may
be left open circuited. Logic "0" lines must be
grounded.
In operation, RT ENABLE goes high when a valid
command word containing the hard-wired address
is received. See "RECEIVE CYCLE OPERATION"
for timing.
OSCILLATOR AND CLOCK DRIVER
The hybrid may be operated with either the internal
Aeroflex Circuit Technology
9
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number
Package
2.155" x 1.14" Metal Plug In
CT1820
Plug-In Package Outline
2.155 MAX
1.900
29
48
49
28
TOP VIEW
.450 REF
1.155
.900
56
21
1
20
.100 TYP
.200 MAX
.175 MIN
.018 DIA TYP
±.002
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Telephone: (516) 694-6700
FAX:
(516) 694-6715
Toll Free Inquiries: 1-(800)THE-1553
Specifications subject to change without notice.
Aeroflex Circuit Technology
10
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700