CXA1819Q RGB Driver for LCD Description The CXA1819Q is an RGB driver designed for LCD panel LCX007. It supports a line alternative RGB drive system. In addition, three-panel projectors can be supported by using three CXA1819Q ICs. Features • Built-in RGB signal phase matching sample-andhold circuit • Effective frequency response (horizontal resolution of 600 TV lines achieved in combination with the LCX007AL) • Built-in γ control circuit • Built-in side black generation circuit for 4:3/16:9 aspect conversion • Built-in VCOM voltage output circuit Absolute Maximum Ratings • Supply voltage VCC • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD Operating Condition Supply voltage VCC1 VCC2 14 –20 to +75 –65 to +150 600 5 12.2 to 13.3 48 pin QFP (Plastic) Structure Bipolar silicon monolithic IC Applications Liquid crystal projectors Liquid crystal viewfinders Compact liquid crystal monitors V °C °C mW V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94634A77 CXA1819Q NC BF SH1 SH2 SH3 SH4 BBRT RBRT RGBBRT SIDBRT PRG FRP Block Diagram 36 35 34 33 32 31 30 29 28 27 26 25 SUB BRT CONT NC 37 24 NC NC 38 AMP BUFF 23 VCOMCONT RIN 39 22 VCOMOUT GIN 40 21 SIDCLP BIN 41 CLP S/H BRT S/H GAMMA AMP BUFF 19 BRT 42 VCC1 43 20 SIDOUT CLP S/H BRT S/H GAMMA AMP BUFF VCC2 18 VCC2 VCC1 44 17 GND2 GND1 45 16 GND2 15 ROUT 14 RCLP 13 NC GND1 46 CLP S/H BRT S/H GAMMA AMP BUFF MODE 47 GAIN CONT 1 2 3 4 5 6 7 8 9 10 11 12 NC GAMMA BGAIN RGAIN RGBGAIN SIDGAIN SIG.C BCLP BOUT GCLP GOUT NC NC 48 –2– CXA1819Q Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description VCC1 1.5k 2 GAMMA 0 to 5V∗ 2 129 Gamma control. Gamma variable range: 3.7 to 15dB Preset mode (pin 0V) ≈ 0dB 50µA GND1 3 B GAIN 1.6 to 5V∗ VCC1 1.5k B signal gain control. Gain variable range: –2.0 to +2.0dB 3 4 4 R GAIN 1.6 to 5V∗ 129 50µA GND1 R signal gain control. Gain variable range: –2.0 to +2.0dB VCC1 400 5 RGB GAIN 1.6 to 5V∗ RGB signal common gain control. Gain variable range: 5.5 to 11dB 5 129 150µA GND1 VCC1 1.5k 6 SID GAIN 1.6 to 5V∗ SID signal gray level control. 6 129 50µA GND1 Note) ∗ in the Pin voltage indicates external applied voltage. –3– CXA1819Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC2 7 SIG CENT 1.6 to 5V∗ RGB signal center voltage control. Center voltage variable range: 6.2 to 7.6V 7 129 100µA GND1 VCC2 8 B CLP 6.2 to 7.6V∗ 8 B output detection signal input. 129 5µA GND1 VCC2 9 B OUT 8V Typ. B signal output. The output is fed back to provide sufficiently low impedance (less than few Ω). 9 GND2 VCC2 10 G CLP 6.2 to 7.6V∗ 10 G output detection signal input. 129 5µA GND1 Note) ∗ in the Pin voltage indicates external applied voltage. –4– CXA1819Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC2 11 G OUT 8V Typ. G signal output. The output is fed back to provide sufficiently low impedance (less than few Ω). 11 GND2 VCC2 14 R CLP 6.2 to 7.6V∗ R output detection signal input. 14 129 5µA GND1 VCC2 15 R OUT 8V Typ. 15 R signal output. The output is fed back to provide sufficiently low impedance (less than few Ω). GND2 16 17 18 19 GND2 GND GND. Vcc2 13V 13V power supply. VCC2 20 SID OUT 8V Typ. 20 GND2 Note) ∗ in the Pin voltage indicates external applied voltage. –5– SID signal output. The output is fed back to provide sufficiently low impedance (less than few Ω). CXA1819Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC2 21 6.2 to 7.6V∗ SID CLP SID output detection signal input. 21 129 5µA GND1 VCC2 22 VCOM OUT 6.2 to 8.0V 22 VCOM voltage output. The output is fed back to provide sufficiently low impedance (less than few Ω). 50µA GND1 VCC2 23 VCOM CONT 1.6 to 5V∗ VCOM voltage control. VCOM voltage variable range: 6.2 to 8.0V 23 129 100µA GND1 VCC2 30µs 25 H 5V L 0V FRP 25 129 2.5V 100µA GND1 Note) ∗ in the Pin voltage indicates external applied voltage. –6– Flyback pulse input. This pulse is used to invert the polarity of R, G and B outputs. Input level: High ≥ 4V, Low ≤ 1V CXA1819Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC1 100µA 26 PRG 0V∗ 26 129 2.5V This pin switches black level and gray level output of the SID signal. Black level is output for 0V and gray level is output for 5V. This pin should normally be set to 0V. GND1 1.5k 27 SID BRT 1.6 to 5V∗ SID signal black level control. 27 129 50µA VCC1 28 RGB BRT 1.6 to 5V∗ 400 28 129 RGB signal common brightness control. Brightness variable range: 5 to 9.8V 150µA GND1 VCC1 29 R BRT 1.6 to 5V∗ 1.5k R signal brightness control. Brightness variable range (difference with G signal): –1.0 to +0.7V 29 30 30 B BRT 1.6 to 5V∗ 129 50µA GND1 Note) ∗ in the Pin voltage indicates external applied voltage. –7– B signal brightness control. Brightness variable range (difference with G signal): –1.0 to +0.7V CXA1819Q Pin No. 31 Symbol Pin voltage Equivalent circuit Description Resampling sample-and-hold pulse input. Input level: High ≥ 4.2V, Low ≤ 0.4V SH4 VCC1 32 33 100µA SH3 66ns 31 H 5V 32 L 0V 33 22ns SH2 129 G signal sample-and-hold pulse input. Input level: High ≥ 4.2V, Low ≤ 0.4V 200 34 GND1 34 B signal sample-and-hold pulse input. Input level: High ≥ 4.2V, Low ≤ 0.4V R signal sample-and-hold pulse input. Input level: High ≥ 4.2V, Low ≤ 0.4V SH1 VCC1 1.5k 30µs 35 H 5V L 0V BF 35 129 2.5V 1.2µs GND1 39 50µA VCC1 R IN R signal input. 2.5V (PEDESTAL LEVEL) 40 41 B IN 120µA 39 40 G IN Signal more than 1V from pedestal is sliced after input to IC. Burst flag pulse input. Used as an input clamp pulse. Input level: High ≥ 4V, Low ≤ 1V 41 G signal input. 129 1k GND1 B signal input. VCC1 1.5k 42 BRT 1.6 to 5V∗ 42 129 50µA GND1 Note) ∗ in the Pin voltage indicates external applied voltage. –8– User brightness control. Adjusts the input DC level for the gamma breakpoint. Control voltage: 1.6 to 5V CXA1819Q Pin No. 43 44 45 46 Symbol Pin voltage Vcc1 5V GND1 GND Equivalent circuit Description 5V power supply. GND. VCC1 100µA 47 MODE 5V∗ 47 129 2.5V GND1 Note) ∗ in the Pin voltage indicates external applied voltage. –9– Gain control mode selector. Normal mode for 5V and high gain mode for 0V. This pin should normally be set to 5V. CXA1819Q Electrical Characteristics (Ta = 25°C, Vcc1 = 5V, Vcc2 = 13V, see the Electrical Characteristics Measurement Circuit.) Measurement conditions No. Item Symbol Input pin Measurement point Conditions Measurement method Min. Typ. Max. Unit 1 Current Icc1 consumption 1 43 44 5V power supply current 16.6 consumption I43 + I44 22 27.4 mA 2 Current Icc2 consumption 2 18 19 13V power supply current 11.4 consumption I18 + I19 14 21.1 mA 3 Frequency response Frequency which is –3dB at 200kHz 11 MHz I/O gain 8.6 dB G I/O gain 3.5 4 5 6 R, G, B standard gains RGB gain adjust -ment range 7 8 R gain adjust -ment range 9 10 11 12 B gain adjust -ment range SID gain adjust -ment range FR 39 FG 40 FB 41 GR 39 GG 40 GB 41 Input waveform diagram 1 Output waveform diagram 1 15 Input waveform diagram 2 Output waveform diagram 2 15 9 11 9 Input waveform diagram 2 Output waveform diagram 2 RGB gain pin = 1.6V Min. GGL 40 Max. GGH Input waveform diagram 2 Output waveform diagram 2 RGB gain pin = 5.0V Min. GRL Input waveform diagram 2 Output waveform diagram 2 R gain pin = 1.6V 39 Max. GRH Input waveform diagram 2 Output waveform diagram 2 R gain pin = 5.0V Min. GBL Input waveform diagram 2 Output waveform diagram 2 B gain pin = 1.6V 41 Max. GBH Input waveform diagram 2 Output waveform diagram 2 B gain pin = 5.0V Min. GSL Input waveform diagram 4 Output waveform diagram 6 SID gain pin = 1.6V 26 Max. GSH 11 Input waveform diagram 4 Output waveform diagram 6 SID gain pin = 5.0V 5.50 dB 11 G I/O gain 11.0 12.5 R I/O gain difference with G I/O gain –3.5 –2.0 dB 15 R I/O gain difference with G I/O gain 2.0 B I/O gain difference with G I/O gain +3.5 –3.5 –2.0 dB 9 B I/O gain difference with G I/O gain 20 – 10 – 2.0 Black level and gray level difference of SID output Black level and gray level difference of SID output +3.5 0.75 0.94 V 2.1 2.4 CXA1819Q Measurement conditions No. 13 14 15 16 Item Gamma adjust -ment range RGB BRT adjust -ment range 17 18 R BRT adjust -ment range 19 20 21 22 B BRT adjust -ment range SID BRT adjust -ment range Symbol Input pin γ RL 39 Min. γ GL 40 γ BL 41 γ RH 39 Max. γ GH 40 γ BH 41 Measurement point Conditions Input waveform diagram 3 Output waveform diagram 3 GAMMA pin = 1.6V 15 I/O gain–GR 11 I/O gain–GG 9 I/O gain–GB Input waveform diagram 3 Output waveform diagram 3 GAMMA pin = 5.0V 15 I/O gain–GR 11 I/O gain–GG 9 I/O gain–GB 11 Voltage between pedestals of odd and even lines at G output Output waveform diagram 4 RGB BRT pin = 1.6V Min. BGL 40 Max. BGH Output waveform diagram 4 RGB BRT pin = 5.0V Min. BRL Output waveform diagram 4 R BRT pin = 1.6V Max. BRH Output waveform diagram 4 R BRT pin = 5.0V Min. BBL Output waveform diagram 4 B BRT pin = 1.6V 9 41 Max. BBH Output waveform diagram 4 B BRT pin = 5.0V Min. BSL Input waveform diagram 4 Output waveform diagram 7 SID BRT pin = 1.6V Max. BSH Input waveform diagram 4 Output waveform diagram 7 SID BRT pin = 5.0V Min. Typ. Max. Unit 1 Voltage difference between R output pedestals of odd and even lines to G output Voltage difference between B output pedestals of odd and even lines to G output 15 18 – 11 – 5.0 V 9.8 10.5 –2.2 –1.0 V 0.7 2.1 –2.2 –1.0 V 0.7 2.1 4.1 20 3.7 dB 3.9 15 39 26 Measurement method Voltage difference between SID output black levels 5.2 V 9.3 10.8 CXA1819Q Measurement conditions No. 23 24 Item SIG CENT adjust -ment range 25 26 VCOM adjust -ment range Symbol Input pin Measurement point Conditions Output waveform diagram 5 SIG.C pin = 5.0V Min. SL 40 Output waveform diagram 5 SIG.C pin = 1.6V Min. VL VCOM CONT pin = 1.6V V 9.0 5.6 VCOM CONT pin = 5.0V VCOM OUT DC voltage 6.2 V 8.0 8.6 When there is no description in the Conditions, the pin voltages are as follows. GAMMA (Pin 2) = 0V, RGB GAIN (Pin 5) R GAIN (Pin 4) B GAIN (Pin 3) = 2.9V, BRT (Pin 42) RGB BRT (Pin 28) R BRT (Pin 29) B BRT (Pin 30) VCOM CONT (Pin 23) SIG.C (Pin 7) = 3.4V, MODE (Pin 47) = 5V, PRG (Pin 26) = 0V – 12 – 6.2 G output center voltage 7.6 22 Max. VH Min. Typ. Max. Unit 5.2 11 Max. SH Measurement method 5V 47µ 5V (3.4V) BIN GIN RIN 0.1µ GND1 GND1 VCC1 VCC1 BRT BIN GIN RIN NC MODE 0.1µ 0.1µ 0.1µ NC NC 48 47 46 45 44 43 42 41 40 39 38 37 CLP CLP CLP 1 36 5V 5 31 29 7 GAMMA GAMMA GAMMA 8 SUB BRT CONT 30 6 BRT BRT BRT 32 (3.4V) (3.4V) (3.4V) (3.4V) (0V) (2.9V) (2.9V) (2.9V) (2.9V) (2.9V) 4 GAIN CONT S/H S/H S/H 33 3 34 2 S/H S/H S/H 35 BF GAMMA NC NC SH1 BGAIN SH4 SIDGAIN SH2 RGAIN BBRT SIG.C SH3 RGBGAIN RBRT BCLP 9 28 RGBBRT BOUT 10 AMP AMP AMP AMP 27 SIDBRT GCLP 25 FRP 11 12 BUFF BUFF BUFF BUFF 26 PRG GOUT – 13 – NC Electrical Characteristics Measurement Circuit NC 13 14 15 16 17 18 19 20 21 22 NC RCLP ROUT GND2 GND2 VCC2 VCC2 SIDOUT SIDCLP VCOMOUT buff. buff. buff. buff. VCOMCON 23 T 24 47µ 1µ 100k 1µ 100k 1µ 100k 1µ 100k V20 V22 V9 V11 V15 0.1µ 6000pF (3.4V) 13V Note 1) Always input BF signal (Pin 35) and FRP signal (Pin 25). Note 2) For Pins 2, 3, 4, 5, 6, 7, 23, 27, 28, 29, 30, and 42, apply the voltage in parentheses when there is no description in the Conditions for the Electrical Characteristics. CXA1819Q CXA1819Q Measurement Circuit I/O Waveform Diagram 5V Input waveform BF (Pin 35) 1.5µs 30µs 0V 5V 31.5µs 0.5µs Input waveform FRP (Pin 25) 0V Input level 500mVp-p Input waveform disgram 1 3.5µs 3.5µs APL500mV Input level 500mV Input waveform diagram 2 100mV Input level 100mV 50mV Input waveform diagram 3 5V 0.5µs Input waveform diagram 4 2.5µs 0V Measurement level Output waveform diagram 1 Output waveform diagram 2 Output waveform diagram 3 Output waveform diagram 4 Measurement level Measurement level Measurement level (Voltage between pedestals) a Output waveform diagram 5 a Measurement level GND Output waveform diagram 6 Output waveform diagram 7 Measurement level Measurement level – 14 – 0.01µ 47µ VR NC MODE GND1 GND1 VCC1 VCC1 BRT BIN GIN RIN 48 47 46 45 44 43 42 41 40 39 38 37 VR Represented as this. 0.1µ 0.1µ 0.1µ 0.1µ NC NC CLP CLP CLP 1 36 VR VR VR 4 GAIN CONT S/H S/H S/H 33 3 34 2 S/H S/H S/H 35 CXD2412Q Timing Generator 31 29 GAMMA GAMMA GAMMA VR 7 VR VR 8 SUB BRT CONT 30 6 BRT BRT BRT VR 5 32 VR VR 9 28 VR 10 AMP AMP AMP AMP 27 25 11 12 BUFF BUFF BUFF BUFF 26 FRP buff. buff. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 22k 50k 5V 5V 5V ANALOG RGB IN BIN GIN RIN BF GAMMA NC NC SH1 BGAIN SH4 SIDGAIN SH2 RGAIN BBRT SIG.C SH3 RGBGAIN RBRT BCLP RGBBRT BOUT SIDBRT GCLP PRG GOUT – 15 – NC Application Circuit NC NC 1µ 1µ 47µ 1µ 0.1µ 13V 390k 1µ 390k VR 3.3k buff. buff. 390k RCLP ROUT GND2 GND2 VCC2 VCC2 SIDOUT SIDCLP VCOMOUT 390k 13 14 15 16 17 18 19 20 21 22 VCOMCON 23 T 24 3.3k 13V buff. LCX007 LCD Panel Represented as this. CXA1819Q CXA1819Q Description of Operation • Gamma Control Output This pin controls the gain of the low brightness range as shown in the figure at right. The breakpoints are constant and only the gain is changed. Gamma is OFF when the GAMMA pin (Pin 2) is 0V. GAMMA = 0V Input Breakpoint • BRT Control This pin controls the pedestal of the input signal to the gamma circuit. BRT can be controlled without changing the γ characteristics to the panel because the input bias is changed with the breakpoint for output kept constant. In the figure at right, when the input signal pedestal is moved to the left of 0, the signal at that point is sliced. The input signal pedestal can be varied by ±500mV (R, G, and B IN input conversion). Output Output signal Input – • Side Black Output (SID OUT) + Input signal The CXA1819Q outputs a side black signal for 4:3/16:9 aspect conversion. The black level is controlled by the SID BRT pin (Pin 27). • Output CLP The average value of each RGB output signal and SID output signal is detected with external RC and input to the RGB CLP and SID CLP pins. Then the center voltage offsets among R, G and B outputs are reduced by feedback which equalizes the averages of G and R, B and SID outputs thus eliminating the need to adjust the center voltages among R, G and B. ROUT 390k RCLP 1µF GCLP GOUT 390k 1µF – 16 – CXA1819Q Notes on Operation Take the following precautions when using the CXA1819Q. 1. R, G, B IN input signal impedance An external capacitor is used as a hold capacitor for the clamp at the input of this IC. Therefore, the input signal impedance must be sufficiently low (70Ω or less). Note that if the impedance is too high, the characteristics may change or oscillation may tend to occur. 0.1µ 0.1µ 0.1µ R IN G IN B IN 25 CLP 26 CLP 27 CLP 2. R, G, B SID OUT load capacitance RGB OUT and SID OUT will tend to oscillate if a load capacitance of greater than 50pF is attached. Therefore, when a LCD panel with an input capacitance of greater than 50pF is connected to the output, a buffer should be used as shown in the figure at right. In addition, when not using a buffer, design to keep this load capacitance from exceeding 50pF. R, G, B, SID OUT Buffer 390k R, G, B, SID CLP 1µF 3. External capacitor at the output The absolute value and tolerance of leak current for the average value detecting external capacitor in the figure at right should be small. Note that if there is an offset in the leak current between R, G, B and SID, offset voltage is also generated between R, G, B and SID, of the external resistor which causes a DC offset of the output signal. ROUT 390k RCLP 1µF GCLP GOUT 390k 1µF – 17 – Load capacitance CXA1819Q Characteristics Graphs (Vcc = 5V, 13V, Ta = 25°C) RGB GAIN R GAIN 4 14 3 12 2 R gain to Gch gain [dB] Gch gain [dB] See Electrical Characteristics 5 and 6 for measurement 10 conditions. 8 6 4 See Electrical Characteristics 1 7 and 8 for measurement conditions. 0 –1 –2 –3 2 0 0 –4 0.5 1 1.5 2 2.5 3 3.5 4 4.5 –5 5 0 0.5 1 1.5 B GAIN 20 3 18 16 Low luminance gain [dB] B gain to Gch gain [dB] 1 See Electrical Characteristics 9 and 10 for measurement conditions. 0 –1 –2 2 2.5 3 3.5 4 4.5 0 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 4 4.5 5 Pin 2 voltage [V] RGB BRT R BRT 3 R BRT difference with Gch BRT [V] 12 10 See Electrical Characteristics 15 and 16 for measurement 8 conditions. Gch BRT [V] 5 6 Pin 3 voltage [V] 6 4 2 0 0 4.5 8 2 1.5 4 10 –4 1 3.5 12 4 0.5 3 See Electrical Characteristics 13 and 14 for measurement conditions. 14 –3 –5 0 2.5 GAMMA 4 2 2 Pin 4 voltage [V] Pin 5 voltage [V] 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2 See Electrical Characteristics 1 17 and 18 for measurement conditions. 0 –1 –2 –3 5 Pin 28 voltage [V] 0 0.5 1 1.5 2 2.5 3 3.5 Pin 29 voltage [V] – 18 – CXA1819Q B BRT VCOM 9 8.5 2 VCOM OUT voltage [V] B BRT difference with Gch BRT [V] 3 See Electrical Characteristics 19 and 20 for measurement conditions. 1 0 –1 8 See Electrical Characteristics 25 and 26 for measurement conditions. 7.5 7 6.5 6 –2 5.5 –3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5 0 0.5 1 Pin 30 voltage [V] 1.5 2 2.5 3 3.5 4 4.5 5 4 4.5 5 Pin 23 voltage [V] SIG.C SID BRT 9 12 8.5 10 7.5 SID output BRT [V] Signal center voltage [V] 8 7 6.5 6 See Electrical Characteristics 23 and 24 for measurement conditions. 5.5 5 See Electrical Characteristics 21 and 22 for measurement conditions. 8 6 4 2 4.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 Pin 7 voltage [V] BRT Input conversion offset voltage [mW] 600 400 200 See BRT control in Description of Operation –200 –400 –600 0 0.5 1 1.5 2 2.5 3 3.5 0.5 1 1.5 2 2.5 3 3.5 Pin 27 voltage [V] 800 0 0 4 4.5 5 Pin 42 voltage [V] – 19 – CXA1819Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 0.15 36 25 24 13.5 37 48 + 0.2 0.1 – 0.1 13 12 0.8 + 0.15 0.3 – 0.1 0.24 M 0.9 ± 0.2 1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE SONY CODE QFP-48P-L04 EIAJ CODE QFP048-P-1212 JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER / PALLADIUM PLATING LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 20 –