CXA1779P Predriver for High Resolution Computer Displays For the availability of this product, please contact the sales office. Description The CXA1779P is a bipolar IC developed for high resolution computer displays. 28 pin DIP (Plastic) Features • Wide bandwidth (150MHz/–3dB typ.) • RGB single package • Permits RGB common and independent contrast control • Permits RGB independent pedestal level control • Input D-range: 0.7Vp-p (min.) Absolute Maximum Ratings • Supply voltage Vcc 14 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 2.8 W Applications High resolution computer displays Structure Bipolar silicon monolithic IC Recommended Operating Conditions Supply voltage Vcc 12 ± 0.6 Block Diagram and Pin Configuration (Top View) Vcc 1 PEDESTAL CLAMP 1.7V R IN CLP 2 SYNC SLICE GAIN +15dB BLANK INC ADD BLK R DRV R GND 3 4 R CONTRAST CONTROL 1.7V G IN 5 CLP SYNC SLICE GAIN +15dB 6 G CONTRAST CONTROL 7 B IN 8 CLP 9 10 B CONTRAST CONTROL RD GND 24 G OUT 23 G S/H 22 G BRT 21 GO GND 20 B OUT 19 B S/H 18 B BRT 17 BO GND 16 BLK 15 N.C. BRIGHTNESS CONTROL CLP PIX REG 25 OUTPUTBUFFER GAIN +15dB BLK B GND R BRT BRIGHTNESS CONTROL BLANKING ADD SYNC SLICE 26 OUTPUTBUFFER PEDESTAL CLAMP 1.7V B DRV R S/H CLP PIX G GND 27 BRIGHTNESS CONTROL BLANKING ADD BLK G DRV R OUT OUTPUTBUFFER CLP PIX PEDESTAL CLAMP 28 V 11 PIX PIX 12 RGB CONTRAST CONTROL BLK GND 13 CLP CLP 14 CLAMP PULSESHAPE BLANKING PULSESHAPE Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94510-ST CXA1779P Pin Description Pin No. Symbol 1 Vcc 2 R IN Pin voltage Equivalent circuit Description Power supply pin. 12V Vcc 200µA 5 G IN 3.0V RGB input pins. The pedestal level of the input signal is 3.0V during clamping. Connect 0.01µF in series as the clamping capacitor. 129 2 5 129 8 8 B IN 3 R DRV 200µA GND Vcc 200µA 6 G DRV 60k 9 B DRV — 3 RGB simultaneous contrast adjustment pin. The variable range of the pin voltage is from 0 to 5V. 9 12 PIX GND 4 R GND 7 G GND 10 B GND RGB contrast adjustment pins. The variable range of the pin voltages is from 0 to 5V. 129 6 12 200µA GND pins for the input amplifier block. 0V Vcc 11 REG 5V 11 20k • Internal regulator stabilizing pin. • 5V regulator output pin. • Attaches the decoupling capacitance (0.01µF). GND 13 GND 17 BO GND 21 GO GND 25 RO GND 0V GND pin. 0V GND pins for the output stage buffer amplifier block. –2– CXA1779P Pin No. Symbol Pin voltage Equivalent circuit Description Vcc 14 CLP • Clamp pulse input pin. • Turns the input clamp and the bright level adjustment circuit on and off when high. VH = 3V VL = 1.5V 14 — 129 15k GND 15 N.C. Leave this pin open. Connect to GND. — Vcc 16 BLK — • Blanking pulse input pin. • Threshold level at approximately 2.25V. VH = 3V VL = 1.5V 16 129 30k GND Vcc 18 B BRT 200µA 200µA RGB bright level adjustment pins. The variable range of the pin voltages is from 0 to 5V. 50k 22 G BRT — 18 22 26 R BRT 129 26 GND Vcc 19 B S/H 1k 23 G S/H Pins to externally attach the sample-and-hold capacitor (0.01µF). 19 23 27 27 R S/H 20 B OUT 24 G OUT 100µA 200µA GND Vcc 20 24 28 28 R OUT GND –3– RGB output pins. CXA1779P Electrical Characteristics No. Item 1 Current consumption (Ta = 25°C, Vcc = 12V, See Electrical Characteristics Measurement Circuit.) Symbol Icc Measurement contents S1 to S7: OFF Input signal: None Min. Typ. Max. Unit 50 88 120 mA –3 –1.5 — dB 13 14 — dB — 3.5 — S1 to S7: ON Input continuous 1MHz and 100MHz sine waves at 0.7Vp-p, and measure the gain difference of the output amplitudes. 2 Frequency response f100MHz Gain difference [dB] = 20log ( VV OUT 100M 1M OUT ) RGB input signal (RGB input pin) 0.7Vpp 0.35V CLP potential GND S1 to S7: OFF Input video signal 0.7Vp-p and measure output signal amplitude VOUT. Calculate the contrast gain from this VOUT. 3 Contrast control CONTMAX [dB] = 20log CONTMAX ( V0.7 ) OUT RGB input signal 0.7Vpp Measuring is possible with or without a sync signal. S1 to S7: OFF CLP pulse width: 300ns BRTmax Measure the pedestal level of the RGB output signal. 4 RGB output signal Brightness control V BRTmin Pedestal level — 1.9 — — –6 — GND Measuring is possible with or without a sync signal. S1 to S7: OFF Input video signal 0.7Vp-p and measure the variable width of output signal VOUT. 5 Sub contrast gain Gain difference [dB] = 20log DRVgain OUT DRVmin OUT DRVmax ( VV RGB output signal ) DRVmax DRVmin Measuring is possible with or without a sync signal. –4– dB CXA1779P No. 6 7 Item Input D-range Minimum clamp pulse width Symbol Measurement contents Min. Typ. Max. Unit D rang S1 to S7: OFF Measure the level which maintains the output gain when the input video signal level is varied. — 0.8 — Vp-p — 300 — ns S1 to S7: OFF Measure the clamp pulse width where the pedestal level of output signal VOUT does not fluctuate. CLPmin Video input Pulse width CLP pulse –5– CXA1779P Electrical Characteristics Measurement Circuit 9V S5 + 0.01µ 23 22 21 GO GND 20 19 18 G DRV G GND B IN B DRV 5 6 7 8 9 CLP G IN 4 GND R GND RO GND G OUT R DRV 3 PIX R S/H R IN 2 15 16 REG R OUT Vcc 1 17 N.C. 24 BLK 25 BO GND 26 B BRT 27 B OUT 28 G BRT VOUT G S/H VOUT R BRT VOUT BLK S6 0.01µ B S/H 2.5V B GND S4 0.01µ 10 11 12 13 14 S7 10µ 0.1µ 4V 12V 0.01µ 0.01µ + 0.01µ Vcc S1 VIN Vcc 1k + + + VIN 4V 10k S2 VIN Vcc 1k 10k CLP S3 1k 10k Application Circuit 5V 5V 5V 0.01µ R GND RO GND G OUT G IN G DRV G GND B IN B DRV 4 5 6 7 8 9 0.01µ 12V R in 0.7Vpp 0.01µ 5V 16 15 N.C. R BRT R DRV 3 17 CLP R S/H R IN 2 18 BLK R OUT Vcc 1 10µ 19 20 GND 21 PIX 22 REG 23 B S/H 24 B GND 25 B OUT 26 G BRT 27 G S/H 28 BO GND 0.01µ GO GND 0.01µ B BRT CATHODE DRIVER BLK in 10 11 12 13 14 0.01µ 5V 5V G in 0.7Vpp B in 0.7Vpp 0.1µ 5V CLP in Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –6– CXA1779P Description of Operation 1. Contrast control The contrast for RGB IN (Pins 2, 5 and 8) input signals is adjusted using a DC externally input to the PIX pin (Pin 12). In addition, the contrast for each RGB channel can be adjusted independently using a DC externally input to the DRV pins (Pins 3, 6 and 9). (See Graphs 1 and 2.) 2. Pedestal clamp and brightness control The pedestal clamp clamps the pedestal level when the CLP pin (Pin 14) is high. The RGB IN pin voltage at the pedestal is approximately 3.2V when the pedestal is clamped. The CLP pin threshold level is 3V for VH and 1.5V for VL. (See Fig. 2.) Using a DC externally input to the R, G and B BRT pins (Pins 26, 22 and 18), the brightness control samples and holds the pedestal with the capacitance connected to the RGB SH pins (Pins 27, 23 and 19) when the CLP pin (Pin 14) is high, thereby adjusting the pedestal level of the R, G and B channels. (See Graph 3.) 3. Blanking additional function Output is blanked when the BLK pin (Pin 16) is high. The BLK pin threshold level is 3V for VH and 1.5V for VL. See the Example of Input/Output Signals for output signal levels. The output signal is 0.3V during the blanking interval. (See Figs. 4 and 5.) –7– CXA1779P Example of Input/Output Signals 0.7Vpp (Typ.) RGB IN Pins 2, 5 and 8 Clamp DC voltage 3.2V GND = 0V Fig. 1 tCLP VH = 3V CLP pulse Pin 14 tCLP ≥ 300ns VL = 1.5V Fig. 2 RGB OUT Pins 20, 24 and 28 Adjust the contrast with the PIX and DRV pins. Adjust the pedestal level with the BRT pin. GND When a sync signal is added to the RGB input signal, after the signal is sliced into approximately 60mVp-p inside the IC, it is amplified by the gain from the PIX and DRV pins and output. Fig. 3 VH = 3V BLK Pin 16 VL = 1.5V Fig. 4 RGB OUT Pins 20, 24 and 28 (During BLK pulse input) (When the blanking function is operating) Approximately 0.3V (typ.) GND Fig. 5 –8– CXA1779P Example of Representative Characteristics Graph 1. Contrast control (RGB common) characteristics 20 Output level [dB] Input conditions for each control pin 10 Pin name 12 3 6 9 26 22 18 5 0 –10 –20 0 1 2 3 4 PIX R DRV G DRV B DRV R BRT G BRT B BRT G IN Pin voltage 0 to 5 [V] 4 [V] 4 [V] 4 [V] 2.5 [V] 2.5 [V] 2.5 [V] 0.65 [Vpp] 5 PIX [V] Graph 2. DRV control (RGB independent) characteristics (Gch) 2 Input conditions for each control pin Output level [dB] 0 Pin name 12 3 6 9 26 22 18 5 –2 PIX –4 –6 0 1 2 3 4 PIX R DRV G DRV B DRV R BRT G BRT B BRT G IN Pin voltage 4 [V] 4 [V] 0 to 5 [V] 4 [V] 2.5 [V] 2.5 [V] 2.5 [V] 0.65 [Vpp] 5 G DRV [V] Graph 3. BRT control characteristics 4 Pedestal level [V] Input conditions for each control pin 3 Pin name 12 3 6 9 26 22 18 5 2 1 0 1 2 3 4 5 G BRT [V] –9– PIX R DRV G DRV B DRV R BRT G BRT B BRT G IN Pin voltage 2.5 [V] 2.5 [V] 2.5 [V] 2.5 [V] 2.5 [V] 0 to 5 [V] 2.5 [V] 0.65 [Vpp] CXA1779P Package Outline Unit: mm + 0.1 0.05 0.25 – 28PIN DIP (PLASTIC) + 0.4 37.8 – 0.1 1 + 0.3 13.0 – 0.1 15 15.24 28 0° to 15° 14 0.5 ± 0.1 1.2 ± 0.15 Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface. + 0.4 4.6 – 0.1 3.0 MIN 0.5 MIN 2.54 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-28P-03 LEAD TREATMENT SOLDER PLATING EIAJ CODE DIP028-P-0600 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 4.2g JEDEC CODE – 10 –