CXD2064Q Digital Comb Filter (NTSC/PAL) Description The CXD2064Q is an adaptive intra-field comb filter compatible with NTSC and PAL systems, and can provide high-precision Y/C separation with a single chip. Features • Adaptive intra-field Y/C separation • M-PAL and N-PAL supported • Vertical enhancer • Horizontal aperture correction • 8-bit A/D converter (1-channel) • 8-bit D/A converter (2-channel) • 4× PLL • Sync tip clamp • Four 1H delay lines 48 pin QFP (Plastic) Absolute Maximum Ratings (Ta = 25°C, VSS = 0V) • Supply voltage DVDD VSS – 0.5 to +7.0 V DAVD VSS – 0.5 to +7.0 V ADVD VSS – 0.5 to +7.0 V PLVD VSS – 0.5 to +7.0 V CLVD VSS – 0.5 to +7.0 V • Input voltage VI • Output voltage VO • Storage temperature Tstg Applications Y/C separation for color TVs and VCRs Structure Silicon gate CMOS ICStructure VSS – 0.5 to VDD + 0.5 VSS – 0.5 to VDD + 0.5 V V –55 to +150 °C Recommended Operating Conditions • Supply voltage DVDD 5.0 ± 0.25 DAVD 5.0 ± 0.25 ADVD 5.0 ± 0.25 PLVD 5.0 ± 0.25 CLVD 5.0 ± 0.25 • Analog input ADIN 1.75 • Operating temperature Topr –20 to +70 V V V V V Vp-p °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96X19B91-PS CXD2064Q DVSS TEST DVDD TEST TEST TRAP APCN DVSS TEST DVDD NTPL1 NTPL2 Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 FIN 37 24 DTR CKSL 38 23 PNR PLSL 39 22 VEH1 MCKO 40 21 VEH2 ADCK 41 20 VEH3 DVDD CLVD 46 15 TEST CLPEN 47 14 VB CLVS 48 13 IRF 2 3 4 5 6 7 8 9 AYO 1 10 11 12 VRF 16 VG PLVD 45 DAVS MOD2 DAVD 17 ACO VCV 44 RT DVSS ADVD 18 ADVS PLVS 43 RB MOD1 ADIN 19 CLPO CPO 42 Block Diagram Vertical enhancement circuit ADIN 2 NTSC: 1H PAL : 2H A/D NTSC: 1H PAL : 2H DL CLPO 1 D/A 9 AYO D/A 7 ACO Clamp Adaptive filter operation Logical operation 4fsc Phase comparator VCO SW 1/4 SW 1/2 42 44 39 CPO VCV PLSL –2– 37 38 FIN CKSL CXD2064Q Pin Description Pin No. Symbol I/O Description 1 CLPO O Internal clamp circuit current output. Connect to ADIN when using the internal clamp. Leave this pin open when not in use. 2 ADIN I Comb filter analog input (A/D converter input). 3 RB O Reference bottom voltage for the A/D converter (0.52V typ.). 4 ADVS — A/D converter analog ground. 5 ADVD — A/D converter analog power supply. (5.0V) 6 RT O Reference top voltage for the A/D converter (2.60V typ.). 7 ACO O Analog chroma signal output. Output can be obtained by connecting a resistor between this pin and the analog ground. 8 DAVD — D/A converter analog power supply. (5.0V) 9 AYO O Analog luminance signal output. Output can be obtained by connecting a resistor between this pin and the analog ground. 10 DAVS — D/A converter analog ground. 11 VG O D/A converter related pin. Connect a capacitor of approximately 0.1µF between this pin and the analog power supply (DAVD). 12 VRF I Sets the full-scale value of the Y and C-channel D/A converter output signal. 13 IRF O Connect a resistor of “16R” (16 times the output resistor “R” of the D/A converter). 14 VB O D/A converter related pin. Connect to the analog ground (DAVS) via a capacitor of approximately 0.1µF. 15 TEST I Test pin. Normally fix to “Low”. 16 DVDD — Digital power supply. (5.0V) 18 DVSS — Digital ground. 17 MOD2 I 19 MOD1 I 20 VEH3 I 21 VEH2 I 22 VEH1 I 23 PNR I L: NTSC/H: PAL, M-PAL, N-PAL 24 DTR I Normally fix to “Low”. 25 NTPL2 I 26 NTPL1 I 27 DVDD — Y/C separation mode setting. MOD2 L H H MOD1 L L H Adaptive processing mode BPF separation mode Through mode Vertical enhancement setting. Can be set in 8 stages from VEH3 VEH2 VEH1: LLL (off) to HHH (max.) NTSC/PAL/M-PAL/N-PAL mode setting. Digital power supply. (5.0V) –3– NTPL2 L L H H NTPL1 L H L H NTSC PAL M-PAL N-PAL CXD2064Q Pin No. Symbol I/O Description 28 TEST I 29 DVSS — 30 APCN I Horizontal aperture correction circuit setting. Low: Off, High: On. 31 TRAP I Trap filter setting. Low: Off, High: On. 32 TEST I Test pin. Normally open or fix to “Low”. 33 TEST I Test pin. Normally open or fix to “Low”. 34 DVDD — 35 TEST I 36 DVSS — 37 FIN Test pin. Normally fix to “Low”. Digital ground. Digital power supply. (5.0V) Test pin. Normally open or fix to “Low”. Digital ground. I Clock input. Input the burst-locked fsc (2fsc) when using the internal PLL. Input the burst-locked 4fsc when not using the internal PLL. 38 CKSL I PLL control. Low: The internal PLL is not used. The clock (4fsc) which is input to FIN is supplied internally. High: The internal PLL is used. VCO oscillation output 4fsc clock is supplied internally. 39 PLSL I Selects the clock input to FIN. Low: fsc, High: 2fsc. When inputting 4fsc to FIN (when not using the internal PLL), this pin may be set to either “Low” or “High”. 40 MCKO O Clock (4fsc) output. 41 ADCK I Clock input for A/D converter. Normally connect to MCKO. 42 CPO O PLL phase comparator output. Leave open when not using the PLL. 43 PLVS — PLL analog ground. 44 VCV I 45 PLVD — PLL analog power supply. (5.0V) 46 CLVD — Clamp D/A converter analog power supply. (5.0V) 47 CLPEN 48 CLVS I — VCO control voltage input. Connect to PLVS when not using the PLL. Clamp circuit enable pin. Low: Clamp on, High: Clamp off. Clamp D/A converter analog ground. –4– CXD2064Q Electrical Characteristics DC Characteristics Item (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +70°C) Symbol Measurement conditions Min. Typ. Max. Unit Applicable pins — 4.75 5.0 5.25 V ∗1 — –20 +70 °C — mA — VDD V ∗2 V ∗3 ns ∗1 DVDD DAVD Supply voltage ADVD PLVD CLVD Operating temperature Topr Supply current IDD Input/output voltage VI, VO Input voltage tr, tf VOH — 90 Vss — 0.7VDD VIH VIL Input rise/fall time Clock 18MHz CMOS level input 0.3VDD 500 0 — IOH = –2mA ∗4 VDD – 0.8 IOH = –3mA Output voltage VOL V IOL = 4mA 0.4 Vp-p VIN fmax = 50MHz sine wave Feedback resistance value RFB VIN = Vss or VDD 250k IIL, IIH VIN = Vss or VDD –10 IIH VIH = VDD 40 100 240 3.0 9.0 18.0 Input leak current Clock amplifier output delay ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 ∗9 — — All pins All pins other than ∗6 All input pins other than ∗6 All output pins other than ∗5 CPO (Pin 42) FIN (Pin 37) All input pins other than ∗8 Pins 32, 33 and 35 MCKO (Pin 40) –5– 0.5 1M 2.5M 10 ∗4 ∗5 IOL = 1.5mA Clock input amplitude ∗5 Ω µA ns ∗6 ∗7 ∗8 ∗9 CXD2064Q I/O Pin Capacitance (Ta = 25°C, f = 1MHz, VIN = VOUT = 0V) Item Symbol Min. Min. Max. Input pin capacitance CIN — — 9 Output pin capacitance COUT — — 11 Unit pF Internal 8-bit A/D Converter Characteristics (VDD = 5V, Ta = 25°C, f = 10MHz) Item Symbol Conditions Min. Typ. Max. Unit Resolution n — 8 — bit Max. conversion speed fmax 18 — — MSPS Analog input bandwidth BW — 18 — MHz VRB 0.48 0.52 0.56 V VRT – VRB 1.96 2.08 2.22 V Self bias –3dB Output data delay tpd — — 45 ns Differential linearity error ED –1.0 — +1.0 LSB Integral linearity error EL –2.0 — +2.0 LSB Internal 8-bit D/A Converter Characteristics (VDD = 5V, VRF = 2V, RIRF = 3.3kΩ, R = 200Ω, Ta = 25°C, f = 10MHz) Symbol Item Conditions Min. Typ. Max. Unit Resolution n — 8 — bit Max. conversion speed fmax 18 — — MSPS Differential linearity error ED –0.8 — +0.8 LSB Integral linearity error EL –2.0 — +2.0 LSB Output full-scale voltage VFS 1.805 1.90 1.995 V Output full-scale current IFS — 9.5 15 mA Output offset voltage VOS — — 1.0 mV Glitch energy GE — 30 — pV-s R = 75Ω, 1Vp-p output Internal Clamp (VDD = 5V, Ta = 25°C, f = 10MHz) Item Clamp level ∗1 Symbol Conditions CLV ∗1 Sync tip clamp –6– Min. Typ. Max. Unit — 0.67 — V CXD2064Q Description of Functions • Y/C separation mode The Y/C separation mode can be switched by the following pin settings. Mode name MOD2 (Pin 17) MOD1 (Pin 19) Adaptive processing mode L L BPF separation mode H L Through mode H H Adaptive processing mode: Y/C separation is performed by detecting the correlation between three lines and switching between comb filter and BPF processing. BPF separation mode: Y/C separation is performed only by BPF processing. Through mode: The composite video signal input from ADIN (Pin 2) is A/D converted and then D/A converted without modification. D/A outputs are AYO (Pin 9) and ACO (Pin 7). • Horizontal aperture correction circuit This circuit corrects the frequency response degradation caused by the aperture effects accompanying D/A conversion. This circuit is valid in the adaptive processing and BPF separation modes noted above. • Trap filter circuit A trap filter is applied to remove the frequency components near fsc in the luminance signal after Y/C separation. This reduces the fsc frequency component gain by approximately 2.5dB. This circuit is valid in the adaptive processing and BPF separation modes noted above. • Using the internal PLL (clock selection method) PLL used PLL not used FIN (Pin 37) CKSL (Pin 38) PLSL (Pin 39) fsc input H L 2fsc input H H 4fsc input L L/H –7– CXD2064Q • Vertical enhancement circuit This circuit generates an enhanced component in accordance with the vertical aperture component (luminance difference from the preceding and following lines) of the luminance signal. The vertical aperture of the picture can be enhanced naturally by adding this enhanced component to the luminance signal after Y/C separation. The enhancement level can be set in eight steps. The size of | a | in the figure below varies according to the pin settings. Accordingly,enhanced level can be changed for portions of natural pictures with small luminance differences where the effects are particularly easy to see. Portions with large luminance differences are cut with a limiter so that they are not excessively enhanced. Also, portions with extremely large luminance differences such as white and black lines are not enhanced because they need be enhanced any more. Enhancement level Limiter 0 –a Enhancement level Luminance difference a Limiter Pin settings VEH3 (Pin 20) VEH2 (Pin 21) VEH1 (Pin 22) |a| OFF L L L — 1 L L H Large 2 L H L ↑ 3 L H H 4 H L L 5 H L H 6 H H L ↓ Max H H H Small –8– CXD2064Q Application Circuit for D/A Converter Block 8 10µ DAVD Y output AYO 9 0.1µ 3k 10 DAVS 200 (R) VRF 12 2k 0.1µ IRF 13 3.3k (R’) C output ACO 7 200 (R) VG 11 0.1µ : Analog power Supply (5V) VB 14 0.1µ : Analog ground • Method of selecting the output resistor The CXD2064Q has a built-in current output type D/A converter. To obtain the output voltages, connect resistors to the AYO and ACO pins. The specs are as follows: output full-scale voltage VFS = 0.5 to 2.0 [V], output full-scale current IFS = 0 to 15 [mA]. Calculate the output resistance value using the relationship VFS = IFS × R. In addition, connect a resistor of 16 times the output resistor to the reference current pin (IRF). In case this results in a unpractical value, use a resistance value as close to the calculated value as possible. Note that, at this time, VFS = VRF × 16R/R’ (VRF: Pin voltage of VRF). Here, R is the resistor connected to AYO/ACO, and R’ is the resistor connected to IRF. Power consumption can be reduced by using higher resistance values, but the glitch energy and data settling time increase contrastingly. Set the optimum values according to the system applications. • VDD, VSS Separate the analog and digital systems around the device to reduce the effects of noise. DAVD is bypassed to DAVS as close to each other as possible through a ceramic capacitor of approximately 0.1µF. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –9– CXD2064Q External Connection Diagram H L H L H L H L 31 30 29 28 27 26 25 TRAP APCN DVSS TEST DVDD NTPL1 NTPL2 DVDD 33 TEST 34 Clock Input 32 TEST 36 TEST 0.1µ DVSS 0.1µ 35 37 FIN H L H L 560 H L H L H L H L H L H L DTR 24 0.001µ 38 CKSL PNR 23 39 PLSL VEH1 22 40 MCKO VEH2 21 41 ADCK VEH3 20 42 CPO MOD1 19 43 PLVS DVSS 18 56k 0.022µ 44 VCV MOD2 17 45 PLVD DVDD 16 46 CLVD TEST 15 0.1µ H L 0.1µ 0.1µ ADVD RT ACO DAVD AYO DAVS VG VRF IRF 13 ADVS 48 CLVS RB VB 14 ADIN 47 CLPEN CLPO H L 1 2 3 4 5 6 7 8 9 10 11 12 0.1µ 0.1µ Composite Video Input 0.1µ 0.1µ 0.1µ 3k 2k H : CMOS High level : Analog ground L : CMOS Low level 200 C output 3.3k 0.1µ 10µ : Analog power Supply (5V) 0.1µ 0.1µ 200 Y output : Digital power Supply (5V) : Digital ground Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXD2064Q Notes on Operation • Make the wiring for the signal input to ADIN (Pin 2) as short as possible. Also, drive the input signal to ADIN at low impedance. • Make the analog and digital power supply and GND lines as wide and short as possible to ensure low impedance. • Bypass the analog and digital power supply pins to GND with a ceramic capacitor of about 0.1µF connected as close to the pin as possible. • Input a clock that is locked to the burst signal of the input video signal. • Separate the wiring to the clock input pin FIN (Pin 37) from the external analog circuits, analog power supplies and analog GND. • ADIN (analog input signal) Set the input signal peak-to-peak value VPP to 1.75V or less. Additionally, VPP is recommended to be 1.3V or more since the A/D converter input dynamic range should be made as large as possible. C → B → 2.60V (Reference top voltage typical value for internal A/D converter) VPP 0.67V (Sync tip clamp level) A → 0.52V (Reference bottom voltage typical value for internal A/D converter) The DC level at the ADIN pin is as shown in the diagram above when the internal sync tip clamp is used. Labeling the internal D/A converter AYO output full-scale voltage as VFS, the correspondence between the ADIN pin voltage and AYO output pin voltage (DC level) is as follows; DC voltage at point B → AYO maximum output voltage [V] DC voltage at point A → 0 [V] DC voltage at point C → VFS [V] The VFS is the AYO output voltage generated when the voltage equivalent to the point C is input. • Internal delay The delay from the internal A/D converter to the D/A converter output is as follows; NTSC: 1H + 24.5 clocks + αns PAL: 2H + 24.5 clocks + αns (α: D/A converter analog output delay = approximately 20ns) The 24.5 clocks are the sum of the clocks shown below; A/D converter: 3.5 clocks (“0.5” is for fetching the data at the fall of the clock.) Internal logic: 20 clocks D/A converter: 1 clock – 11 – CXD2064Q Application Circuit 1 • fsc is used for clock H L H L X’tal PAL : 4.43MHz NTSC : 3.58MHz 34 33 32 31 30 29 28 27 26 25 TEST DVDD TEST TEST TRAP APCN DVSS TEST DVDD NTPL1 NTPL2 0.1µ 35 DVSS 0.1µ 36 Burst-locked Clock (fsc) Clock Generator 37 FIN H L H L 560 H L H L H L H L H L H L H L H L DTR 24 0.001µ 38 CKSL PNR 23 39 PLSL VEH1 22 40 MCKO VEH2 21 41 ADCK VEH3 20 42 CPO MOD1 19 43 PLVS DVSS 18 44 VCV MOD2 17 45 PLVD DVDD 16 46 CLVD TEST 15 56k 0.022µ 0.1µ H L 0.1µ 0.1µ ADVD RT ACO DAVD AYO DAVS VG VRF IRF 13 ADVS 48 CLVS RB VB 14 ADIN 47 CLPEN CLPO H L 1 2 3 4 5 6 7 8 9 10 11 12 0.1µ 0.1µ 0.1µ Composite Video Input 3.3k 0.1µ 0.1µ 0.1µ LPF 3k 2k 10µ 0.1µ 0.1µ : Analog power Supply (5V) : Analog ground LPF Y output 200 : Digital power Supply (5V) : Digital ground H : CMOS High level L : CMOS Low level LPF C output 200 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 12 – CXD2064Q Application Circuit 2 • 2fsc is used for clock H L H L X’tal PAL : 8.86MHz NTSC : 7.16MHz 36 35 34 33 32 31 30 29 28 27 26 25 TEST DVDD TEST TEST TRAP APCN DVSS TEST DVDD NTPL1 NTPL2 0.1µ DVSS 0.1µ Burst-locked Clock (2fsc) Clock Generator 37 FIN H L H L 560 H L H L H L H L H L H L H L H L DTR 24 0.001µ 38 CKSL PNR 23 39 PLSL VEH1 22 40 MCKO VEH2 21 41 ADCK VEH3 20 42 CPO MOD1 19 43 PLVS DVSS 18 44 VCV MOD2 17 45 PLVD DVDD 16 46 CLVD TEST 15 56k 0.022µ 0.1µ H L 0.1µ 0.1µ ADVD RT ACO DAVD AYO DAVS VG VRF IRF 13 ADVS 48 CLVS RB VB 14 ADIN 47 CLPEN CLPO H L 1 2 3 4 5 6 7 8 9 10 11 12 0.1µ 0.1µ 0.1µ Composite Video Input 3.3k 0.1µ 0.1µ 0.1µ LPF 3k 2k 10µ 0.1µ 0.1µ : Analog power Supply (5V) : Analog ground LPF Y output 200 : Digital power Supply (5V) : Digital ground H : CMOS High level L : CMOS Low level LPF C output 200 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 13 – CXD2064Q Application Circuit 3 • 4fsc is used for clock X’tal PAL : 17.7MHz NTSC : 14.3MHz 36 35 34 33 32 31 30 29 28 27 26 25 TEST DVDD TEST TEST TRAP APCN DVSS TEST DVDD NTPL1 NTPL2 0.1µ DVSS 0.1µ Burst-locked Clock (4fsc) Clock Generator 37 FIN H L H L H L H L H L H L H L H L H L H L H L H L DTR 24 0.001µ 38 CKSL PNR 23 39 PLSL VEH1 22 40 MCKO VEH2 21 41 ADCK VEH3 20 42 CPO MOD1 19 43 PLVS DVSS 18 44 VCV MOD2 17 45 PLVD DVDD 16 46 CLVD TEST 15 0.1µ H L 0.1µ 0.1µ ADVD RT ACO DAVD AYO DAVS VG VRF IRF 13 ADVS 48 CLVS RB VB 14 ADIN 47 CLPEN CLPO H L 1 2 3 4 5 6 7 8 9 10 11 12 0.1µ 0.1µ 0.1µ Composite Video Input 3.3k 0.1µ 0.1µ 0.1µ LPF 3k 2k 10µ 0.1µ 0.1µ : Analog power Supply (5V) : Analog ground LPF Y output 200 : Digital power Supply (5V) : Digital ground H : CMOS High level L : CMOS Low level LPF C output 200 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 14 – CXD2064Q Package Outline Unit : mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 0.15 36 25 24 13.5 37 48 + 0.2 0.1 – 0.1 13 12 0.8 + 0.15 0.3 – 0.1 0.24 M 0.9 ± 0.2 1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-48P-L04 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE QFP048-P-1212 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.7g JEDEC CODE – 15 –