CXP402 CMOS 4-bit Single Chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP402 is a CMOS 4-bit single chip microcomputer which consists of 4-bit CPU, ROM, RAM, 8-bit timer, 8-bit timer/counter, 18-bit time-base timer, LCD controller/driver, digital signal processor circuit for CD player, 1-bit DAC and the like. Features • Instruction cycle 1.89µs for 16.93MHz oscillation • ROM capacity 6144 × 8 bits • RAM capacity 400 × 4 bits (Including stack and display area) • LCD controller/driver (Enables to direct drive) • 8-bit timer, 8-bit timer/event counter and 18-bit time-base timer are incorporated; they are independently controllable. • Arithmetic and logical operations between the entire RAM area, I/O area and the accumulator by means of the memory mapped I/O. • Entire ROM area can be referred by the table lookup instruction. Digital Signal Processor (DSP) Block • Playback mode supporting CAV (Constant Angular Velocity) • Frame jitter free • Allows relative rotational velocity readout • Supports spindle external control • Wide capture range playback mode • Spindle rotational velocity following method • 16K RAM • EFM data demodulation • Enhanced EFM frame sync signal protection • SEC strategy-based error correction • Subcode demodulation and Sub Q data error detection • Digital spindle servo • 16-bit traverse counter • Asymmetry correction circuit • Servo auto sequencer • Digital audio interface output • Digital peak meter 112 pin LQFP (Plastic) Digital Filter, DAC and Analog Low-Pass Filter Blocks • DBB (digital bass boost) function • Digital de-emphasis • Digital attenuation • Zero detection function • 8Fs oversampling digital filter • S/N: 100dB or more (master clock: 384Fs, typ.) Logical value: 109dB • THD + N: 0.007% or less (master clock: 384Fs, typ.) • Rejection band attenuation: –60dB or more • 112-pin plastic LQFP • Piggyback package (CXP401Z) available Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98924-PS PA3 69 PA2 68 PA1 67 PA0 66 SEG15 73 SEG14 74 SEG13 75 SEG12 76 SEG11 77 SEG10 78 SEG9 79 SEG8 80 Port ROM 6K Byte SCOR COM0 VLC1 70 29 RMC 62 63 64 65 58 59 60 61 T/C RAM 400 × 4bit RST PX0 PX3 SIO I/F PF0 PF1 PF2 PF3 PE0 PE1 PE2 PE3 PD0 PD1 PD2 PY3 PY2 OSC Analog Out 16K RAM ASYI ASYO BIAS RF AVDD Digital CLV 1-bit DAC Digital Filter EPROM Collector EFM Demodulator Digital PLL Test Circuit D/A I/F Asymmetry Collector 49 13 12 14 15 16 17 18 19 20 21 22 24 23 25 26 CLTV 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 37 36 35 34 33 32 SQCK SQSO ACDT RMUT LMUT DATA XLAT CLOK XRST SYSM PWMI XTSL ASYE SENS FOK GFS AVSS PY1 AVDD SPC500 CPU Core AIN2 SEG7 81 AOUT2 SEG6 82 SCOR EMPHI Servo Auto Sequencer AVSS INT PY0 SBSO 2 54 55 11 8 10 9 CNIN LOUT2 SEG5 83 CPU I/F SEIN 1 EXCK XVSS EMPH PORT I/F CLKO 5 LOCK XTAO SEG4 84 XLTO 4 MON XTAI LCD Controller/Driver DATO 3 MDS XVDD FOK GFS XRSTO 53 51 30 31 40 MDP AVSS 85 86 87 88 89 90 91 92 95 94 93 C4M LOUT1 SEG3 PB0 VPCO1 AIN1 SEG1 PB2 VPCO2 AOUT1 SEG2 PB1 V16M AVSS SEG0 PB3 VCKI AVDD COM3 PC0 VCTL BCKI COM1 PC2 PCO BCK COM2 PC1 FILI PCMDI VLC3 PC3 RMC FILO PCMD VLC2 XRST AVSS LRCKI –2– LRCK Block Diagram VDD VSS 7 6 43 VSS 44 VDD 71 VSS 72 VDD 57 CTEST 56 DTEST 27 TEST1 28 TEST0 50 DOUT 46 MNT3 47 MNT1 48 MNT0 45 XROF 42 C2PO 41 RFCK 39 XPCK 38 GTOP 52 WFCK CXP402 CXP402 SEG2 SEG3 SEG1 SEG0 COM3 COM2 COM0 COM1 VLC3 VLC2 VLC1 AVSS AOUT1 AVDD AIN1 LOUT1 AVSS XVDD XTAO XTAI XVSS AVSS LOUT2 AIN2 AVDD AOUT2 AVSS NC Pin Configuration (Top View) 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 SEIN 1 84 SEG4 CNIN 2 83 SEG5 DATO 3 82 SEG6 XLTO 4 81 SEG7 CLKO 5 80 SEG8 VSS 6 79 SEG9 VDD 7 78 SEG10 MON 8 77 SEG11 MDP 9 76 SEG12 MDS 10 75 SEG13 LOCK 11 74 SEG14 VPCO2 12 73 SEG15 VPCO1 13 72 VDD VCKI 14 71 VSS V16M 15 70 RMC VCTL 16 69 PA3 PCO 17 68 PA2 FILI 18 67 PA1 FILO 19 66 PA0 AVSS 20 65 PB3 CLTV 21 64 PB2 AVDD 22 63 PB1 RF 23 62 PB0 BIAS 24 61 PC3 ASYI 25 60 PC2 ASYO 26 59 PC1 TEST1 27 58 PC0 TEST0 28 57 CTEST –3– DTEST EXCK SBSO SCOR EMPH WFCK DOUT C4M MNT0 MNT1 MNT3 XROF VDD VSS C2PO RFCK GFS XPCK GTOP BCKI BCK PCMDI PCMD LRCKI LRCK FOK XRST XRSTO 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 CXP402 Pin Description Symbol Description I/O PA0 to PA3 I/O (Port A) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) PB0 to PB3 I/O (Port B) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) PC0 to PC3 I/O (Port C) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) SEG0 to SEG15 Output LCD segment signal output. (16 pins) COM0 to COM3 Output LCD common signal output. LCD bias power supply. Bias voltage is generated, which is 1/3 the supply voltage due to the internal resistor. (3 pins) VLC1 to VLC3 SEIN Input SENS input from SSP. CNIN Input Track jump count signal input. DATO Output Serial data output to SSP. XLTO Output Serial data latch output to SSP. CLKO Output Serial clock output to SSP. MON Output Spindle motor ON/OFF control output. MDP MDS Output (tri-state) Spindle motor servo control. (2 pins) LOCK Output Lock signal output. GFS is sampled at 460Hz and; when GFS is high, this pin outputs a high signal. If GFS is low eight convective samples, this pin outputs low. VPCO1 VPCO2 Output (tri-state) Wide-band EFM PLL charge pump output. (2 pins) VCKI Input Wide-band EFM PLL VCO2 oscillation input. V16M Output Wide-band EFM PLL VCO2 oscillation output. VCTL Input Wide-band EFM PLL VCO2 control voltage input. PCO Output (tri-state) Master PLL charge pump output. FILI Input FILO Output (Analog) Master PLL filter output. CLTV Input Master VCO control voltage input. RF Input EFM signal input. BIAS Input Asymmetry circuit constant current input. ASYI Input Asymmetry comparator voltage input. ASYO Output EFM output. (full swing) XRST Input System reset input. Active at low. Master PLL filter input. –4– CXP402 Symbol Description I/O XRSTO Output Reset signal output. Active at low. FOK Input Focus OK input. Used for SENS output and servo auto sequencer. LRCK Output D/A interface LR clock output. (f = Fs) LRCKI Input LR clock input. PCMD Output D/A interface serial data output. PCMDI Input D/A interface serial data input. BCK Output D/A interface bit clock output. BCKI Input D/A interface bit clock input. GTOP Output GTOP output. XPCK Output XPLCK output. GFS Output GFS output. RFCK Output RFCK output. C2PO Output C2PO output. XROF Output XRAOF output. MNT3 Output MNT3 output. MNT1 Output MNT1 output. MNT0 Output MNT0 output. C4M Output 1/4 frequency division output of the oscillation input. (4.2336MHz for 16.3944MHz) DOUT Output Digital Out output. EMPH Output De-emphasis ON/OFF output. High is output for ON; low is output for OFF. WFCK Output WFCK output. SCOR Output Subcode sync detection output. Outputs a high signal when either subcode sync S0 or S1 is detected. SBSO Output Sub P to W serial data output. EXCK Input SBSO serial clock input. AOUT1 Output (Analog) Lch analog output. AIN1 Input (Analog) Lch operational amplifier input. LOUT1 Output Lch LINE output. AOUT2 Output (Analog) Rch analog output. AIN2 Input (Analog) Rch operational amplifier LOUT2 Output Rch LINE output. RMC Input Remote control receiver circuit input. XTAI Input XTAO Connect a crystal for system clock oscillation. When the clock is supplied externally, input it to the XTAI pin and leave the XTAO pin open. NC No connected. –5– CXP402 Symbol Description I/O VDD Positive power supply. VSS GND. AVDD Positive power supply for analog circuit. AVSS GND for analog circuit. XVDD Positive power supply for oscillation circuit. XVSS GND for oscillation circuit. TEST1 Input TEST0 Input DTEST Input CTEST Input Test for LSI. Connect to GND for normal operation. Notes • Power supply pins AVDD, AVss, XVDD, XVss, VDD and Vss should process all the pins. • PCMD is the MSB first, two's complement output. • GTOP is used to monitor the frame sync protection status. (High: sync protection window open.) • XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. • XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. • The GFS signal goes high when the frame sync and the insertion timing match. • RFCK is derived from the crystal accuracy, and has a cycle of 136µs (at normal speed). • C2PO represents the data error status. • XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin. –6– CXP402 Input/Output Circuit Formats for Pins Circuit format Pin When reset Port A ∗ Port B Ports A, B data PA0 to PA3 PB0 to PB3 Hi-Z Ports A, B I/O direction Input protection circuit IP Data bus RD (Ports A, B) 8 pins ∗ Pull-up transistor approx. 50kΩ Port C ∗ Port C data PC0 to PC3 Hi-Z Port C I/O direction IP Data bus 4 pins RMC XRST SEIN CNIN VCKI FOK LRCKI PCMDI BCKI EXCK RD (Port C) ∗ Pull-up transistor approx. 50kΩ Schmitt input Internal circuit IP ∗ EMPHI is not Schmitt input. 10 pins –7– Hi-Z CXP402 Circuit format Pin When reset VCH SEG0 to SEG15 VDD level VCL 16 pins VDD COM0 COM1 COM2 COM3 VLC1 VDD level VLC2 4 pins VLC3 ∗ VLC1 VLC2 VLC3 VLC1 = 3/4VDD VLC2 = 2/4VDD VLC3 = 1/4VDD (when pins left open) IP ∗ ∗ Internal resistor approx. 20kΩ 3 pins XVDD XVDD XTAI XTAO XVSS 4 pins XTAI Oscillation XVSS XTAO –8– CXP402 Circuit format Pin PCO MDP VPCO1 VPCO2 When reset — 4 pins MDS MDS — Output enable 1 pin VCTL FILI CLTV RF BIAS ASYI IP — Poly resistor 6 pins AIN1 AIN2 IP — 2 pins AOUT1 AOUT2 LOUT1 LOUT2 — 4 pins –9– CXP402 Pin Circuit format DATO XLTO CLKO LOCK MON V16M FILO ASYO XRSTO LRCK PCMD BCK GTOP XPCK GFS RFCK C2PO XROF MNT3 MNT1 MNT0 C4M DOUT EMPH WFCK SCOR SBSO 27 pins When reset — – 10 – CXP402 (Vss = 0V reference) Absolute Maximum Ratings Symbol Ratings Supply voltage VDD LCD bias voltage VLC1, VLC2, VLC3 –0.3 to +7.0∗1 –0.3 to +7.0∗2 Input voltage VIN Output voltage VOUT High level output current IOH –5 mA Output pin (value per pin) High level total output current ∑IOH –70 mA Total of output pins Low level output current IOL 15 mA Output pin (value per pin) Low level total output current ∑IOL 100 mA Total of output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –40 to +125 °C Allowable power dissipation PD 600 mW Item Unit Remarks V V –0.3 to +7.0∗2 –0.3 to +7.0∗2 V V ∗1 The potential difference between analog power supplies AVDD, AVss, the oscillation power supplies XVDD, XVss and VDD, Vss should be within ±0.3V. ∗2 VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended conditions. Exceeding those conditions may adversely affect the reliability of the LSI. (Vss = 0V reference) Recommended Operation Conditions Item Symbol Min. Max. Unit Remarks Supply voltage VDD 3.4 5.25 V Operation guaranteed range LCD bias voltage VLC1, VLC2, VLC3 VSS VDD V Liquid crystal power supply range∗1 VIH 0.7VDD VDD V VIHS 0.8VDD VDD V VIL 0 0.3VDD V VILS 0 0.2VDD V Analog input voltage VIA 0 VDD V Operating temperature Topr –20 +75 °C High level input voltage Low level input voltage Hysteresis input∗2 Hysteresis input∗2 ∗3 ∗1 The optimal value depends on the characteristics of the used LCD element. Also, the LCD bias voltage is biased to 1/3 the supply voltage by the resistor of approximately 20kΩ in the LSI. ∗2 RME, XRST, EXCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, PCMDI pins ∗3 CLTV, FILI, RF, VCTL, AIN1, AIN2, BAIS, ASYI pins – 11 – CXP402 Electrical Characteristics DC characteristics Item (Topr = –20 to +75°C, VSS = AVSS = XVSS = 0V reference) Symbol Pins PA, PB VOH BCKI, C2PO, SBSO, DATO, XLTO, CLKO, PA (VOL only), PB (VOL only), PC, MON, MDS, LOCK, LRCK, PCMD, BCK, GTOP, GFS, RFCK, XROF, MNT3, MNT1, MNT0, DOUT, WFCK, SCOR, MDP, VPCO2, VPCO1, PCO, V16M, EMPH, XPCK, ASYO, C4M, XRSTO, LRCK, PCMD FILO High level output voltage Low level output voltage VOL IIH Input current XTAI IILE Conditions Min. VDD = 4.75V, IOH = –0.1mA 4.25 V VDD = 4.75V, IOH = –2.0mA 4.25 V VDD = 4.75V, IOH = –0.28mA 4.25 V Unit 0.4 V VDD = 4.75V, IOL = 6.0mA 0.4 V VDD = 4.75V, IOL = 9.0mA 0.6 V 0.2 30 µA –0.2 –30 µA –0.06 –0.2 mA ±5 µA 30 kΩ 3 5 kΩ 5 15 kΩ 37 80 mA 10 20 pF VDD = 5.25V, VIH = 5.25V VDD = 5.25V, VIL = 0.4V PA to PC High-impedance I/O leak current IIZ PCMDI, RME, XRST, EXCK, FOK, SEIN, CNIN, VCKI, VDD = 5.25V LRCKI, BCKI, VI = 0, 5.25V CLTV, FILI, RF, VCTL, AIN1, AIN2, MDP, MDS, VPCO1, VPCO2 LCD bias voltage resistance RB VLC1, VLC2, VLC3 Common output impedance RCOM COM0 to COM3 Segment output impedance RSEG SEG0 to SEG15 Input capacity Max. VDD = 4.75V, IOL = 0.36mA IIL Supply current Typ. VDD = 5V, VLC1, VLC2, VLC3 pins left open VDD = 5.0V VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25V IDD VDD, AVDD VDD = 5.25V 16.93MHz self-excited oscillation operation All output pins left open CIN Pins other than VLC1 to VLC3, COM0 to COM3, SEG0 to SEG15, PA to PC, VDD, VSS, AVDD, AVSS, XVDD, XVSS Clock 1MHz 0V for no-measured pins – 12 – 7 CXP402 AC Characteristics 1. XTAI pin (1) When using self-excited oscillation (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Oscillation frequency Symbol fMAX Min. Typ. Max. Unit 15 16.93 20 MHz (2) When inputting pulses to XTAI pin (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Symbol Min. Typ. Max. Unit High level pulse width tWHX 13 500 ns Low level pulse width tWLX 13 500 ns Pulse cycle tCK 26 1,000 ns Input high level VIHX VDD – 1.0 Input low level VILX 0.8 V Rise time, fall time tR, tF 10 ns V tCK tWLX tWHX VIHX VIHX × 0.9 VDD/2 XTAI VIHX × 0.1 VILX tR tF (3) When inputting sine waves to XTAI pin via a capacitor (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Input amplitude Symbol Min. VI 2.0 Typ. Max. Unit VDD + 0.3 Vp-p – 13 – CXP402 2. CNIN, EXCK pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Item Symbol Clock frequency fCK Clock pulse width Latch pulse width tWCK tSU tH tD tWL EXCK frequency fT EXCK pulse width fWT Setup time Hold time Delay time Min. Typ. Max. Unit 0.65 MHz 750 ns 300 ns 300 ns 300 ns 750 ns 0.65 750 MHz ns 1/fCK tWCK tWCK CLK DATA XLT tSU tH tD tWL EXCK CNIN tWT tWT 1/fT SUBQ tSU tH 3. BCKI, LRCKI, PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Item BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time Symbol Conditions tW tSU tH tSU Min. Max. Unit 94 ns 18 ns 18 ns 18 ns tW (BCKI) tW (BCKI) BCKI Typ. VDD/2 VDD/2 tSU tH (PCMDI) (PCMDI) PCMDI tSU (LRCKI) LRCKI – 14 – CXP402 1-bit DAC, LPF Blocks Analog Characteristics Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C) Symbol Item Total harmonic distortion THD Signal-tonoise ratio S/N Typ. Max. 384Fs 0.0050 0.0070 768Fs 0.0045 0.0065 Min. Crystal Conditions 1kHz, 0dB data 1kHz, 0dB data (A-filter) 384Fs 96 100 768Fs 96 100 Fs = 44.1kHz. The total harmonic distortion and signal-to-noise ratio are measured by the circuits shown below. 12k AOUT1 (2) 680p 12k 12k SHIBASOKU (AM51A) AIN1 (2) 150p Audio Analyzer LOUT1 (2) 22µ 100k LPF external circuit diagram 768Fs/384Fs DATA Rch A Lch B RF CXP402 TEST DISC Audio Analyzer Block diagram of analog characteristics measurement (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C) Item Symbol Output voltage VOUT Load resistance RL Min. Typ. 1.23∗ 8 ∗ When a sine wave of 1kHz, 0dB is output. Applicable pins ∗1 LOUT1, LOUT2 – 15 – Max. Unit Applicable pins Vrms ∗1 kΩ ∗1 Unit % dB CXP402 Package Outline Unit: mm 112PIN LQFP(PLASTIC) 22.0 ± 0.2 1.7MAX 20.0 ± 0.1 1.4 ± 0.1 84 S 57 0.1 56 85 B A 112 29 28 1 0.65 0.32 ± 0.05 0.13 M S 0° — 10° DETAIL A 0.145 ± 0.03 (0.3) (0.125) 0.6 ± 0.15 0.32 ± 0.05 (0.5) 0.25 (21.0) 0.1 ± 0.05 DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-112P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE LQFP112-P-2020 LEAD MATERIAL COPPER ALLOY PACKAGE WEIGHT 1.3g JEDEC CODE – 16 – S