CXP87740A/87748A CMOS 8-bit Single Chip Microcomputer Description The CXP87740A/87748A is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, PWM generator, PWM for tuner, VISS/VASS circuit, 32kHz timer/event counter, remote control receiving circuit, VCR vertical sync separation circuit and the measuring circuit which measure signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP87740A/87748A provides sleep/stop function which enables to lower power consumption and ultra-low speed instruction mode in 32kHz operation. 100 pin QFP (PIastic) 100 pin LQFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which cover various types of data — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle During operation 333ns/12MHz (Supply voltage 3.0 to 5.5V) During operation 250ns/16MHz (Supply voltage 4.5 to 5.5V) During operation 122µs/32kHz • Incorporated ROM capacity 40K bytes (CXP87740A) 48K bytes (CXP87748A) • Incorporated RAM capacity 1344 bytes • Peripheral functions — A/D converter 8-bit, 12-channel, successive approximation system (Conversion time 20.0µs/16MHz) — Serial interface Incorporated 8-bit and 8-stage FIFO, 1-channel (1 to 8 bytes auto transfer) 8-bit serial I/O, 1-channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter — High precision timing pattern generator PPG 19 pins 32-stage programmable RTG 5-pins 2-channel — PWM/DA gate output 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz) — Servo input control Capstan FG, Drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14-bit, 1-channel — VISS/VASS circuit Pulse duty auto detection circuit — Remote control receiving circuit 8-bit pulse measuring counter, 6-stage FIFO • Interruption 21 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin plastic QFP/LQFP • Piggyback/evaluation chip CXP87700 100-pin ceramic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94Z16-ST AVDD PI3/ADJ PE2/PWM0 PE4/DAA0 PE6/DAB0 PE3/PWM1 PE5/DAA1 PE7/DAB1 PI2/PWM PI1/RMC PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL 12 BIT PWM GENERATOR CH1 12 BIT PWM GENERATOR CH0 14 BIT PWM GENERATOR VISS/VASS FIFO SERVO INPUT CONTROL REMOCON INPUT CTL DRUM CAPSTAN V SYNC SEPARATOR PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 8 BIT TIMER 1 PI3/TO/DDO 8 BIT TIMER/COUNTER 0 PE1/EC FIFO SERIAL INTERFACE UNIT (CH1) SERIAL INTERFACE UNIT (CH0) 4 2 2 3 2 2 2 PE0/INT0 NMI PE1/INT2 CH0 1 CH REALTIME PULSE GENERATOR 32kHz TIMER/COUNTER PRESCALER/ TIME BASE TIMER RAM 1344 BYTES 5 2 RST MP VDD Vss CLOCK GENERATOR/ SYSTEM CONTROL AA 19 RAM PROGRAMMABLE PATTERN GENERATOR ROM 40K/48K BYTES SPC700 CPU CORE FIFO PI4/INT1/NMI FRC CAPTURE UNIT INTERRUPT CONTROLLER AVREF A/D CONVERTER AVss PI7/SI1 PI6/SO1 PI5/SCK1 CS0 SI0 SO0 SCK0 12 TEX TX PA0/PPO0 to PC2/PPO18 AN0 to AN3 PF0/AN4 to PF7/AN11 EXTAL XTAL PC3/RTO3 to PC7/RTO7 8 8 7 8 PJ0 to PJ7 PI1 to PI7 PH0 to PH7 PG0 to PG7 PF4 to PF7 8 PF0 to PF3 4 6 4 PE0 to PE1 PE2 to PE7 PD0 to PD7 PC0 to PC7 PB0 to PB7 PA0 to PA7 2 8 8 8 PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I –2– PORT J Block Diagram CXP87740A/87748A CXP87740A/87748A PI5/SCK1 PI4/INT1/NMI PI3/TO/DDO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Configuration 1 (Top View) 100 pin QFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 1 80 PI6/SO1 PB4/PPO12 2 79 PI7/SI1 PB3/PPO11 3 78 PE0/INT0 PB2/PPO10 4 77 PE1/EC/INT2 PB1/PPO9 5 76 PE2/PWM0 PB0/PPO8 6 75 PE3/PWM1 PC7/RTO7 7 74 PE4/DAA0 PC6/RTO6 8 73 PE5/DAA1 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 PC3/RTO3 11 70 PG0/CFG PC2/PPO18 12 69 PG1/DFG PC1/PPO17 13 68 PG2/DPG PC0/PPO16 14 67 PG3/PBCTL PJ7 15 66 PG4/SYNC0 PJ6 16 65 PG5/SYNC1 PJ5 17 64 PG6/EXI0 PJ4 18 63 PG7/EXI1 PJ3 19 62 AN0 PJ2 20 61 AN1 PJ1 21 60 AN2 PJ0 22 59 AN3 PD7 23 58 PF0/AN4 PD6 24 57 PF1/AN5 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3 27 54 AVDD PD2 28 53 AVREF PD1 29 52 AVSS PD0 30 51 PF4/AN8 Note) PF5/AN9 PF6/AN10 PF7/AN11 SCK0 SO0 SI0 CS0 EXTAL XTAL VSS RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. –3– CXP87740A/87748A PE0/INT0 PI7/SI1 PI6/SO1 PI5/SCK1 PI4/INT1/NMI PI3/TO/DDO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 PB5/PPO13 PB4/PPO12 Pin Configuration 2 (Top View) 100 pin LQFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 1 75 PE1/EC/INT2 PB2/PPO10 2 74 PE2/PWM0 PB1/PPO9 3 73 PE3/PWM1 PB0/PPO8 4 72 PE4/DAA0 PC7/RTO7 5 71 PE5/DAA1 PC6/RTO6 6 70 PE6/DAB0 PC5/RTO5 7 69 PE7/DAB1 PC4/RTO4 8 68 PG0/CFG PC3/RTO3 9 67 PG1/DFG PC2/PPO18 10 66 PG2/DPG PC1/PPO17 11 65 PG3/PBCTL PC0/PPO16 12 64 PG4/SYNC0 PJ7 13 63 PG5/SYNC1 PJ6 14 62 PG6/EXI0 PJ5 15 61 PG7/EXI1 PJ4 16 60 AN0 PJ3 17 59 AN1 PJ2 18 58 AN2 PJ1 19 57 AN3 PJ0 20 56 PF0/AN4 PD7 21 55 PF1/AN5 PD6 22 54 PF2/AN6 PD5 23 53 PF3/AN7 PD4 24 52 AVDD PD3 25 51 AVREF Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. –4– AVSS PF4/AN8 PF5/AN9 PF6/AN10 SCK0 PF7/AN11 SO0 SI0 CS0 EXTAL XTAL VSS RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PD0 PD1 PD2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP87740A/87748A Pin Description Symbol I/O Description PA0/PPO0 to PA7/PPO7 Output/ Real time Output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PB0/PPO8 to PB7/PPO15 Output/ Real time Output (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PC0/PPO16 to PC2/PPO18 I/O/ Real time Output PC3/RTO3 to PC7/RTO7 I/O/ Real time Output (Port C) 8-bit I/O port, enables to specify I/O by bit unit. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Programmable pattern generator (PPG) output. Functions as high precision real time pulse output port. (19 pins) Real time pulse generator (RTG) output. Functions as high precision real time pulse output port. (5 pins) (Port D) 8-bit I/O port. Enable to specify I/O by 4-bit unit. Enables to drive 12mA sink current. (8 pins) PD0 to PD7 I/O PE0/INT0 Input/input Input pin to request external interruption. Active when falling edge. PE1/EC/INT2 Input/input/input External event input pin for timer/counter. (Port E) 8-bit port. Lower 2 bits are input pins and upper 6 bits are output pins. (8 pins) Input pin to request external interruption. Active when falling edge. PE2/PWM0 Output/output PE3/PWM1 Output/output PE4/DAA0 Output/output PE5/DAA1 Output/output PE6/DAB0 Output/output PE7/DAB1 Output/output AN0 to AN3 Input Analog input pins to A/D converter. (12 pins) PF0/AN4 to PF3/AN7 Input/input PF4/AN8 to PF7/AN11 Output/input (Port F) Lower 4 bits are input port and upper 4 bits are output port. Lower 4 bits also serve as standby release input pin. (8 pins) SCK0 I/O Serial clock (CH0) I/O pin. SO0 Ouput Serial data (CH0) output pin. SI0 Input Serial data (CH0) input pin. CS0 Input Serial chip select (CH0) input pin. PWM output pins. (2 pins) DA gate pulse output pins. (4 pins) –5– CXP87740A/87748A Symbol I/O Description PG0/CFG Input/input Capstan FG input pin. PG1/DFG Input/input Drum FG input pin. PG2/DPG Input/input PG3/PBCTL Input/input PG4/SYNC0 Input/input PG5/SYNC1 Input/input PG6/EXI0 Input/input PG7/EXI1 Input/input Drum PG input pin. (Port G) 8-bit input port. (8 pins) Playback CTL pulse input pin. Composite sync signal input pin. External input pin to FRC capture unit. (Port H) 8-bit output port ; Medium withstand voltage (12V) and high current (12mA), N-ch open drain output. (8 pins) PH0 to PH7 Output PI1/RMC I/O/input Remote control receiving circuit input pin. PI2/PWM I/O/output 14-bit PWM output pin. PI3/TO/ DDO/ADJ I/O/output/ output/output PI4/INT1/ NMI I/O/input/Input PI5/SCK1 I/O/I/O PI6/SO1 I/O/output Serial data (CH1) output pin. PI7/SI1 I/O/input Serial data (CH1) input pin. PJ0 to PJ7 I/O EXTAL Input XTAL Output TEX Input TX Output Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (Feedback resistor is not removed.) RST Input System reset pin of active "L" level. MP Input Microprocessor mode input pin. Always connect to GND. Timer/counter, CTL duty detection, 32kHz oscillation adjustment output pin. Input pin to request external interruption and non maskable interruption. Active when falling edge. Serial clock (CH1) I/O pin. (Port J) 8-bit I/O port. Function as standby release input can be specified by bit unit. I/O can be specified by bit unit. Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Positive power supply pin of A/D converter. AVDD AVREF (Port I) 7-bit I/O port. I/O port can be specified by bit unit. (7 pins) Input Reference voltage input pin of A/D converter. AVss GND pin of A/D converter. VDD Positive power supply pin. Vss GND pin. Connect both Vss pins to GND. –6– CXP87740A/87748A Input/Output Circuit Formats for Pins Pin When reset Circuit format Port A AA AA Port B PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15 AAAA AAAA PPO data Port A or Port B Data bus Hi-Z Output becomes active from high impedance by data writing to port register. RD 16 pins Port C PC0/PPO16 to PC2/PPO18 AAAA AAAA AAAA PPO, RTO data Input protection circuit Port C data PC3/RTO3 to PC7/RTO7 AA AA AA AA Hi-Z IP Port C direction (Every bit) Data bus RD (Port C) 8 pins Port D PD0 to PD7 AAAA AAAA AAAA High current 12mA Port D data IP Port D direction (Every 4 bits) PD0 to 3 PD4 to 7 Data bus 8 pins AA AA AA AA RD (Port D) –7– Hi-Z CXP87740A/87748A Pin Circuit format AA AA AAAA Port E When reset Schmitt input PE0/INT0 PE1/EC/INT2 IP 2 pins Hi-Z Data bus RD (Port E) AA AA AAA AA AAA AA AAA Port E AA AA DA gate output or PWM output MPX Hi-Z control PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 Port E data Hi-Z Port/DA output select Data bus 4 pins RD (Port E) AA AA AAAA AA AAAA AAAA AA AA Port E DA gate output MPX Hi-Z control PE6/DAB0 PE7/DAB1 Port E data H level Port/DA output select Data bus 2 pins RD (Port E) AN0 to AN3 A/D converter IP 4 pins Port F PF0/AN4 to PF3/AN7 AA AA AAAA AA A AAA Input multiplexer Input multiplexer A/D converter IP Hi-Z Data bus 4 pins Hi-Z RD (Port F) –8– CXP87740A/87748A Pin Circuit format AAAA AAAA AAAA AA A AAA When reset AA AA AA Port F PF4/AN8 to PF7/AN11 Port F data Data bus RD (Port F) 4 pins PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 8 pins IP Port/AD select Input multiplexer Port G Schmitt input IP Servo input Data bus RD (Port G) AAAA AAAA AAAA AAAAAAA AAA AAAA AAA AAAA AAA AAAA Port H data Data bus 8 pins Hi-Z Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt input can be selected with the mask option. Port H PH0 to PH7 Hi-Z A/D converter AA AA Medium withstand voltage 12V Hi-Z High current 12mA RD (Port H) Port I Port I function select PI2/PWM PI3/TO/ DDO/ADJ PI2: From 14-bit PWM PI3: From timer/counter, CTL duty detection circuit, 32kHz timer MPX Port I data Port I direction Data bus 2 pins RD (Port I) –9– AA AA AA AA IP Hi-Z CXP87740A/87748A PIn Circuit format AAAA AAAA AAAA Port I AA AA AA AA Port I data PI1/RMC PI4/INT1/NMI PI7/SI1 Port I direction IP Data bus RD (Port I) 3 pins When reset Hi-Z Schmitt input PI1: To remote control circuit PI4: To interruption circuit PI7: To serial CH1 AAAA AAAA AA AA AAAA AA AA AA AAAA AA AA AA AAAA AA AA AA AAAA AA AAAA AA AAAA A AA AA AA A AAA AA AA Port I Port I function select PI5/SCK1 PI6/SO1 From serial CH1 MPX Port I data Port I direction MPX IP Note) PI5 is schmitt input PI6 is inverter input Data bus 2 pins Hi-Z RD (Port I) To serial CH1 Port J Port J data PJ0 to PJ7 Port J direction Data bus 8 pins CS0 SI0 RD (Port J) Edge detection Standby release Schmitt input IP 2 pins SO0 SO0 from SIO 1 pin Hi-Z IP SO0 output enable – 10 – Hi-Z To SIO Hi-Z CXP87740A/87748A PIn Circuit format When reset Internal serial clock from SIO SCK0 IP SCK0 output enable External serial clock to SIO Schmitt input 1 pin AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AAAA EXTAL XTAL EXTAL 2 pins XTAL TEX TX 2 pins RST AA AA AA AA • Shows the circuit composition during oscillation. IP • Feedback resistor is removed during stop. XTAL becomes "H" level. 32kHz timer counter TEX TX Hi-Z IP • Shows the circuit composition during oscillation. • Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs "L" level and TX pin outputs "H" level. Oscillation Oscillation Pull-up resistor Mask option Schmitt input OP L level IP 1 pin MP IP 1 pin – 11 – CPU mode Hi-Z CXP87740A/87748A Absolute Maximum Ratings Item (Vss=0V) Symbol VDD Supply voltage AVDD Rating Unit –0.3 to +7.0 AVss to +7.0∗1 V V Remarks V Input voltage VIN –0.3 to +0.3 –0.3 to +7.0∗2 Output voltage VOUT –0.3 to +7.0∗2 V Medium withstand output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of output pins IOL 15 mA IOLC 20 mA Other than high current output pins: per pin High current port pin∗3: per pin Low level total output current ∑IOL 130 mA Total of output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD AVSS Low level output current V 600 380 mW PH pin QFP package type LQFP package type ∗1 AVDD and VDD should be set to a same voltage. ∗2 VIN and VOUT should not exceed VDD + 0.3V. ∗3 The high current operation transistors are the N-CH transistors of the PD and PH ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 12 – CXP87740A/87748A Recommended Operating Conditions Item Supply voltage Analog power supply HIgh level input voltage Symbol Min. Max. Unit Remarks 4.5 5.5 V 3.0 5.5 V fc = 16MHz Guaranteed range during high speed mode (1/2 dividing fc = 12MHz clock) operation 2.7 5.5 V Guaranteed range during low speed mode (1/16 dividing clock) operation 2.7 5.5 V Guaranteed operation range by TEX clock 2.5 5.5 V 3.0 5.5 V Guaranteed data hold operation range during STOP ∗1 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V VIHTS 2.2 VDD V VDD AVDD VIHEX CMOS schmitt input∗3 TTL schmitt input∗4, ∗7 VDD – 0.4 VDD + 0.3 V VDD – 0.2 VDD + 0.2 V EXTAL pin∗5, ∗7 EXTAL pin∗5, ∗8 0 0.3VDD V ∗2, ∗7 0 0.2VDD V ∗2, ∗8 VILS 0 0.2VDD V VILTS 0 0.8 V –0.3 0.4 V –0.3 0.2 V –20 +75 °C VIL Low level input voltage (Vss = 0V) VILEX Operating temperature Topr TEX pin∗6, ∗7 TEX pin∗6, ∗8 CMOS schmitt input∗3 TTL schmitt input∗4, ∗7 EXTAL pin∗5, ∗7 EXTAL pin∗5, ∗8 TEX pin∗6, ∗7 TEX pin∗6, ∗8 ∗1 AVDD and VDD should be set to a same voltage. ∗2 Normal input port (each pin of PC, PD, PE0 to PE1, PF0 to PF3, PG, PI and PJ), MP pin. ∗3 Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1. ∗4 Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option) ∗5 It specifies only when the external clock is input. ∗6 It specifies only when the event count clock is input. ∗7 This case applies to the range of 4.5 to 5.5V supply voltage (VDD). ∗8 This case applies to the range of 3.0 to 3.6V supply voltage (VDD). – 13 – CXP87740A/87748A Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH VOL (Ta = –20 to +75°C, Vss = 0V) Pins Conditions Min. Typ. Max. Unit PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V PD, PH IIHE VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V VDD = 4.5V, IOL = 12.0mA 1.5 V VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA –10 µA IILR VDD = 5.5V, VIL = 0.4V –0.1 RST∗1 –1.5 –400 µA I/O leakage current IIZ PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 VDD = 5.5V, VI = 0, 5.5V ±10 µA Open drain output leakage current (N-CH Tr OFF in state) ILOH PH VDD = 5.5V VOH = 12V 50 µA 24 45 mA 1.3 8 mA 35 100 µA 6 30 µA 10 µA 20 pF IILE Input current EXTAL IIHT IILT TEX 16MHz crystal oscillation (C1 = C2 = 15pF) IDD1 VDD = 5V ± 0.5V∗3 SLEEP mode IDDS1 VDD = 5V ± 0.5V Supply current∗2 IDD2 IDDS2 32kHz crystal oscillation (C1 = C2 = 47pF) VDD VDD = 3V ± 0.3V SLEEP mode VDD = 3V ± 0.3V IDDS3 STOP mode (EXTAL and TEX pins oscillation stop) VDD = 5V ± 0.5V Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss 10 ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗2 When entire output pins are open. ∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 14 – CXP87740A/87748A DC Characteristics (VDD = 3.0 to 3.6V) Item High level output voltage Low level output voltage Symbol VOH VOL Pins Input current Min. Typ. Max. Unit VDD = 3.0V, IOH = –0.15mA 2.7 V VDD = 3.0V, IOH = 0.5mA 2.3 V PD, PH EXTAL IIHT IILT Conditions PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 IIHE IILE (Ta = –20 to +75°C, Vss = 0V) TEX VDD = 3.0V, IOL = 1.2mA 0.3 V VDD = 3.0V, IOL = 1.6mA 0.5 V VDD = 3.0V, IOL = 5mA 1.0 V VDD = 3.6V, VIH = 3.6V 0.3 20 µA VDD = 3.6V, VIL = 0.3V –0.3 –20 µA VDD = 3.6V, VIH = 3.6V 0.1 10 µA –0.1 –10 µA –0.9 –200 µA IILR RST∗1 VDD = 3.6V, VIL = 0.3V I/O leakage current IIZ PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 VDD = 3.6V, VI = 0, 3.6V ±10 µA Open drain output leakage current ILOH PH VDD = 3.6V, VOH = 12V 50 µA 11 25 mA 0.5 2.5 mA 10 µA 20 pF 12MHz crystal oscillation (C1 = C2 = 15pF) IDD1 Supply current∗2 IDDS1 IDDS3 VDD = 3.3V ± 0.3V∗3 SLEEP mode VDD VDD = 3.3V ± 0.3V STOP mode (EXTAL and TEX pins oscillation stop) VDD = 3.3V ± 0.3V Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss 10 ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗2 When entire output pins are open. ∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 15 – CXP87740A/87748A AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Item Symbol Pins Conditions Min. VDD = 4.5 to 5.5V System clock frequency fC XTAL EXTAL Fig. 1, Fig. 2 System clock input pulse width tXL, tXH XTAL EXTAL VDD = 4.5 to 5.5V Fig. 1, Fig. 2 (External clock drive) XTAL EXTAL Fig. 1, Fig. 2 (External clock drive) EC Fig. 3 Event count clock input rise and fall times tCR, tCF tEH, tEL tER, tEF EC Fig. 3 System clock frequency fC TEX TX Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) Event count clock input pulse width tTL, tTH tTR, tTF TEX Fig. 3 TEX Fig. 3 System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times Max. Unit 1 16 1 12 28 MHz ns 37.5 200 tsys × 4∗ ns ns 20 ns 32.768 kHz 10 µs 20 ms ∗ tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied condition AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Crystal oscillation Ceramic oscillation EXTAL C1 XTAL C2 External clock EXTAL 32kHz clock applying condition crystal oscillation TEX XTAL 74HC04 – 16 – C1 TX C2 CXP87740A/87748A Fig. 3. Event count clock timing 0.8VDD TEX EC 0.2VDD tEH tEF tEL tER tTH tTF tTL tTR (2) Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Condition Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) tsys+200 ns CS0 ↑ → SCK0 floating delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) tsys+200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode tsys+200 ns CS0 ↑ → SO0 floating delay time tDCSOF SO0 Chip select transfer mode tsys+200 ns CS0 high level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK0 cycle time Input mode SCK0 2tsys + 200 ns tKCY 16000/fc ns SCK0 high and low level widths tKH tKL tsys + 100 ns SCK0 8000/fc – 50 ns SI0 input setup time (against SCK0 ↑) SCK0 input mode 100 ns tSIK SI0 SCK0 output mode 200 ns SI0 input hold time (against SCK0 ↑) SI0 tsys + 200 ns tKSI 100 ns SCK0 ↓ → SO0 delay time tKSO SO0 Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. – 17 – CXP87740A/87748A Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Symbol Pin Condition Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 250 ns CS0 ↑ → SCK0 floating delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode tsys + 250 ns CS0 ↑ → SO0 floating delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS0 high level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK0 cycle time Input mode SCK0 2tsys + 200 ns tKCY 16000/fc ns SCK0 high and low level widths tKH tKL tsys + 100 ns SCK0 8000/fc – 100 ns SI0 input setup time (against SCK0 ↑) SCK0 input mode 100 ns tSIK SI0 SCK0 output mode 200 ns SI0 input hold time (against SCK0 ↑) SI0 tsys + 200 ns tKSI 100 ns SCK0 ↓ → SO0 delay time tKSO SO0 Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode tsys + 250 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF. – 18 – CXP87740A/87748A Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tKSI tSIK 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 19 – CXP87740A/87748A Serial transfer (CH1) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pins SCK1 cycle time tKCY SCK1 SCK1 high and low level widths tKH tKL SCK1 SI1 input setup time (against SCK1 ↑) tSIK SI1 SI1 input hold time (against SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Conditions Input mode Min. Max. Unit 1000 ns 16000/fc ns 400 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns SCK1 input mode 200 ns SCK1 output mode 100 ns Output mode Input mode Output mode SCK1 input mode 200 ns SCK1 output mode 100 ns Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Serial transfer (CH1) Item (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Symbol Pins SCK1 cycle time tKCY SCK1 SCK1 high and low level widths tKH tKL SCK1 SI1 input setup time (against SCK1 ↑) tSIK SI1 SI1 input hold time (against SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Conditions Input mode Min. Max. Unit 1000 ns 16000/fc ns 400 ns 8000/fc – 100 ns SCK1 input mode 100 ns SCK1 output mode 200 ns SCK1 input mode 200 ns SCK1 output mode 100 ns Output mode Input mode Output mode SCK1 input mode 250 ns SCK1 output mode 100 ns Note) The load of SCK1 output mode and SO1 output delay time is 50pF. – 20 – CXP87740A/87748A Fig. 5. Serial transfer CH1 timing tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD Output data SO1 0.2VDD – 21 – CXP87740A/87748A (3) A/D converter characteristics Item (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Symbol Pins Conditions Min. Typ. Max. Unit 8 Bits ±1 LSB ±2 LSB Resolution Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Linearity error Absolute error Conversion time Sampling time tCONV tSAMP Reference input voltage VREF Analog input voltage VIAN IREFS µs 12/fADC∗ µs AVREF AVDD – 0.5 AN0 to AN11 0 IREF AVREF current 160/fADC∗ V V 0.6 Operating mode AVREF AVDD SLEEP mode STOP mode 32kHz operating mode 1.0 mA 10 µA (Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V) Item Symbol Pins Conditions Min. Typ. Max. Unit 8 Bits ±1 LSB ±2 LSB Resolution Ta = 25°C VDD = AVDD = AVREF = 3.3V VSS = AVSS = 0V Linearity error Absolute error Conversion time Sampling time 160/fADC∗ 12/fADC∗ tCONV tSAMP AVREF AVDD – 0.3 AN0 to AN11 0 Reference input voltage VREF Analog input voltage VIAN IREF AVREF current IREFS Operating mode AVREF SLEEP mode STOP mode 32kHz operating mode µs µs 0.4 AVDD V 0.7 mA 10 µA Fig. 6. Definitions of A/D converter terms Digital conversion value FFH FEH ∗ The value of fADC is as follows by selecting ADC operation clock (MSC: Address 01FFH bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc Linearity error 01H 00H VFT VZT Analog input – 22 – CXP87740A/87748A (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Item Symbol Pins Conditions External interruption high and low level widths tIH tIL INT0 INT1 INT2 NMI PJ0 to PJ7 Reset input low level width tRSL RST Min. Max. Unit 1 µs 32/fc µs Fig. 7. Interruption input timing INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge) tIH tIL 0.8VDD 0.2VDD Fig. 8. Reset input timing tRSL RST 0.2VDD (5) Others (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Item Symbol tCFH tCFL tDFH DFG input tDFL high and low level widths DPG minimum pulse width tDPW CFG input high and low level widths DPG minimum removal time trem PBCTL input high and low level widths tCTH tCTL tEIH tEIL EXI input high and low level widths Pins Conditions Min. Max. Unit CFG tFRC × 24 + 200 ns DFG tFRC × 8 + 200 ns DPG 50 ns DPG 50 ns PBCTL tsys = 2000/fc tFRC × 8 + 200 + tsys ns EXI0 EXI1 tsys = 2000/fc tFRC × 8 + 200 + tsys ns Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11") tFRC [ns] = 1000/fc – 23 – CXP87740A/87748A Fig. 9. Other timings tCFH CFG tCFL 0.8VDD 0.2VDD tDFH DFG tDFL 0.8VDD 0.2VDD trem tDPW trem 0.8VDD DPG tCTH tCTL 0.8VDD PBCTL 0.2VDD tEIH EXI0 EXI1 tEIL 0.8VDD 0.2VDD – 24 – CXP87740A/87748A Supplement Fig. 10. Recommended oscillation circuit AAAAA AAAAA AAAAA (i) EXTAL (ii) AAAA AAAA Rd Rd C2 C1 Manufacturer Model C2 C1 fc (MHz) 8.00 RIVER ELETEC CO., LTD. HC-49/U03 P3 C2 (pF) 10 10 5 5 8.00 16 12 10.00 16 12 12.00 12 12 16.00 12 12 32.768kHz 30 18 16.00 KINSEKI LTD. C1 (pF) 10.00 12.00 HC-49/U (-S) TX TEX XTAL Rd (Ω) Circuit example 0 (i) 0 (i) 470k (ii) Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2). Mask option table Item Reset pin pull-up resistor Input circuit format∗ Content Non-existent Existent C-MOS schmitt TTL schmitt ∗ In PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin. However, TTL schmitt can not be selected when the supply voltage (VDD) ranges from 3.5V to 5.5V. – 25 – CXP87740A/87748A Characteristics Curve IDD vs. VDD IDD vs. fc (fc = 16MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical) 1/4 dividing mode 10.0 20 1/16 dividing mode 5.0 SLEEP mode 1.0 0.5 32kHz mode (instruction) 32kHz mode SLEEP 0.1 (100µA) 0.05 (50µA) IDD – Supply current [mA] IDD – Supply current [mA] 1/2 dividing mode 1/2 dividing mode 20.0 15 1/4 dividing mode 10 5 1/16 dividing mode 0.01 (10µA) SLEEP mode 2 3 4 5 6 7 0 10 5 fc – System clock [MHz] IDD vs. VDD IDD vs. fc (fc = 12MHz, Ta = 25°C, Typical) (VDD = 3.3V, Ta = 25°C, Typical) 20.0 1/2 dividing mode 10.0 1/4 dividing mode 5.0 SLEEP mode 1.0 0.5 0.1 (100µA) 16 20 1/16 dividing mode IDD – Supply current [mA] IDD – Supply current [mA] VDD – Supply voltage [V] 15 1/2 dividing mode 10 0.05 (50µA) 1/4 dividing mode 5 0.01 (10µA) 1/16 dividing mode SLEEP mode 2 3 4 5 6 7 0 VDD – Supply voltage [V] 5 10 fc – System clock [MHz] – 26 – 16 CXP87740A/87748A Unit: mm 100PIN QFP (PLASTIC) + 0.1 0.15 – 0.05 15.8 ± 0.4 + 0.4 14.0 – 0.01 17.9 ± 0.4 23.9 ± 0.4 + 0.4 20.0 – 0.1 A 0.65 + 0.35 2.75 – 0.15 ±0.12 M 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-100P-L01 LEAD TREATMENT EIAJ CODE ∗QFP100-P-1420-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.4g JEDEC CODE 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 51 76 (15.0) 50 0.5 ± 0.2 A 26 (0.22) 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SONY CODE LQFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP100-P-1414-A LEAD MATERIAL 42 ALLOY JEDEC CODE PACKAGE WEIGHT – 27 –