CYPRESS CY14E102L

ADVANCE
CY14E102L, CY14E102N
2-Mbit (256K x 8/128K x 16) nvSRAM
Features
Functional Description
■
15 ns, 20 ns, 25 ns, and 45 ns access times
■
Internally organized as 256K x 8 (CY14E102L) or 128K x 16
(CY14E102N)
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ nonvolatile elements initiated by
software, device pin, or AutoStore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Infinite read, write, and recall cycles
■
200,000 STORE cycles to QuantumTrap
The Cypress CY14E102L/CY14E102N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 256K words of 8 bits each or 128K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data reside in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
■
20 year data retention
■
Single 5V +10% operation
■
Commercial and Industrial temperatures
■
48-pin FBGA, 44 and 54-pin TSOP II packages
■
Pb-free and RoHS compliance
Logic Block Diagram
VCC
VCAP
[1]
Address A0 - A17
[1]
DQ0 - DQ7
CE
OE
CY14E102L
CY14E102N
WE
HSB
BHE
BLE
VSS
Note
1. Address A0 - A17 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A16 and Data DQ0 - DQ15 for x16 configuration.
Cypress Semiconductor Corporation
Document Number: 001-45755 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 27, 2008
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
Pinouts
Figure 1. Pin Diagram - 48 FBGA (Top View)
(x16)
(Not to Scale)
(x8)
(Not to Scale)
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
NC
A
NC
B
DQ8 BHE
A3
A4
CE
DQ0
B
NC
DQ4
C
DQ9 DQ10
A5
A6
DQ1 DQ2
C
A7
DQ5
VCC
D
VSS
A7
DQ3
VCC
D
A16
DQ6
VSS
E
VCC DQ12 VCAP
A16
DQ4
VSS
E
2
3
4
5
6
NC
OE
A0
A1
A2
NC
NC
NC
A3
A4
CE
DQ0
NC
A5
A6
VSS
DQ1
A17
1
VCC
DQ2 VCAP
[2]
DQ11 NC
DQ3
NC
A14
A15
NC
DQ7
F
DQ14 DQ13
A14
A15
DQ5 DQ6
F
[4]
NC
HSB
A12
A13
WE
NC
G
DQ15 HSB
A12
A13
WE
DQ7
G
[2]
NC
A8
A9
A10
A11
[3]
NC
H
[3]
NC
A9
A10
A11
[4]
NC
H
A8
Figure 2. Pin Diagram - 44 TSOP II (Top View)
NC
[4]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(x8)
(Not to Scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HSB
NC
[3]
NC
[2]
NC
A17
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
30
29
28
27
26
25
24
23
VCAP
A14
A13
A12
A11
A10
NC
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(x16)
(Not to Scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
[2]
NC
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
Notes
2. Address expansion for 4 Mbit. NC pin not connected to die.
3. Address expansion for 8 Mbit. NC pin not connected to die.
4. Address expansion for 16 Mbit. NC pin not connected to die.
Document Number: 001-45755 Rev. *A
Page 2 of 21
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CY14E102L, CY14E102N
ADVANCE
Pinouts
(continued)
Figure 3. Pin Diagram - 54 TSOP II (Top View)
NC
[4]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54
53
52
51
50
49
(x16)
(Not to Scale)
19
20
21
22
23
24
25
26
27
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
[3]
NC
[2]
NC
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
NC
NC
Pin Definitions
Pin Name
IO Type
A0 – A17
Input
A0 – A16
Description
Address Inputs. Used to select one of the 262, 144 bytes of the nvSRAM for x8 Configuration.
Address Inputs. Used to select one of the 131, 072 bytes of the nvSRAM for x16 Configuration.
DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE high.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
VSS
Ground
VCC
Ground for the Device. Must be connected to the ground of the system.
Power Supply Power Supply Inputs to the Device.
HSB
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection is optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from the SRAM
to nonvolatile elements.
NC
No Connect No Connect. Do not connect this pin to the die.
Document Number: 001-45755 Rev. *A
Page 3 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
The CY14E102L/CY14E102N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture all cells are stored and
recalled in parallel. During the STORE and RECALL operations
SRAM read and write operations are inhibited. The
CY14E102L/CY14E102N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations.
SRAM Read
The CY14E102L/CY14E102N performs a READ cycle when CE
and OE are LOW, and WE and HSB are HIGH. The address
specified on pins A0-17 or A0-16 determines which of the 262, 144
data bytes or 131, 072 words of 16 bits each is accessed. When
the read is initiated by an address transition, the outputs are valid
after a delay of tAA. If the read is initiated by CE or OE, the
outputs are valid at tACE or at tDOE, whichever is later. The data
outputs repeatedly respond to address changes within the tAA
access time without the need for transitions on any control input
pins. This remains valid until another address change or until CE
or OE is brought HIGH, or WE or HSB is brought LOW.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. Monitor the HSB signal by the system to detect if an
AutoStore cycle is in progress.
Figure 4. AutoStore Mode
Vcc
0.1uF
10kOhm
Device Operation
Vcc
WE
V CAP
V SS
V CAP
SRAM Write
Hardware STORE Operation
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable before entering
the WRITE cycle and must remain stable until either CE or WE
goes high at the end of the cycle. The data on the common IO
pins DQ0–15 are written into the memory if the data is valid tSD
before the end of a WE controlled WRITE or before the end of
an CE controlled WRITE. It is recommended that OE be kept
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE is left LOW, internal circuitry turns off
the output buffers tHZWE after WE goes LOW.
The CY14E102L/CY14E102N provides the HSB pin for
controlling and acknowledging the STORE operations. Use the
HSB pin to request a hardware STORE cycle. When the HSB pin
is driven LOW, the CY14E102L/CY14E102N conditionally
initiates a STORE operation after tDELAY. An actual STORE cycle
only begins if a WRITE to the SRAM took place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition while the STORE (initiated by any means) is in
progress.
AutoStore Operation
SRAM READ and WRITE operations that are in progress when
HSB is driven LOW by any means are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14E102LL/CY14E102N continues SRAM operations for
tDELAY. During tDELAY, multiple SRAM READ operations may take
place. If a WRITE is in progress when HSB is pulled low it is
allowed a time, tDELAY to complete. However, any SRAM WRITE
cycles requested after HSB goes LOW is inhibited until HSB
returns HIGH.
The CY14E102L/CY14E102N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB, Software Store activated by an address
sequence, and AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14E102L/CY14E102N.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the section DC
Electrical Characteristics on page 7 for the size of VCAP .
Document Number: 001-45755 Rev. *A
During any STORE operation, regardless of how it was initiated,
the CY14E102L/CY14E102N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation,
the
CY14E102L/CY14E102N remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Page 4 of 21
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CY14E102L, CY14E102N
ADVANCE
Hardware RECALL (Power Up)
The software sequence may be clocked with CE controlled
READs or OE controlled READs. After the sixth address in the
sequence is entered, the STORE cycle commences and the chip
is disabled. It is important to use READ cycles and not WRITE
cycles in the sequence, although it is not necessary that OE be
LOW for a valid sequence. After the tSTORE cycle time is fulfilled,
the SRAM is activated again for the READ and WRITE operation.
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Software RECALL
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14E102L/CY14E102N
software STORE cycle is initiated by executing sequential
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations must
be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If there are intervening
READ or WRITE accesses, the sequence is aborted and no
STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared and then, the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for READ and WRITE operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Table 1. Mode Selection
CE
H
WE
X
OE
X
A15 - A0
Mode
IO
Power
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[5,6,7]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[5,6,7]
Notes
5. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
6. While there are 18/17 address lines on the CY14E102L/CY14E102N, only the lower 16 lines are used to control software modes.
7. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
Document Number: 001-45755 Rev. *A
Page 5 of 21
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CY14E102L, CY14E102N
ADVANCE
Table 1. Mode Selection (continued)
CE
L
WE
H
OE
L
A15 - A0
Mode
IO
Power
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[5,6,7]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[5,6,7]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
Document Number: 001-45755 Rev. *A
If the AutoStore function is disabled or re-enabled a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Data Protection
The CY14E102L/CY14E102N protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14E102L/CY14E102N
is in a write mode (both CE and WE LOW) at power up, after a
RECALL or STORE, the write is inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer CY Application Note AN1064.
Page 6 of 21
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CY14E102L, CY14E102N
ADVANCE
Maximum Ratings
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface Mount Pb Soldering
Temperature (3 Seconds) .......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
Output Short Circuit Current [8] .................................... 15 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +150°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V
Latch-Up Current ................................................... > 200 mA
Voltage Applied to Outputs
in High-Z State....................................... –0.5V to VCC + 0.5V
Operating Range
Input Voltage.............................................–0.5V to Vcc+0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
Range
Commercial
Industrial
Ambient Temperature
VCC
0°C to +70°C
4.5V to 5.5V
–40°C to +85°C
4.5V to 5.5V
DC Electrical Characteristics
Over the Operating Range (VCC = 4.5V to 5.5V)[10]
Parameter
ICC1
Description
Average VCC Current
Test Conditions
tRC = 15 ns
tRC = 20 ns
tRC = 25 ns
tRC = 45 ns
Dependent on output loading and cycle
rate.Values obtained without output loads.
IOUT = 0 mA
Min
Max
Unit
Commercial
70
65
65
50
mA
mA
mA
Industrial
75
70
70
52
mA
mA
mA
ICC2
Average VCC Current
during STORE
All Inputs Don’t Care, VCC = Max
Average current for duration tSTORE
6
mA
ICC3[9]
Average VCC Current at WE > (VCC – 0.2). All other I/P cycling.
tRC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained
without output loads.
typical
35
mA
ICC4
Average VCAP Current All Inputs Don’t Care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
6
mA
ISB
VCC Standby Current
3
mA
IIX
Input Leakage Current VCC = Max, VSS < VIN < VCC
(except HSB)
–1
+1
μA
Input Leakage Current VCC = Max, VSS < VIN < VCC
(For HSB)
–100
+1
μA
–1
+1
μA
CE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
IOZ
Off-State Output
Leakage Current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH
VIH
Input HIGH Voltage
2.0
VCC + 0.5
V
VIL
Input LOW Voltage
Vss – 0.5
0.8
V
VOH
Output HIGH Voltage
IOUT = –2 mA
VOL
Output LOW Voltage
IOUT = 4 mA
VCAP
Storage Capacitor
Between VCAP pin and VSS, 5V Rated
2.4
61
V
0.4
V
82
μF
Notes
8. Outputs shorted for no more than one second. No more than one output shorted at a time.
9. Typical conditions for the active current shown on the front page of the data sheet are average values at 25°C (room temperature), and VCC = 5V. Not 100% tested.
10. The HSB pin has IOUT=-10 uA for VOH of 2.4V.This parameter is characterized but not tested.
Document Number: 001-45755 Rev. *A
Page 7 of 21
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CY14E102L, CY14E102N
ADVANCE
Capacitance
The following table lists the capacitance parameters.[11]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
Max
Unit
7
pF
7
pF
Thermal Resistance
The following table lists the thermal resistance parameters. [11]
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
Thermal Resistance
(Junction to Case)
48-FBGA 44-TSOP II 54-TSOP II
Unit
28.82
31.11
30.73
°C/W
7.84
5.56
6.08
°C/W
AC Test Loads
963Ω
963Ω
5.0V
5.0V
R1
for tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
512Ω
5 pF
R2
512Ω
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%) ........................ <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
11. These parameters are guaranteed but not tested.
Document Number: 001-45755 Rev. *A
Page 8 of 21
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CY14E102L, CY14E102N
ADVANCE
AC Switching Characteristics
The following table lists the AC switching characteristics.
Parameters
Cypress
Alt
Parameters Parameters
15 ns
Description
Min
20 ns
Max
Min
25 ns
Max
Min
Max
45 ns
Min
Max
Unit
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
tRC[12]
15
tRC
Read Cycle Time
tAA[13]
tAA
Address Access Time
15
20
25
45
ns
tDOE
tOE
Output Enable to Data Valid
10
10
12
20
ns
tOHA
tOH
Output Hold After Address
Change
3
3
3
3
ns
tLZCE[14]
tLZ
Chip Enable to Output Active
3
3
3
3
ns
tHZCE[14]
15
20
20
25
45
ns
Chip Disable to Output Inactive
tOLZ
Output Enable to Output Active
tHZOE[14]
tOHZ
Output Disable to Output
Inactive
tPU[11]
tPA
Chip Enable to Power Active
tPD[11]
tPS
Chip Disable to Power Standby
15
20
25
45
ns
tDBE
-
Byte Enable to Data Valid
10
10
12
20
ns
tLZBE
-
Byte Enable to Output Active
tHZBE
-
Byte Disable to Output Inactive
0
7
0
0
8
0
0
10
ns
tHZ
0
8
45
[14]
tLZOE
7
25
7
0
10
0
0
15
8
ns
15
0
0
ns
ns
0
10
ns
ns
15
ns
SRAM Write Cycle
tWC
tWC
Write Cycle Time
15
20
25
45
ns
tPWE
tWP
Write Pulse Width
10
15
20
30
ns
tSCE
tCW
Chip Enable To End of Write
15
15
20
30
ns
tSD
tDW
Data Setup to End of Write
5
8
10
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
0
ns
tAW
tAW
Address Setup to End of Write
10
15
20
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
0
0
0
ns
tWZ
Write Enable to Output Disable
tOW
Output Active after End of Write
3
3
3
3
ns
-
Byte Enable to End of Write
15
15
20
30
ns
tHZWE[14,15]
tLZWE
tBW
[14]
7
8
10
15
ns
Notes
12. WE must be HIGH during SRAM read cycles.
13. Device is continuously selected with CE and OE both LOW.
14. Measured ±200 mV from steady state output voltage.
15. If WE is LOW when CE goes LOW, the output goes into high impedance state.
Document Number: 001-45755 Rev. *A
Page 9 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
AutoStore and Power Up RECALL
Parameters
CY14E102L/CY14E102N
Description
Min
Unit
Max
tHRECALL [16] Power Up RECALL Duration
20
ms
STORE Cycle Duration
15
ms
VSWITCH
Low Voltage Trigger Level
4.4
V
tVCCRISE
VCC Rise Time
tSTORE
[17]
μs
150
Software Controlled STORE and RECALL Cycle
The following table lists the software controlled STORE and RECALL cycle parameters.[18, 19]
Parameters
Description
15ns
Min
20 ns
Max
Min
25ns
Max
Min
45ns
Max
Min
Max
Unit
tRC
STORE and RECALL Initiation Cycle Time
15
20
25
45
ns
tAS
Address Setup Time
0
0
0
0
ns
tCW
Clock Pulse Width
12
15
20
30
ns
tGHAX
Address Hold Time
1
1
1
1
ns
tRECALL
RECALL Duration
200
200
200
200
μs
tSS [20, 21]
Soft Sequence Processing Time
70
70
70
70
μs
Hardware STORE Cycle
Parameters
Description
CY14E102L/CY14E102N
Min
Max
70
tDELAY [22]
Time allowed to complete SRAM cycle
1
tHLHX
Hardware STORE pulse width
15
Unit
μs
ns
Notes
16. tHRECALL starts from the time VCC rises above VSWITCH.
17. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.
18. The software sequence is clocked with CE controlled or OE controlled reads.
19. The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles.
20. This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.
21. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
22. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete.
Document Number: 001-45755 Rev. *A
Page 10 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled[12, 13, 23]
tRC
ADDRESS
t AA
t OHA
DQ (DATA OUT)
DATA VALID
Figure 6. SRAM Read Cycle #2: CE and OE Controlled[12, 23, 25]
tRC
ADDRESS
tLZCE
CE
tACE
tPD
tHZCE
OE
tLZOE
t HZOE
tDOE
BHE , BLE
tLZBE
DQ (DATA OUT)
t PU
ICC
tHZCE
tHZBE
tDBE
DATA VALID
ACTIVE
STANDBY
Notes
23. HSB must remain HIGH during READ and WRITE cycles.
24. CE or WE must be >VIH during address transitions.
25. BHE and BLE are applicable for x16 configuration only.
Document Number: 001-45755 Rev. *A
Page 11 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
Switching Waveforms (continued)
Figure 7. SRAM Write Cycle #1: WE Controlled[13, 21, 22, 23]
t WC
ADDRESS
t HA
t SCE
CE
t AW
t SA
t PWE
WE
t BW
BHE , BLE
t SD
t HD
DATA VALID
DATA IN
tHZWE
DATA OUT
t LZWE
HIGH IMPEDANCE
PREVIOUS DATA
Figure 8. SRAM Write Cycle #2: CE Controlled[13, 21, 22, 23]
tWC
ADDRESS
tSA
tSCE
CE
tHA
tAW
WE
BHE , BLE
tPWE
tBW
tSD
DATA IN
DATA OUT
Document Number: 001-45755 Rev. *A
tHD
DATA VALID
HIGH IMPEDANCE
Page 12 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
Switching Waveforms (continued)
Figure 9. AutoStore or Power Up RECALL[26]
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
VCC
VSWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
tHRECALL
Read & Write Inhibited
Figure 10. CE Controlled Software STORE/RECALL Cycle[19]
Note
26. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
Document Number: 001-45755 Rev. *A
Page 13 of 21
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CY14E102L, CY14E102N
ADVANCE
Switching Waveforms (continued)
Figure 11. OE Controlled Software STORE/RECALL Cycle[19]
tRC
ADDRESS # 1
ADDRESS
CE
tAS
ADDRESS # 6
tCW
OE
tGHAX
DATA VALID
a
a
DQ (DATA)
t STORE / t RECALL
DATA VALID
a
a
a
a
a
a
a
a
a
a
a a
tRC
HIGH IMPEDANCE
Figure 12. Hardware STORE Cycle[22]
Figure 13. Soft Sequence Processing[20, 21]
tSS
Document Number: 001-45755 Rev. *A
tSS
Page 14 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
Ordering Information
Speed
(ns)
15
20
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY14B102L-ZS15XCT
51-85087
44-pin TSOP II
Commercial
CY14E102L-ZS15XIT
51-85087
44-pin TSOP II
Industrial
CY14E102L-ZS15XI
51-85087
44-pin TSOP II
CY14E102L-BA15XCT
51-85128
48-ball FBGA
Commercial
Industrial
CY14E102L-BA15XIT
51-85128
48-ball FBGA
CY14E102L-BA15XI
51-85128
48-ball FBGA
CY14E102L-ZSP15XCT
51-85160
54-pin TSOP II
Commercial
CY14E102L-ZSP15XIT
51-85160
54-pin TSOP II
Industrial
CY14E102L-ZSP15XI
51-85160
54-pin TSOP II
CY14E102N-BA115XCT
51-85128
48-ball FBGA
Commercial
CY14E102N-BA15XIT
51-85128
48-ball FBGA
Industrial
CY14E102N-BA15XI
51-85128
48-ball FBGA
CY14E102N-ZSP15XCT
51-85160
54-pin TSOP II
Commercial
CY14E102N-ZSP15XIT
51-85160
54-pin TSOP II
Industrial
CY14E102N-ZSP15XI
51-85160
54-pin TSOP II
CY14B102L-ZS20XCT
51-85087
44-pin TSOP II
Commercial
Industrial
CY14E102L-ZS20XIT
51-85087
44-pin TSOP II
CY14E102L-ZS20XI
51-85087
44-pin TSOP II
CY14E102L-BA20XCT
51-85128
48-ball FBGA
Commercial
CY14E102L-BA20XIT
51-85128
48-ball FBGA
Industrial
CY14E102L-BA20XI
51-85128
48-ball FBGA
CY14E102L-ZSP20XCT
51-85160
54-pin TSOP II
Commercial
Industrial
CY14E102L-ZSP20XIT
51-85160
54-pin TSOP II
CY14E102L-ZSP20XI
51-85160
54-pin TSOP II
CY14E102N-BA20XCT
51-85128
48-ball FBGA
Commercial
CY14E102N-BA20XIT
51-85128
48-ball FBGA
Industrial
CY14E102N-BA20XI
51-85128
48-ball FBGA
CY14E102N-ZSP20XCT
51-85160
54-pin TSOP II
Commercial
Industrial
CY14E102N-ZSP20XIT
51-85160
54-pin TSOP II
CY14E102N-ZSP20XI
51-85160
54-pin TSOP II
Document Number: 001-45755 Rev. *A
Page 15 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
Ordering Information (continued)
Speed
(ns)
25
45
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY14E102L-ZS25XCT
51-85087
44-pin TSOP II
Commercial
CY14E102L-ZS25XIT
51-85087
44-pin TSOP II
Industrial
CY14E102L-ZS25XI
51-85087
44-pin TSOP II
CY14E102N-BA25XCT
51-85128
48-ball FBGA
Commercial
Industrial
CY14E102L-BA25XIT
51-85128
48-ball FBGA
CY14E102L-BA25XI
51-85128
48-ball FBGA
CY14E102L-ZSP25XCT
51-85160
54-pin TSOP II
Commercial
CY14E102L-ZSP25XIT
51-85160
54-pin TSOP II
Industrial
CY14E102L-ZSP25XI
51-85160
54-pin TSOP II
CY14E102N-BA25XCT
51-85128
48-ball FBGA
Commercial
CY14E102N-BA25XIT
51-85128
48-ball FBGA
Industrial
CY14E102N-BA25XI
51-85128
48-ball FBGA
CY14E102N-ZSP25XCT
51-85160
54-pin TSOP II
Commercial
CY14E102N-ZSP25XIT
51-85160
54-pin TSOP II
Industrial
CY14E102N-ZSP25XI
51-85160
54-pin TSOP II
CY14E102L-ZS45XCT
51-85087
44-pin TSOP II
Commercial
Industrial
CY14E102L-ZS45XIT
51-85087
44-pin TSOP II
CY14E102L-ZS45XI
51-85087
44-pin TSOP II
CY14E102L-BA45XCT
51-85128
48-ball FBGA
Commercial
CY14E102L-BA45XIT
51-85128
48-ball FBGA
Industrial
CY14E102L-BA45XI
51-85128
48-ball FBGA
CY14E102L-ZSP45XCT
51-85160
54-pin TSOP II
Commercial
Industrial
CY14E102L-ZSP45XIT
51-85160
54-pin TSOP II
CY14E102L-ZSP45XI
51-85160
54-pin TSOP II
CY14E102N-BA45XCT
51-85128
48-ball FBGA
Commercial
CY14E102N-BA45XIT
51-85128
48-ball FBGA
Industrial
CY14E102N-BA45XI
51-85128
48-ball FBGA
CY14E102N-ZSP45XCT
51-85160
54-pin TSOP II
Commercial
Industrial
CY14E102N-ZSP45XIT
51-85160
54-pin TSOP II
CY14E102N-ZSP45XI
51-85160
54-pin TSOP II
All parts are Pb-free. The above table contains Advance information. Please contact your local Cypress sales representative for availability of these parts.
Document Number: 001-45755 Rev. *A
Page 16 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
Part Numbering Nomenclature
CY 14 E 102 L - ZS P 15 X C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
P - 54 Pin
Blank - 44 Pin
Package:
BA - 48 FBGA
ZS - TSOP II
Voltage:
E - 5.0V
Data Bus:
L - x8
N - x16
Speed:
15 - 15 ns
20 - 20 ns
25 - 25 ns
45 - 45 ns
Density:
102 - 2 Mb
NVSRAM
14 - Auto Store + Software Store + Hardware Store
Cypress
Document Number: 001-45755 Rev. *A
Page 17 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
Package Diagrams
Figure 14. 44-Pin TSOP II
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
1
23
10.262 (0.404)
10.058 (0.396)
11.938 (0.470)
11.735 (0.462)
22
EJECTOR PIN
44
TOP VIEW
0.800 BSC
(0.0315)
OR E
K X A
SG
BOTTOM VIEW
0.400(0.016)
0.300 (0.012)
10.262 (0.404)
10.058 (0.396)
BASE PLANE
0.210 (0.0083)
0.120 (0.0047)
0°-5°
0.10 (.004)
Document Number: 001-45755 Rev. *A
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
18.517 (0.729)
18.313 (0.721)
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
51-85087-*A
Page 18 of 21
[+] Feedback
CY14E102L, CY14E102N
ADVANCE
Package Diagrams
(continued)
Figure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
10.00±0.10
10.00±0.10
1
F
G
H
H
1.875
A
A
B
0.75
6.00±0.10
0.53±0.05
B
0.15 C
0.21±0.05
0.25 C
3.75
6.00±0.10
0.15(4X)
Document Number: 001-45755 Rev. *A
1.20 MAX
0.36
SEATING PLANE
C
51-85128-*D
Page 19 of 21
[+] Feedback
ADVANCE
Package Diagrams
CY14E102L, CY14E102N
(continued)
Figure 16. 54-Pin TSOP II
51-85160-**
Document Number: 001-45755 Rev. *A
Page 20 of 21
[+] Feedback
ADVANCE
CY14E102L, CY14E102N
Document History Page
Document Title: CY14E102L/CY14E102N 2-Mbit (256K x 8/128K x 16) nvSRAM
Document Number: 001- 45755
REV.
ECN NO.
Orig. of
Change
**
2470086
GVCH
*A
2522209
GVCH/
AESA
Submission
Date
Description of Change
New Data Sheet
06/27/2008
Added 20 ns access speed information in “Features”.
Added ICC1 for tRC=20 ns for both industrial and Commercial temperature Grade.
Updated Thermal resistance values for 48-FBGA, 44-TSOP II and 54-TSOP II
Packages.
Added AC Switching Characteristics specs for 20 ns access speed.
Added software controlled STORE/RECALL cycle specs for 20 ns access speed.
Updated ordering information and part numbering nomenclature.
Updated data sheet template.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
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© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-45755 Rev. *A
Revised June 27, 2008
Page 21 of 21
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
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