CYPRESS CY14V256LA

CY14V256LA
256-Kbit (32 K × 8) nvSRAM
256-Kbit (32 K × 8) nvSRAM
Features
Functional Description
■
35 ns access time
■
Internally organized as 32 K × 8
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power down
■
RECALL to SRAM initiated by software or power up
■
Infinite read, write, and recall cycles
■
1 million STORE cycles to QuantumTrap
The Cypress CY14V256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 K bytes of 8 bits each. The embedded
nonvolatile elements incorporate QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
■
20 year data retention
■
Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
■
Industrial temperature
■
48-ball fine-pitch ball grid array (FBGA) package
■
Pb-free and restriction of hazardous substances (RoHS)
compliance
Logic Block Diagram
Logic Block Diagram
VCC VCCQ VCAP
Quantum Trap
512 X 512
A5
DQ 3
DQ 4
DQ 5
DQ 6
RECALL
STORE/
RECALL
CONTROL
HSB
A14 - A 2
COLUMN I/O
INPUT BUFFERS
DQ 2
STATIC RAM
ARRAY
512 X 512
SOFTWARE
DETECT
DQ 0
DQ 1
POWER
CONTROL
STORE
ROW DECODER
A6
A7
A8
A9
A 11
A 12
A 13
A 14
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-76295 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 3, 2013
CY14V256LA
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ................................................................ 4
SRAM Write ................................................................. 4
AutoStore Operation .................................................... 4
Hardware STORE Operation ....................................... 4
Hardware RECALL (Power-Up) .................................. 5
Software STORE ......................................................... 5
Software RECALL ....................................................... 5
Preventing AutoStore .................................................. 6
Data Protection ............................................................ 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Loads .................................................................. 9
AC Test Conditions .......................................................... 9
AC Switching Characteristics ....................................... 10
SRAM Read Cycle .................................................... 10
SRAM Write Cycle ..................................................... 10
Document Number: 001-76295 Rev. *B
Switching Waveforms .................................................... 11
AutoStore/Power-up RECALL ....................................... 13
Switching Waveforms .................................................... 14
Software Controlled STORE/RECALL Cycle ................ 15
Switching Waveforms .................................................... 15
Hardware STORE Cycle ................................................. 16
Switching Waveforms .................................................... 16
Truth Table For SRAM Operations ................................ 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Page 2 of 22
CY14V256LA
Pinout
Figure 1. 48-ball FBGA (6 × 10 × 1.2 mm) pinout
(× 8)
Top View
(not to scale)
2
3
4
5
6
NC
OE
A0
A1
A2
VCC
A
NC
NC
A3
A4
CE
NC
B
DQ0
VCC
A5
A6
NC
DQ4
C
VSS
DQ1
NC
A7
DQ5 VCCQ
1
VCAP VSS
D
DQ6
VSS
E
VSS
NC
DQ7
F
A12
A13
WE
NC
G
A9
A10
A11
NC
H
VCCQ
DQ2
DQ3
NC
A14
NC
HSB
NC
A8
Pin Definitions
Pin Name
A0–A14
DQ0–DQ7
I/O Type
Input
Description
Address inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation.
WE
Input
Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE
Input
Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
VSS
Ground
VCC
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the core of the device.
VCCQ
Power supply Power supply inputs for the inputs and outputs of the device.
HSB
Input/Output Hardware STORE busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each hardware
and software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC
No connect
No connect. This pin is not connected to the die.
Document Number: 001-76295 Rev. *B
Page 3 of 22
CY14V256LA
The CY14V256LA nvSRAM is made up of two functional
components paired in the same physical cell. They are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14V256LA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer to the Truth Table For SRAM Operations on page 17 for a
complete description of read and write modes.
SRAM Read
The CY14V256LA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A0–14 determines which of the 32,768 data bytes each are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of tAA (read cycle 1). If the read
is initiated by CE or OE, the outputs are valid at tACE or at tDOE,
whichever is later (read cycle 2). The data output repeatedly
responds to address changes within the tAA access time without
the need for transitions on any control input pins. This remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if the data is valid tSD before the end of
a WE-controlled write or before the end of a CE-controlled write.
Keep OE HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14V256LA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by HSB; Software STORE activated by an address sequence;
AutoStore on device power down. The AutoStore operation is a
unique feature of QuantumTrap technology and is enabled by
default on the CY14V256LA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled using the soft sequence specified in Preventing
AutoStore on page 6. If AutoStore is enabled without a capacitor
on VCAP pin, the device attempts an AutoStore operation without
sufficient charge to complete the Store. This corrupts the data
stored in nvSRAM.
Document Number: 001-76295 Rev. *B
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 7 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. Place a
pull-up on WE to hold it inactive during power up. This pull-up is
only effective if the WE signal is tristate during power up. Many
MPUs tristate their controls on power-up. This must be verified
when using the pull-up. When the nvSRAM comes out of
power-on-RECALL, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 2. AutoStore Mode
VCCQ
VCC
0.1 uF
0.1 uF
10 kOhm
Device Operation
VCCQ
VCC
WE
VCAP
VCAP
VSS
Hardware STORE Operation
The CY14V256LA provides the HSB pin to control and
acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14V256LA conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle only begins if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 k weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14V256LA. But any SRAM read and write cycles
Page 4 of 22
CY14V256LA
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0FC0 Initiate STORE Cycle
are inhibited until HSB is returned HIGH by MPU or other
external source.
During any STORE operation, regardless of how it is initiated,
the CY14V256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
tLZHSB time after HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power-Up)
During power up or after any low-power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0C63 Initiate RECALL Cycle
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14V256LA Software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
To initiate the Software STORE cycle, the following read
sequence must be performed:
Table 1. Mode Selection
CE
WE
OE
A14–A0[1]
Mode
I/O
Power
H
X
X
X
Not selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output data
Active
L
L
X
X
Write SRAM
Input data
Active
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output data
Output data
Output data
Output data
Output data
Output data
Active [2]
Notes
1. While there are 15 address lines on the CY14V256LA, only the 13 address lines (A14–A2) are used to control software modes. Rest of the address lines are don’t care.
2. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-76295 Rev. *B
Page 5 of 22
CY14V256LA
Table 1. Mode Selection (continued)
CE
WE
OE
A14–A0[1]
Mode
I/O
Power
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output data
Output data
Output data
Output data
Output data
Output data
Active[3]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output data
Output data
Output data
Output data
Output data
Output High Z
Active ICC2[3]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[3]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B46 AutoStore Enable
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled
and written 0x00 in all cells.
Data Protection
The CY14V256LA protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and write operations. The low-voltage condition is detected when
VCC < VSWITCH. If the CY14V256LA is in a write mode (both CE
and WE are LOW) at power up, after a RECALL or STORE, the
write is inhibited until the SRAM is enabled after tLZHSB (HSB to
output active). When VCCQ < VIODIS, I/Os are disabled (no
STORE takes place). This protects against inadvertent writes
during brown out conditions on VCCQ supply.
Note
3. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-76295 Rev. *B
Page 6 of 22
CY14V256LA
Maximum Ratings
Transient voltage (< 20 ns) on
any pin to ground potential ...............–2.0 V to VCCQ + 2.0 V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time:
At 150 C ambient temperature ..................... 1000 h
At 85 C ambient temperature .................... 20 Years
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current
(1 output at a time, 1s duration) .................................. 15 mA
Maximum junction temperature ................................. 150 C
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Latch up current .................................................... > 140 mA
Supply voltage on VCCQ relative to VSS ......–0.5 V to 2.45 V
Voltage applied to outputs
in High Z State ..................................–0.5 V to VCCQ + 0.5 V
Input voltage .....................................–0.5 V to VCCQ + 0.5 V
Operating Range
Ambient
Temperature
Range
Industrial
VCC
VCCQ
–40 C to +85 C 3.0 V to 3.6 V 1.65 V to 1.95 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
Description
Test Conditions
Power supply voltage
VCCQ
ICC1
Average VCC current
ICCQ1
Average VCCQ current
tRC = 35 ns
Values obtained without output
loads
(IOUT = 0 mA)
ICC2
Average VCC current during
STORE
ICC3
Average VCC current at
tRC = 200 ns, VCC(Typ), 25 °C
ICCQ3
Average VCCQ current at
tRC = 200 ns, VCCQ(Typ), 25 °C
ICC4
Min
Typ [4]
Max
Unit
3.0
3.3
3.6
V
1.65
1.8
1.95
V
–
–
60
mA
–
–
20
mA
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
10
mA
All inputs cycling at CMOS levels.
Values obtained without output
loads (IOUT = 0 mA)
–
35
–
mA
–
5
–
mA
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average
current for duration tSTORE
–
–
8
mA
ISB
VCC standby current
CE > (VCCQ – 0.2 V).
VIN < 0.2 V or > (VCCQ – 0.2 V).
Standby current level after
nonvolatile cycle is complete. Inputs
are static. f = 0 MHz
–
–
8
mA
IIX[5]
Input leakage current
(except HSB)
VCCQ = Max, VSS < VIN < VCCQ
–1
–
+1
µA
Input leakage current (for HSB)
VCCQ = Max, VSS < VIN < VCCQ
–100
–
+1
µA
Notes
4. Typical values are at 25 °C, VCC = VCC(Typ) and VCCQ= VCCQ(Typ). Not 100% tested.
5. The HSB pin has IOUT = –4 µA for VOH of 1.07 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document Number: 001-76295 Rev. *B
Page 7 of 22
CY14V256LA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Min
Typ [4]
Max
Unit
–1
–
+1
µA
0.7 × VCCQ
–
VCCQ + 0.3
V
– 0.3
–
0.3 × VCCQ
V
VCCQ – 0.45
–
–
V
Test Conditions
IOZ
Off-state output leakage current VCCQ = Max, VSS < VOUT < VCCQ,
CE or OE > VIH or WE < VIL
VIH
Input HIGH voltage
VIL
Input LOW voltage
–
VOH
Output HIGH voltage
IOUT = –1 mA
–
VOL
Output LOW voltage
IOUT = 2 mA
–
–
0.45
V
VCAP[6]
Storage capacitor
Between VCAP pin and VSS,
5 V rated
61
68
180
µF
VVCAP[7, 8]
Maximum voltage driven on VCAP VCC = Max
pin by the device
–
–
VCC
V
Min
Unit
Data Retention and Endurance
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
20
Years
1,000
K
Max
Unit
7
pF
Capacitance
Parameter [8]
Description
Test Conditions
CIN
Input capacitance (except HSB) TA = 25 C, f = 1 MHz, VCC = VCC(Typ), VCCQ = VCCQ(Typ)
Input capacitance (for HSB)
8
pF
COUT
Output capacitance (except HSB)
7
pF
Output capacitance (for HSB)
8
pF
Thermal Resistance
Parameter [8]
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
48-ball FBGA
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
48.19
C/W
6.5
C/W
Notes
6. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on
VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options.
7. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating
temperature range should be higher than the VVCAP voltage.
8. These parameters are guaranteed by design and are not tested.
Document Number: 001-76295 Rev. *B
Page 8 of 22
CY14V256LA
AC Test Loads
Figure 3. AC Test Loads
450 
450 
1.8 V
1.8 V
R1
for tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
450 
5 pF
R2
450 
AC Test Conditions
Input pulse levels.................................................0 V to 1.8 V
Input rise and fall times (10% to 90%)...................... < 1.8 ns
Input and output timing reference levels........................ 0.9 V
Document Number: 001-76295 Rev. *B
Page 9 of 22
CY14V256LA
AC Switching Characteristics
Over the Operating Range
Parameters [9]
Cypress
Parameters
35 ns
Description
Alt
Parameters
Min
Max
Unit
SRAM Read Cycle
tACE
tACS
Chip enable access time
–
35
ns
tRC[10]
tAA[11]
tRC
Read cycle time
35
–
ns
tAA
Address access time
–
35
ns
tDOE
tOE
Output enable to data valid
–
15
ns
tOHA[11]
tOH
Output hold after address change
3
–
ns
tLZCE[12, 13]
tLZ
Chip enable to output active
3
–
ns
tHZCE[12, 13]
tHZ
Chip disable to output inactive
–
13
ns
tLZOE[12, 13]
tOLZ
Output enable to output active
0
–
ns
tHZOE[12, 13]
tOHZ
Output disable to output inactive
–
13
ns
tPU[12]
tPA
Chip enable to power active
0
–
ns
tPD[12]
tPS
Chip disable to power standby
–
35
ns
SRAM Write Cycle
tWC
tWC
Write cycle time
35
–
ns
tPWE
tWP
Write pulse width
25
–
ns
tSCE
tCW
Chip enable to end of write
25
–
ns
tSD
tDW
Data setup to end of write
12
–
ns
tHD
tDH
Data hold after end of write
0
–
ns
tAW
tAW
Address setup to end of write
25
–
ns
tSA
tAS
Address setup to start of write
0
–
ns
tHA
tWR
Address hold after end of write
0
–
ns
tHZWE[12, 13, 14] tWZ
Write enable to output disable
–
13
ns
tLZWE[12, 13]
Output active after end of write
3
–
ns
tOW
Notes
9. Test conditions assume signal transition time of 1.8 ns or less, timing reference levels of VCCQ/2, input pulse levels of 0 to VCC Q(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 3 on page 9.
10. WE must be HIGH during SRAM read cycles.
11. Device is continuously selected with CE and OE LOW.
12. These parameters are guaranteed by design and are not tested.
13. Measured ±200 mV from steady state output voltage.
14. If WE is low when CE goes low, the outputs remain in the high-impedance state.
Document Number: 001-76295 Rev. *B
Page 10 of 22
CY14V256LA
Switching Waveforms
Figure 4. SRAM Read Cycle #1 (Address Controlled) [15, 16, 17]
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
Data Output
tOHA
Figure 5. SRAM Read Cycle #2 (CE and OE Controlled) [15, 17]
Address
Address Valid
tRC
tHZCE
tACE
CE
tAA
tLZCE
tHZOE
tDOE
OE
tLZOE
Data Output
High Impedance
Output Data Valid
tPU
ICC
Standby
tPD
Active
Notes
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE and OE LOW.
17. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-76295 Rev. *B
Page 11 of 22
CY14V256LA
Switching Waveforms (continued)
Figure 6. SRAM Write Cycle #1 (WE Controlled) [18, 19, 20]
tWC
Address
Address Valid
tSCE
tHA
CE
tAW
tPWE
WE
tSA
tHD
tSD
Data Input
Input Data Valid
tLZWE
tHZWE
Data Output
High Impedance
Previous Data
Figure 7. SRAM Write Cycle #2 (CE Controlled) [18, 19, 20]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tPWE
WE
tSD
Input Data Valid
Data Input
Data Output
tHD
High Impedance
Notes
18. HSB must remain HIGH during READ and WRITE cycles.
19. If WE is low when CE goes low, the outputs remain in the high impedance state.
20. CE or WE must be > VIH during address transitions.
Document Number: 001-76295 Rev. *B
Page 12 of 22
CY14V256LA
AutoStore/Power-up RECALL
Over the Operating Range
Parameter
Description
CY14V256LA
Min
Max
Unit
tHRECALL [21]
Power-up RECALL duration
–
20
ms
tSTORE [22]
STORE cycle duration
–
8
ms
tDELAY [23]
Time allowed to complete SRAM write cycle
–
25
ns
VSWITCH
Low voltage trigger level for VCC
–
2.90
V
VIODIS[24]
tVCCRISE[25]
VHDIS[25]
tLZHSB[25]
tHHHD[25]
I/O disable voltage on VCCQ
–
1.50
V
150
–
µs
HSB output disable voltage on VCC
–
1.9
V
HSB to output active time
–
5
µs
HSB high active time
–
500
ns
VCC rise time
Notes
21. tHRECALL starts from the time VCC rises above VSWITCH.
22. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
23. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
24. HSB is not defined below VIODIS voltage.
25. These parameters are guaranteed by design and are not tested.
Document Number: 001-76295 Rev. *B
Page 13 of 22
CY14V256LA
Switching Waveforms
Figure 8. AutoStore or Power-up RECALL [26]
VCC
VSWITCH
VHDIS
VCCQ
VIODIS
22
t VCCRISE
Note
tHHHD
HSB OUT
VCCQ
22
tSTORE
Note
t HHHD
tSTORE
Note
27
27
Note
tDELAY
tLZHSB
AutoStore
t LZHSB
tDELAY
POWERUP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
VCC
Read POWER
POWER-UP Read
&
DOWN
&
RECALL
Write V
Write AutoStore
CCQ
BROWN
OUT
AutoStore
BROWN
OUT
I/O Disable
Notes
26. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
27. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-76295 Rev. *B
Page 14 of 22
CY14V256LA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
Parameter [28, 29]
35 ns
Description
Min
35
Max
–
Unit
tRC
STORE/RECALL initiation cycle time
ns
tSA
Address setup time
0
–
ns
tCW
Clock pulse width
20
–
ns
tHA
Address hold time
0
–
ns
tRECALL
RECALL duration
–
200
µs
Switching Waveforms
Figure 9. CE and OE Controlled Software STORE/RECALL Cycle [29]
tRC
Address
tRC
Address #1
tSA
Address #6
tCW
tCW
CE
tHA
tSA
tHA
tHA
tHA
OE
tHHHD
HSB (STORE only)
tHZCE
tLZCE
t DELAY
30
Note
tLZHSB
High Impedance
tSTORE/tRECALL
DQ (DATA)
RWI
Figure 10. AutoStore Enable / Disable Cycle [29]
Address
tRC
tRC
Address #1
Address #6
tSA
CE
tCW
tCW
tHA
tSA
tHA
tHA
tHA
OE
tLZCE
tHZCE
tSS
30
Note
t DELAY
DQ (DATA)
RWI
Notes
28. The software sequence is clocked with CE controlled or OE controlled reads.
29. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
30. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
Document Number: 001-76295 Rev. *B
Page 15 of 22
CY14V256LA
Hardware STORE Cycle
Over the Operating Range
Parameters
CY14V256LA
Description
Min
Max
25
Unit
tDHSB
HSB to output active time when write latch not set
–
tPHSB
Hardware STORE pulse width
15
–
ns
tSS [31, 32]
Soft sequence processing time
–
100
s
ns
Switching Waveforms
Figure 11. Hardware STORE Cycle [33]
Write Latch set
~
~
tPHSB
HSB (IN)
tSTORE
tHHHD
~
~
~
~
tDELAY
HSB (OUT)
SO
tLZHSB
RWI
Write Latch not set
~
~
tPHSB
HSB (IN)
tDELAY
tDHSB
tDHSB
~
~
HSB (OUT)
HSB pin is driven high to VCCQ only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
RWI
Figure 12. Soft Sequence Processing [31, 32]
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
tSS
Soft Sequence
Command
Address #1
tSS
Address #6
tCW
CE
VCC
Notes
31. This is the amount of time it takes to take action on a soft sequence command. VCC and VCCQ power must remain HIGH to effectively register command.
32. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
33. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-76295 Rev. *B
Page 16 of 22
CY14V256LA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 2. Truth Table for
CE
WE
OE
Inputs/Outputs
H
X
X
High Z
Deselect / Power-down
Standby
L
H
L
Data out (DQ0–DQ7)
Read
Active
L
H
H
High Z
Output disabled
Active
L
L
X
Data in (DQ0–DQ7)
Write
Active
Document Number: 001-76295 Rev. *B
Mode
Power
Page 17 of 22
CY14V256LA
Ordering Information
Speed
(ns)
35
Ordering Code
CY14V256LA-BA35XIT
Package
Diagram
Package Type
51-85128 48-ball FBGA
Operating
Range
Industrial
CY14V256LA-BA35XI
All parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 14 V 256 L A - BA 35 X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (–40 to 85 °C)
Pb-free
Speed:
35 - 35 ns
Die revision:
Blank - No Rev
A - 1st Rev
Package:
BA - 48-ball FBGA
Data Bus:
L-×8
Voltage:
V - 3.3 V VCC, 1.8 V VCCQ
Density:
256 - 256 Kb
14 - nvSRAM
Cypress
Document Number: 001-76295 Rev. *B
Page 18 of 22
CY14V256LA
Package Diagrams
Figure 13. 48-ball FBGA (6 × 10 × 1.2 mm) BA48B Package Outline, 51-85128
51-85128 *F
Document Number: 001-76295 Rev. *B
Page 19 of 22
CY14V256LA
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
CMOS
chip enable
complementary metal oxide semiconductor
°C
degree Celsius
EIA
electronic industries alliance
k
kilohm
FBGA
fine-pitch ball grid array
MHz
megahertz
HSB
I/O
hardware store busy
A
microampere
input/output
F
microfarad
nvSRAM
nonvolatile static random access memory
s
microsecond
OE
SRAM
output enable
mA
milliampere
static random access memory
mm
millimeter
RoHS
restriction of hazardous substances
ms
millisecond
RWI
Read and write inhibited
ns
nanosecond
WE
write enable

ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-76295 Rev. *B
Symbol
Unit of Measure
Page 20 of 22
CY14V256LA
Document History Page
Document Title: CY14V256LA, 256-Kbit (32 K × 8) nvSRAM
Document Number: 001-76295
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
3536107
GVCH
03/06/2012
New data sheet.
*A
3701497
GVCH
08/02/2012
Changed status from Summary to Final.
Updated DC Electrical Characteristics (Added VVCAP parameter and its details,
added Note 7 and referred the same note in VVCAP parameter, also referred
Note 8 in VVCAP parameter).
*B
3990042
GVCH
05/03/2013
Updated Maximum Ratings (Changed “Ambient temperature with power
applied” to “Maximum junction temperature”).
Document Number: 001-76295 Rev. *B
Description of Change
Page 21 of 22
CY14V256LA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-76295 Rev. *B
Revised May 3, 2013
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 22 of 22