CY62128DV30 MoBL 1 Mb (128K x 8) Static RAM Features • • • • • • • • power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW). Very high speed: 55 and 70 ns Wide voltage range: 2.2V to 3.6V Pin compatible with CY62128V Ultra-low active power — Typical active current: 0.85 mA @ f = 1 MHz — Typical active current: 5 mA @ f = fMAX Ultra-low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power-down when deselected Packages offered in a 32-lead SOIC, a 32-lead TSOP, a 32-lead Short TSOP, and a 32-lead Reverse TSOP Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Write Enable(WE) LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A0 thro. A16). Functional Description[1] The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/Oo through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or during a write operation (CE1 LOW, CE2 HIGH), and WE LOW). Logic Block Diagram I/O0 Data in Drivers A0 A1 A2 A3 A4 A5 A 6 A7 A8 A 9 A10 A11 128K x 8 ARRAY I/O 2 SENSE AMPS ROW DECODER I/O1 I/O 3 I/O 4 I/O 5 CE1 CE2 COLUMN DECODER I/O 6 Powerdown I/O 7 OE A 15 A 16 A 12 A 13 A 14 WE Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05231 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 29, 2003 CY62128DV30 MoBL Pin Configuration[2] Top View SOIC NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TSOP I Top View (not to scale) A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CE2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 Reverse TSOP I Top View (not to scale) 25 26 27 26 28 29 30 31 32 1 2 3 4 5 6 7 8 STSOP Top View (not to scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE1 A10 OE Note: 2. NC pins are not connected to the die. Document #: 38-05231 Rev. *C Page 2 of 11 CY62128DV30 MoBL Maximum Ratings DC Input Voltage[3] ................................ −0.3V to VCC + 0.3V (Above which the useful life may be impaired. For user guidelines, not tested.) Output Current into Outputs (LOW)............................. 20 mA Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential .......................................................... −0.3V to 3.9V Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range DC Voltage Applied to Outputs in High-Z State[3] ....................................−0.3V to VCC + 0.3V Range Ambient Temperature (TA) VCC[4] Industrial −40°C to +85°C 2.2V to 3.6V Product Portfolio Power Dissipation Operating, Icc (mA) VCC Range (V) Product CY62128DV30L f = 1 MHz f = fMAX Standby, ISB2 (µA) Min. Typ. Max. Speed (ns) 2.2 3.0 3.6 55/70 0.85 1.5 5 10 1.5 5 55/70 0.85 1.5 5 10 1.5 4 CY62128DV30LL Typ.[5] Max. Typ.[5] Max. Typ.[5] Max. DC Electrical Characteristics (Over the Operating Range) CY62128DV30-55/70 Parameter Description Test Conditions Min. Typ.[5] Output HIGH Voltage 2.2 < VCC < 2.7 IOH = −0.1 mA 2.0 2.7 < VCC < 3.6 IOH = −1.0 mA 2.4 VOL Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 2.7 < VCC < 3.6 IOL = 2.1 mA VIH Input HIGH Voltage 2.2 < VCC < 2.7 VIL Input LOW Voltage IIX Input Leakage Current IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current f = fMAX = 1/tRC Automatic CE Power-down Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < 0.2V, L VIN > VCC − 0.2V, VIN < 0.2V, LL f = fMAX (Address and Data Only), f = 0 (OE, WE,) 1.5 5 1.5 4 Automatic CE Power-down Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC=3.6V L 1.5 5 LL 1.5 4 ISB1 ISB2 Unit Max. VOH V 0.4 V 0.4 1.8 VCC + 0.3 2.7 < VCC < 3.6 2.2 VCC + 0.3 2.2 < VCC < 2.7 −0.3 0.6 2.7 < VCC < 3.6 −0.3 0.8 GND < VI < VCC −1 +1 f = 1 MHz −1 Vcc = 3.6V, IOUT = 0mA, CMOS level V V µA +1 µA 5 10 mA 0.85 1.5 µA µA Capacitance[6] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. Unit 8 pF 8 pF Notes: 3. VIL(min.) = −2.0V for pulse durations less than 20 ns., VIH(max.) = Vcc+0.75V for pulse durations less than 20 ns. 4. Full device operation requires linear ramp of Vcc from 0V to Vcc(min) and Vcc must be stable at Vcc(min) for 500 µ s. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 6. Tested initially and after any design or proces changes that may affect these parameters. Document #: 38-05231 Rev. *C Page 3 of 11 CY62128DV30 MoBL Thermal Resistance Parameter Description Test Conditions θJA Thermal Resistance (Junction to Ambient) θJC Thermal Resistance (Junction to Case)[6] [6] SOIC TSOP I STSOP Unit Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 69 93 65 °C/W 34 17 15 °C/W AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC Typ GND R2 CL = 50 pF 90% 10% 90% 10% Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: Fall Time: 1 V/ns THÉVENIN EQUIVALENT RTH OUTPUT Parameters R1 R2 RTH VTH VTH 3.0V (2.7 – 3.6V) 1103 1554 645 1.75 2.5V (2.2– 2.7V) 16600 15400 8000 1.2 Unit Ω Ω Ω V Data Retention Characteristics Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[5] Chip Deselect to Data Retention Time tR [7] Conditions Min. Typ.[5] Max. Unit 1.5 VCC = 1.5V, CE1 > VCC − 0.2V, CE2 < 0.2V, L VIN > VCC − 0.2V or VIN < 0.2V LL Operation Recovery Time V 4 µA 3 0 ns 100 µs Data Retention Waveform DATA RETENTION MODE VCC V CC(min.) tCDR VD R > 1.5V VCC(min.) tR CE1 or CE 2 Note: 7. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 us. Document #: 38-05231 Rev. *C Page 4 of 11 CY62128DV30 MoBL Switching Characteristics (Over the Operating Range)[8] CY62128DV30-55 Parameter Description Min. Max. CY62128DV30-70 Min. Max. Unit Read Cycle tRC Read Cycle Time 55 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW or CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to Low Z[9] tHZOE OE HIGH to High Z[9,10] 25 ns tLZCE CE1 LOW or CE2 HIGH to Low Z[9] tHZCE CE1 HIGH or CE2 LOW to High Z[9,10] 25 ns tPU CE1 LOW or CE2 HIGH to Power-up tPD CE1 HIGH or CE2 LOW to Power-down 70 ns 55 10 ns 70 10 5 5 20 10 ns 10 20 0 ns 0 55 ns ns ns Write Cycle[11] tWC Write Cycle Time 55 70 tSCE CE1 LOW or CE2 HIGH to Write End 40 60 ns tAW Address Set-up to Write End 40 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 50 ns tSD Data Set-up to Write End 25 30 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[9,10] tLZWE WE HIGH to Low Z[9] 0 20 10 ns ns 25 10 ns ns Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 8. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t. 10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 11. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals. 12. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 13. WE is HIGH for Read cycle. Document #: 38-05231 Rev. *C Page 5 of 11 CY62128DV30 MoBL Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[10, 13, 14] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (WE Controlled) [11, 15, 16, 17] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tHA tAW tPWE WE t SD DATA I/O tHD DATA VALID Notes: 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 15. Data I/O is high-impedance if OE = VIH. 16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05231 Rev. *C Page 6 of 11 CY62128DV30 MoBL Switching Waveforms (continued) Write Cycle No. 2 (CE</>1</> or CE</>2</> Controlled) [11, 15, 16, 17] t WC ADDRESS t SCE CE 1 t SA CE 2 t AW t HA t PWE WE OE t SD DATA I/O t HD DATA IN VALID Write Cycle No. 3 (WE Controlled, OE LOW)[10, 16, 17] t WC ADDRESS t SCE CE 1 CE 2 t SCE t AW t SA t HA t PWE WE tSD DON'T CARE DATA I/O t HD DATA VALID t LZWE t HZWE Truth Table I/O0–I/O7 Mode Power CE1 CE2 WE OE H X X X High Z Deselect/Power-down Standby (I SB ) X L X X High Z Deselect/Power-down Standby (I SB ) L H H L Data Out Read Active (I CC) L H H H High Z Output Disabled Active (I CC) L H L X Data In Write Active (I CC) Document #: 38-05231 Rev. *C Page 7 of 11 CY62128DV30 MoBL Ordering Information Speed (ns) 55 70 Ordering Code Package Name Package Type CY62128DV30L-55SI S34 32-lead SOIC CY62128DV30LL-55SI S34 32-lead SOIC CY62128DV30L-55ZI Z32 32-lead TSOP Type 1 CY62128DV30LL-55ZI Z32 32-lead TSOP Type 1 CY62128DV30L-55ZAI ZA32 Operating Range Industrial 32-lead Short TSOP Type 1 CY62128DV30LL-55ZAI ZA32 32-lead Short TSOP Type 1 CY62128DV30L-55ZRI ZR32 32-lead Reverse TSOP Type 1 CY62128DV30LL-55ZRI ZR32 32-lead Reverse TSOP Type 1 CY62128DV30L-70SI S34 32-lead SOIC CY62128DV30LL-70SI S34 32-lead SOIC CY62128DV30L-70ZI Z32 32-lead TSOP Type 1 CY62128DV30LL-70ZI Z32 32-lead TSOP Type 1 CY62128DV30L-70ZAI ZA32 Industrial 32-lead Short TSOP Type 1 CY62128DV30LL-70ZAI ZA32 32-lead Short TSOP Type 1 CY62128DV30L-70ZRI ZR32 32-lead Reverse TSOP Type 1 CY62128DV30LL-70ZRI ZR32 32-lead Reverse TSOP Type 1 Package Diagrams 32-Lead (450 MIL) Molded SOIC S34 51-85081-*A Document #: 38-05231 Rev. *C Page 8 of 11 CY62128DV30 MoBL 32-Lead Thin Small Outline Package Type I (8 x 20 mm) Z32 51-85056-*D 32-Lead Shrunk Thin Small Outline Package (8 x 13.4 mm) ZA32 51-85094-*D Document #: 38-05231 Rev. *C Page 9 of 11 CY62128DV30 MoBL 32-Lead Reverse Thin Small Outline Package ZR32 51-85089-*C MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05231 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62128DV30 MoBL Document History Page Document Title: CY62128DV30 MoBL® 1 Mb (128K x 8) Static RAM Document Number: 38-05231 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 117691 08/27/02 JUI *A 127314 5/27/03 MPR *B 128342 07/23/03 JUI Changed from Preliminary to Final Add 70-ns speed, updated ordering information *C 129002 08/29/03 CDY Changed Icc 1 MHz typ from 0.5 mA to 0.85 mA Document #: 38-05231 Rev. *C New Data Sheet Changed from Advance Information to Preliminary Changed Isb2 to 5 uA (L), 4 uA (LL) Changed Iccdr to 4 uA (L), 3 uA (LL) Changed Cin from 6 pF to 8 pF Page 11 of 11