CY7C1399D PRELIMINARY 256K (32K x 8) Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1399B • Single 3.3V power supply • Ideal for low-voltage cache memory applications • High speed — tAA = 8 ns • Low active power — ICC = 60 mA @ 10 ns • Low CMOS standby power — ISB2 = 1.2 mA (“L” Version only) • Data Retention at 2.0V • Available in 28-SOJ and 28-TSOP I Pb-Free packages The CY7C1399D is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. The device has an automatic power-down feature, reducing the power consumption when deselected. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399D is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I Pb-Free packages. Logic Block Diagram Pin Configurations SOJ Top View I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 32K x 8 ARRAY A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O3 I/O4 I/O5 CE WE I/O6 POWER DOWN COLUMN DECODER I/O7 A 14 A 12 A 13 A 11 A 10 OE Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05467 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 10, 2005 PRELIMINARY CY7C1399D Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current L 1399D-10 10 60 3.0 1.2 1399D-12 12 50 3.0 1.2 1399D-15 15 40 3.0 1.2 Unit ns mA mA Pin Configuration TSOP I Top View OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 Document #: 38-05467 Rev. *C 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 Page 2 of 10 PRELIMINARY CY7C1399D DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................–0.5V to VCC + 0.5V Range Ambient Temperature Commercial Industrial VCC 0°C to +70°C 3.3V ±300 mV –40°C to +85°C 3.3V ±300 mV Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage[2] IIX Input Load Current IOZ Output Leakage Current 7C1399D-12 Min. Max. 2.4 Max. 2.4 0.4 GND ≤ VI ≤ VCC, Output Disabled Current[3] 7C1399D-10 Min. Unit V 0.4 V 2.0 VCC +0.3V 2.0 VCC +0.3V V –0.3 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA –300 –300 mA 60 50 mA IOS Output Short Circuit ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-down Current — TTL Inputs Max. VCC, CE ≥ VIH, VIN ≥ VIH, or VIN ≤ VIL,f = fMAX 10 10 mA L 10 10 mA Automatic CE Power-down Current — CMOS Inputs[4] Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, L WE ≥VCC – 0.3V or WE ≤0.3V, f = fMAX 3.0 3.0 mA 1.2 1.2 mA ISB2 VCC = Max., VOUT = GND 7C1399D-15 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. Max. 2.4 Unit V 0.4 V 2.0 VCC +0.3V V VIL Input LOW Voltage –0.3 0.8 V IIX Input Load Current –1 +1 µA IOZ Output Leakage Current –1 +1 µA –300 mA GND ≤ VI ≤ VCC, Output Disabled [3] IOS Output Short Circuit Current ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 40 mA ISB1 Automatic CE Power-Down Current — TTL Inputs Max. VCC, CE ≥ VIH, VIN ≥ VIH, or VIN ≤ VIL, f = fMAX 10 mA 10 mA Automatic CE Power-Down Current — CMOS Inputs[4] Max. VCC, CE ≥ VCC–0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, WE≥VCC–0.3V or L WE≤ 0.3V, f=fMAX ISB2 VCC = Max., VOUT = GND L 3.0 mA 1.2 mA Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Device draws low standby current regardless of switching on the addresses. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05467 Rev. *C Page 3 of 10 PRELIMINARY CY7C1399D Capacitance[5] Parameter Description CIN: Addresses Test Conditions Input Capacitance Max. Unit 5 pF 6 pF 6 pF TA = 25°C, f = 1 MHz, VCC = 3.3V CIN: Controls COUT Output Capacitance Thermal Resistance[5] Parameter Description ΘJA Thermal Resistance (Junction to Ambient)[5] ΘJC Thermal Resistance (Junction to Case)[5] Test Conditions All – Packages Unit Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board TBD °C/W TBD °C/W AC Test Loads and Waveforms 10-ns Device 12-ns Device Z = 50Ω OUTPUT R1 317Ω 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 3.3V 30 pF* OUTPUT 1.5V 30pF (a) Equivalent to: R2 351Ω INCLUDING JIG AND SCOPE THÉVENIN EQUIVALENT (b) 167Ω OUTPUT 1.73V High-Z characteristics: R1 317 Ω 3.3V ALL INPUT PULSES 3.0V 10% 90% 10% 90% GND OUTPUT ≤ 3 ns ≤ 3 ns R2 351Ω 5 pF INCLUDING JIG AND SCOPE (c) (d) Switching Characteristics Over the Operating Range [7] 1399D-10 Parameter Description Min. Max. 1399D-12 Min. Max. 1399D-15 Min. Max. Unit Read Cycle tpower[6] VCC(typical) to the first access 100 10 100 µs 100 tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 15 ns tDOE OE LOW to Data Valid 5 5 6 ns tLZOE OE LOW to Low Z[8] 3 tHZOE OE HIGH to High CE LOW to Low Z[8] ns 6 3 ns ns 0 5 3 ns 15 3 0 5 3 15 12 3 0 Z[8, 9] tLZCE 12 10 ns ns Notes: 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF. Document #: 38-05467 Rev. *C Page 4 of 10 PRELIMINARY CY7C1399D Switching Characteristics Over the Operating Range (continued)[7] 1399D-10 Parameter Description tHZCE CE HIGH to High tPU CE LOW to Power-Up Max. Min. 5 0 CE HIGH to Power-Down tPD Write Cycle Min. Z[8, 9] 1399D-12 Max. 1399D-15 Min. 6 0 10 Max. Unit 7 ns 0 12 ns 15 ns [10, 11] tWC Write Cycle Time 10 12 15 ns tSCE CE LOW to Write End 8 8 10 ns tAW Address Set-Up to Write End 7 8 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 7 8 10 ns tSD Data Set-Up to Write End 5 7 8 ns tHD Data Hold from Write End 0 0 0 ns tHZWE WE LOW to High Z[10] tLZWE WE HIGH to Low Z[8] 7 3 7 3 7 3 ns ns Notes: 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±200 mV from steady state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05467 Rev. *C Page 5 of 10 PRELIMINARY CY7C1399D Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current Non-L, Com’l / Ind’l tCDR tR[12] Max. Unit 3 mA 1.2 mA 2.0 L-Version Only Chip Deselect to Data Retention Time [5] Min. VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Operation Recovery Time V 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VDR > 2V 3.0V VCC 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2[14, 15] tRC CE tACE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tHZOE tHZCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05467 Rev. *C Page 6 of 10 PRELIMINARY CY7C1399D Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[10, 16, 17] tWC ADDRESS CE tAW tHA tSA WE tPWE OE tSD DATA I/O NOTE 18 tHD DATAINVALID tHZOE Write Cycle No. 2 (CE Controlled)[10, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATAINVALID Write Cycle No. 3 (WE Controlled, OE LOW)[11, 17] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O tHD DATA IN VALID NOTE 18 tHZWE tLZWE Notes: 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in the output state and input signals should not be applied. Document #: 38-05467 Rev. *C Page 7 of 10 PRELIMINARY CY7C1399D Truth Table CE H WE X OE X Input/Output High Z Mode Deselect/Power-Down Power Standby (ISB) L H L L L Data Out Read Active (ICC) X Data In Write Active (ICC) L H H High Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) 10 12 15 Ordering Code Package Name Package Type CY7C1399D-10VXC V21 28-Lead Molded SOJ (Pb-Free) CY7C1399D-10ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399DL-10VXC V21 28-Lead Molded SOJ (Pb-Free) CY7C1399DL-10ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399D-10VXI V21 28-Lead Molded SOJ (Pb-Free) CY7C1399D-10ZXI Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399DL-10VXI V21 28-Lead Molded SOJ (Pb-Free) CY7C1399DL-10ZXI Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399D-12VXC V21 28-Lead Molded SOJ (Pb-Free) CY7C1399D-12ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399DL-12VXC V21 28-Lead Molded SOJ (Pb-Free) CY7C1399DL-12ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399D-12VXI V21 28-Lead Molded SOJ (Pb-Free) CY7C1399D-12ZXI Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399DL-12VXI V21 28-Lead Molded SOJ (Pb-Free) CY7C1399DL-12ZXI Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399D-15VXC V21 28-Lead Molded SOJ (Pb-Free) CY7C1399D-15ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399DL-15VXC V21 28-Lead Molded SOJ (Pb-Free) CY7C1399DL-15ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399D-15VXI V21 28-Lead Molded SOJ (Pb-Free) CY7C1399D-15ZXI Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399DL-15VXI V21 28-Lead Molded SOJ (Pb-Free) CY7C1399DL-15ZXI Z28 28-Lead Thin Small Outline Package (Pb-Free) Operating Range Commercial Industrial Industrial Commercial Industrial Industrial Commercial Industrial Industrial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05467 Rev. *C Page 8 of 10 PRELIMINARY CY7C1399D Package Diagrams 28-Lead (300-Mil) Molded SOJ V21 51-85031-B 28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28 51-85071-*G All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05467 Rev. *C Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C1399D Document History Page Document Title: CY7C1399D 256K (32K x 8) Static RAM (Preliminary) Document Number: 38-05467 REV. Ecn No. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233722 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in the ‘ordering information *B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307594 See ECN RKF Reduced Speed bins to -10, -12 and -15 ns Document #: 38-05467 Rev. *C Description of Change Page 10 of 10