CYPRESS CY7C43686-15AC

CY7C43666 CY7C436461K/4K/16K x36/x18/x2 Tri Bus FIFO
CY7C43646
CY7C43666
CY7C43686
1K/4K/16K x36/x18/x2 Tri Bus FIFO
Features
• Fully asynchronous and simultaneous read and write
operation permitted
• High-speed, low-power, first-in first-out (FIFO) memories w/ three independent ports (one bidirectional x36,
and two unidirectional x18)
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• 1K x36/x18x2 (CY7C43646)
• Retransmit function
• 4K x36/x18x2 (CY7C43666)
• Standard or FWFT mode user-selectable
• 16K x36/x18x2 (CY7C43686)
• Partial Reset
• 0.35-micron CMOS for optimum speed/power
• Big or Little Endian format for word or byte bus sizes
• High speed 133-MHz operation (7.5-ns read/write
cycle times)
• 128-pin TQFP packaging
• Easily expandable in width and depth
• Low power
— ICC= 100 mA
— ISB= 10 mA
Logic Block Diagram
MBF1
CLKA
MBA
RT2
MRS1
PRS1
1K/4K/16K
x36
Dual Ported
Memory
Input
Register
ENA
Output
Port A
Control
Logic
Register
CSA
W/RA
Output
Bus Matching
Mail1
Register
B0−17
CLKB
Port B
Control
Logic
RENB
CSB
SIZEB
MBB
FIFO1,
Mail1
Reset
Logic
FFA/IRA
RTI
Read
Pointer
Write
Pointer
Status
Flag Logic
AFA
SPM
FS0/SD
FS1/SEN
Programmable
Flag Offset
Registers
EFB/ORB
AEB
Common
Port Logic
(B and C)
Timing
Mode
BE/FWFT
A0−35
Status
Flag Logic
AFC
FIFO2,
Mail2
Reset
Logic
Write
Pointer
Read
Pointer
256/512/1K
4K/16K x36
Dual Ported
Memory
Output
Register
FFC/IRC
PRS2
CLKC
Port C
Control
Logic
Mail2
Register
MRS2
C0−17
Input
Register
AEA
Input
Bus Matching
EFA/ORA
BE
WENC
SIZEC
MBC
MBF2
Cypress Semiconductor Corporation
Document #: 38-06023 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised September 26, 2003
CY7C43646
CY7C43666
CY7C43686
Selection Guide
Maximum Frequency
Maximum Access Time
CY7C43646/66/86
-7
CY7C43646/66/86
-10
CY7C43646/66/86
-15
Unit
133
100
66.7
MHz
6
8
10
ns
7.5
10
15
ns
Minimum Data or Enable Set-up
3
4
5
ns
Minimum Data or Enable Hold
0
0
0
ns
Minimum Cycle Time
Maximum Flag Delay
Active Power Supply
Current (ICC1)
Commercial
6
8
8
ns
100
100
100
mA
Industrial
100
CY7C43646
CY7C43666
CY7C43686
Density
1K x 36
4K x 36
16K x 36
Package
128 TQFP
128 TQFP
128 TQFP
EFB/ORB
FFC/IRC
GND
CSB
WENC
RENB
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
MBF1
VCC
AEB
AFC
TQFP
Top View
VCC
AFA
AEA
MBF2
MBA
MRS1
FS0/SD
CLKC
GND
FS1/SEN
MRS2
MBB
CSA
FFA/IRA
EFA/ORA
PRS1
Pin Configuration
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
RT2
A12
CY7C43646
CY7C43666
CY7C43686
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
CLKB
PRS2
VCC
C17
C16
C15
C14
GND
MBC
C13
C12
C11
C10
C9
C8
RT1
C7
C6
SIZEB
GND
C5
C4
C3
C2
C1
C0
GND
B17
B16
SIZEC
VCC
B15
B14
B13
B12
GND
B11
B10
Document #: 38-06023 Rev. *C
GND
B6
VCC
B7
B8
B9
B2
B3
B4
B5
GND
A5
A4
A3
SPM
VCC
A2
A1
A0
GND
B0
B1
A9
A8
A7
A6
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND
A11
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Page 2 of 39
CY7C43646
CY7C43666
CY7C43686
Functional Description
The CY7C436X6 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory,
which supports clock frequencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x36
dual-port SRAM FIFOs on board each chip buffer data in
opposite directions.
The CY7C436X6 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide
a simple bidirectional interface between microprocessors
and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B or Port C bus width. Each mailbox register
has a flag (MBF1 and MBF2) to signal when new mail has
been stored.
Two kinds of reset are available on the CY7C436X6: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array,
configures the FIFO for Big or Little Endian byte arrangement
and selects serial flag programming, parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pin, MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. Each FIFO has its own,
independent Partial Reset pin, PRS1 and PRS2.
The CY7C436X6 have two modes of operation. In the CY
Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first long-word (36-bit-wide) written to an empty FIFO appears
automatically on the outputs, no read operation required
(nevertheless, accessing subsequent words does necessitate
a formal read request). The state of the BE/FWFT pin during
FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
flag (FFA/IRA and FFC/IRC). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is full or not. The IR and OR functions are selected in
the First-Word Fall-Through Mode. IR indicates whether or not
the FIFO has available memory locations. OR shows whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.[1]
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFC).
AEA and AEB indicate when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFC indicate when a selected number
of words written to the memory achieve a predetermined
“almost full state.”[2]
IRA, IRC, AFA, and AFC are synchronized to the port clock
that writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFC are loaded
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA and AFC threshold can be set at 8, 16, or
64 locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. Such a width expansion requires no additional
external components.
The CY7C436X6 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is greater than 2001V, and latch-up is prevented by
the use of guard rings.
Pin Definitions
Signal Name
Description
I/O
Function
A0–35
Port A Data
I/O 36-bit bidirectional data port for side A.
AEA
Port A Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKA. It is LOW when the
number of words in FIFO2 is less than or equal to the value in the Almost Empty A
offset register, X2.[2]
AEB
Port B Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKB. It is LOW when the
number of words in FIFO1 is less than or equal to the value in the Almost Empty B
offset register, X1.[2]
AFA
Port A Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKA. It is LOW when the number
of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.[2]
AFC
Port C Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKC. It is LOW when the number
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.[2]
B0–17
Port B Data
O
18-bit output data port for port B.
Document #: 38-06023 Rev. *C
Page 3 of 39
CY7C43646
CY7C43666
CY7C43686
Pin Definitions (continued)
Signal Name
Description
I/O
Function
BE/FWFT
Big Endian/
First-Word
Fall-Through
Select
I
This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word
on Port A is transferred to Port B first for A-to-B data flow. For data flowing from Port
C to Port A, the first word/byte written to Port C will come out as the most significant
word/byte on Port A. On the other hand a LOW on BE will select Little Endian operation.
In this case, the least significant byte or word on Port A is transferred to Port B first for
A to B data flow. Similarly, the first word/byte written into Port C will come out as the
least significant word/byte on Port A for C-to-A data flow. After Master Reset, this pin
selects the timing mode. A HIGH on FWFT selects CY Standard Mode, a LOW selects
First-Word Fall-Through Mode. Once the timing mode has been selected, the level on
this pin must be static throughout device operation.
C0–17
Port B Data
I
18-bit input data port for port C.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A
and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA
are all synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchronous or coincident to CLKA. EFB/ORB and AEB are all synchronized to the LOW-to-HIGH transition of CLKB.
CLKC
Port C Clock
I
CLKC is a continuous clock that synchronizes all data transfers through Port C
and can be asynchronous or coincident to CLKA. FFC/IRC, and AFC are all synchronized to the LOW-to-HIGH transition of CLKC.
CSA
Port A Chip
Select
I
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write
on Port A. The A0−35 outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
I
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write
on Port B. The B0–17 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA
Port A
Empty/Output
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the EFA function is selected.
EFA indicates whether or not the FIFO2 memory is empty. In the FWFT Mode, the ORA
function is selected. ORA indicates the presence of valid data on A0−35 outputs,
available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of
CLKA.[1]
EFB/ORB
Port B
Empty/Output
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the EFB function is selected.
EFB indicates whether or not the FIFO1 memory is empty. In the FWFT Mode, the ORB
function is selected. ORB indicates the presence of valid data on B0–17 outputs,
available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of
CLKB.[1]
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write
data on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write
data on Port B.
FFA/IRA
Port A Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the FFA function is selected.
FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA
function is selected. IRA indicates whether or not there is space available for writing to
the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC
Port C Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the FFC function is selected. FFC
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function
is selected. IRC indicates whether or not there is space available for writing to the
FIFO2 memory. FFC/IRC is synchronized to the LOW-to-HIGH transition of CLKB.
Notes:
1. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the boundary
flag (e.g., in bursts), use CY standard mode.
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to three clock cycles for flag assertion and deassertion. Refer to
“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
Document #: 38-06023 Rev. *C
Page 4 of 39
CY7C43646
CY7C43666
CY7C43686
Pin Definitions (continued)
Signal Name
Description
I/O
Function
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, or serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into
the X and Y registers. The number of bit writes required to program the offset registers
is 32 for the CY7C43626, 36 for the CY7C43636, 40 for the CY7C43646, 48 for the
CY7C43666, and 56 for the CY7C43686. The first bit write stores the Y-register MSB
and the last bit write stores the X-register LSB.
FS1/SEN
Flag Offset
Select 1/Serial
Enable
I
FS0/SD
Flag Offset
Select 0/Serial
Data
I
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write
operation. When a read operation is performed on Port A, a HIGH level on MBA selects
data from the Mail2 register for output and a LOW level selects FIFO2 output register
data for output. When a write operation is performed on Port A, a High level on MBA
will write the data into Mail 1 register, while a Low level will write the data into FIFO 1.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B read operation. When
a read operation is performed on Port B, a HIGH level on MBB selects data from the
Mail1 register for output and a LOW level selects FIFO1 output register data for output.
MBC
Port C Mailbox
Select
I
When a write operation is performed on Port C, a HIGH level on MBC writes data
into Mail2 register, and a LOW level writes into FIFO2.
MBF1
Mail1 Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register
Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1
FIFO1 Master
Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable
flag default offsets for FIFO1. It also configures Port B for bus size and endian
arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW.
MRS2
FIFO2 Master
Reset
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location
of memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2
selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2
is LOW.
PRS1
FIFO1 Partial
Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
PRS2
FIFO2 Partial
Reset
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location
of memory and sets the Port A output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
RENB
Port B Read
Enable
I
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on
Port B.
RT1
FIFO1
Retransmit
I
A LOW strobe on this pin will retransmit data on FIFO1. This is achieved by bringing
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
Document #: 38-06023 Rev. *C
Page 5 of 39
CY7C43646
CY7C43666
CY7C43686
Pin Definitions (continued)
Signal Name
Description
I/O
Function
RT2
FIFO2
Retransmit
I
A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
SIZEB
Bus Size Select
I
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A
LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZEB works with
BM and BE to select the bus size and endian arrangement for Port B. The level of
SIZEB must be static throughout device operation.
SIZEC
Bus Size Select
I
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port C. A
LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZEC works with
BM and BE to select the bus size and endian arrangement for Port B. The level of
SIZEC must be static throughout device operation.
SPM
Serial
Programming
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
W/RA
Port A
Write/Read
Select
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for
a LOW-to-HIGH transition of CLKA. The A0−35 outputs are in the high-impedance state
when W/RA is HIGH.
WENC
Port C Write
Enable
I
WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data
on Port C.
Signal Description
Master Reset (MRS1, MRS2)
Each of the two FIFO memories of the CY7C436X6 undergoes
a complete reset by taking its associated Master Reset
(MRS1, MRS2) input LOW for at least four Port A clock (CLKA)
and four Port B clock (CLKB) LOW-to-HIGH transitions. The
Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FFA/IRA, FFC/IRC)
LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB)
LOW, the Almost Empty flag (AEA, AEB) LOW, and the Almost
Full flag (AFA, AFC) HIGH. A Master Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
A Master Reset must be performed on the FIFO after
power-up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determines the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS1, PRS2)
Each of the two FIFO memories of the CY7C436X6 undergoes
a limited reset by taking its associated Partial Reset (PRS1,
PRS2) input LOW for at least four Port A clock (CLKA) and four
Port B clock (CLKB) LOW-to-HIGH transitions. The Partial
Reset inputs can switch asynchronously to the clocks. A
Partial Reset initializes the internal read and write pointers and
forces the Full/Input Ready flag (FFA/IRA, FFC/IRC) LOW, the
Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Document #: 38-06023 Rev. *C
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFC) HIGH. A Partial Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or CY Standard mode) are
currently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to Port C or read
from Port B. This selection determines the order by which
bytes (or words) of data are transferred through these ports.
For the following illustrations, assume that a byte (or word) bus
size has been selected for Port B and Port C.
A HIGH on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Big
Endian arrangement. When data is moving in the direction
from Port A to Port B, the most significant byte (word) of the
long-word written to Port A will be transferred to Port B first;
the least significant byte (word) of the long-word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port C to Port A, the byte (word) written to Port
C first will be transferred to Port A as the most significant byte
(word) of the long-word; the byte (word) written to Port C last
will be transferred to Port A as the least significant byte (word)
of the long- word.
A LOW on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Little
Endian arrangement. When data is moving in the direction
from Port A to Port B, the least significant byte (word) of the
long-word written to Port A will be transferred to Port B first;
Page 6 of 39
CY7C43646
CY7C43666
CY7C43686
the most significant byte (word) of the long-word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port C to Port A, the byte (word) written to Port
C first will be transferred to port A as the least significant byte
(word) of the long-word; the byte (word) written to Port C last
will be transferred to Port A as the most significant byte (word)
of the long- word.
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard Mode or First-Word Fall-Through (FWFT) Mode.
Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH
on the BE/FWFT input during the next LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY
Standard Mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFC) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard Mode, every word
read from the FIFO, including the first, must be requested
using a formal read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKC (for FIFO2) will select FWFT
Mode. This mode uses the Output Ready function (ORA,
ORB) to indicate whether or not there is valid data at the data
outputs (A0–35 or B0–17). It also uses the Input Ready function
(IRA, IRC) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs, no read
request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X6 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port C Almost Full flag (AFC) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs, or programmed in serial
using the Serial Data (SD) input (see Table 1).
To load a FIFO’s Almost Empty flag and Almost Full flag offset
registers with one of the three preset values listed in Table 1.
The Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MRS1 and MRS2). For
example, to load the preset value of 64 into X1 and Y1, SPM,
FS0, and FS1 must be HIGH when FIFO1 reset (MRS1)
returns HIGH. Flag-offset registers associated with FIFO2 are
loaded with one of the preset values in the same way with
Master Reset (MRS2). When using one of the preset values
for the flag offsets, the FIFOs can be reset simultaneously or
at different times.
To program the X1, X2, Y1, and Y2 registers from Port A,
perform a Master Reset on both FIFOs simultaneously with
SPM HIGH and FS0 and FS1 LOW during the LOW-to-HIGH
transition of MRS1 and MRS2. After this reset is complete, the
Document #: 38-06023 Rev. *C
first four writes to FIFO1 do not store data in RAM but load the
offset registers in the order Y1, X1, Y2, X2. The Port A data
inputs used by the offset registers are (A0–9), (A0–11), or
(A0–13), for the CY7C436X6, respectively. The highest
numbered input is used as the most significant bit of the binary
number in each case. Valid programming values for the
registers range from 0 to 1023 for the CY7C43646; 1 to 4095
for the CY7C43666; 0to 16383 for the CY7C43686. After all
the offset registers are programmed from Port A, the Port C
Full/Input Ready (FFC/IRC) is set HIGH and both FIFOs begin
normal operation.
To program the X1, X2, Y1, and Y2 registers serially, initiate a
Master Reset with SPM LOW, FS0/SD LOW and FS1/SEN
HIGH during the LOW-to-HIGH transition of MRS1 and MRS2.
After this reset is complete, the X and Y register values are
loaded bit-wise through the FS0/SD input on each
LOW-to-HIGH transition of CLKA that the FS1/SEN input is
LOW. 40, 48, or 56 bit writes are needed to complete the
programming for the CY7C436X6, respectively. The four
registers are written in the order Y1, X1, Y2, and, finally, X2.
The first-bit write stores the most significant bit of the Y1
register and the last-bit write stores the least significant bit of
the X2 register. Each register value can be programmed from
0 to 1023 (CY7C43646), 0 to 4095 (CY7C43666), or 0 to
16383 (CY7C43686).
When the option to program the offset registers serially is
chosen, the Port A Full/Input Ready (FFA/IRA) flag remains
LOW until all register bits are written. FFA/IRA is set HIGH by
the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO1 operation. The Port C Full/Input ready
(FFC/IRC) flag also remains LOW throughout the serial
programming process, until all register bits are written.
FFC/IRC is set HIGH by the LOW-to-HIGH transition of CLKC
after the last bit is loaded to allow normal FIFO2 operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0–35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data
is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2).
FIFO reads and writes on Port A are independent of any
concurrent Port B operation.
The state of the Port B data (B0–17) lines is controlled by the
Port B Chip Select (CSB) and Port B Read select (RENB). The
B0–17 lines are in the high-impedance state when either CSB
is HIGH or RENB is LOW. The B0–17 lines are active outputs
when CSB is LOW and RENB is HIGH.
Data is loaded into FIFO2 from the C0–17 inputs on a
LOW-to-HIGH transition of CLKC when WENC is LOW, MBC
is LOW, and FFC/IRC is HIGH. Data is read from FIFO1 to the
B0–17 outputs by a LOW-to-HIGH transition of CLKB when
CSB is LOW, RENB is HIGH, MBB is LOW, and EFB/ORB is
Page 7 of 39
CY7C43646
CY7C43666
CY7C43686
HIGH (see Table 3). FIFO reads on Port B and writes to Port
C are independent of any concurrent Port A operation.
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
The set-up and hold time constraints to the port clocks for the
port Chip Selects and Write/Read Selects are only for enabling
write and read operations and are not related to
high-impedance control of the data outputs. If a port enable is
LOW during a clock cycle, the port’s Chip Select and
Write/Read Select may change states during the set-up and
hold time window of the cycle.
In the CY Standard Mode, from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data
available for reading in a minimum of two cycles of the Empty
Flag synchronizing clock. Therefore, an Empty Flag is LOW if
a word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty Flag HIGH; only then can data
be read.
When operating the FIFO in FWFT Mode with the Output
Ready flag LOW, the next word written is automatically sent to
the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data
residing in the FIFO’s memory array is clocked to the output
register only when a read is selected using the port’s Chip
Select, Write/Read Select, Enable, and Mailbox Select.
When operating the FIFO in CY Standard Mode, regardless of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Read Select, Enable, and Mailbox Select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is done to improve flag-signal reliability by
reducing the probability of the metastable events when CLKA,
CLKB, and CLKC operate asynchronously to one another.
EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to
CLKA. EFB/ORB and AEB are synchronized to CLKB.
FFC/IRC and AFC are synchronized to CLKC. Table 5 and
Table 6 show the relationship of each port flag to FIFO1 and
FIFO2.
Empty/Output Ready Flags (EFA/ORA, EFB/ORB)
These are dual-purpose flags. In the FWFT Mode, the Output
Ready (ORA, ORB) function is selected. When the Output
Ready flag is HIGH, new data is present in the FIFO output
register. When the Output Ready flag is LOW, the previous
data word is present in the FIFO output register and attempted
FIFO reads are ignored.(See footnote #1)
In the CY Standard Mode, the Empty Flag (EFA, EFB) function
is selected. When the Empty flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When Empty flag is LOW, the previous data word is present in
the FIFO output register and attempted FIFO reads are
ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is incremented
each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer comparator that indicates when
the FIFO SRAM status is empty, or empty+1.
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycles have not elapsed since the time the word was written.
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
Document #: 38-06023 Rev. *C
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFC/IRC)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IRA and IRC) function is selected. In CY Standard Mode, the
Full Flag (FFA and FFC) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to the port
clock that writes data to its array. For both FWFT and CY
Standard modes, each time a word is written to a FIFO, its
write pointer is incremented. The state machine that controls
a Full/Input Ready flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM status
is full, or full–1. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a
minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less
than two cycles of the Full/Input Ready flag synchronizing
clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the
Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AEA, AEB)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, or almost empty+1. The Almost Empty
state is defined by the contents of register X1 for AEB and
register X2 for AEA. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag offset programming above). An Almost Empty flag is LOW
when its FIFO contains X or less words and is HIGH when its
FIFO contains (X+1) or more words. [2]
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CY7C43666
CY7C43686
Two LOW-to-HIGH transitions of the Almost Empty flag
synchronizing clock are required after a FIFO write for its
Almost Empty flag to reflect the new level of fill. Therefore, the
Almost Empty flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An Almost Empty flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost Empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle.
Almost Full Flags (AFA, AFC)
The Almost Full flag of a FIFO is synchronized to the port clock
that writes data to its array. The state machine that controls an
Almost Full flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is
almost full, almost or full–1. The Almost Full state is defined by
the contents of register Y1 for AFA and register Y2 for AFC.
These registers are loaded with preset values during a FIFO
reset, programmed from Port A, or programmed serially (see
Almost Empty flag and Almost Full flag offset programming
above). An Almost Full flag is LOW when the number of words
in its FIFO is greater than or equal to (1024–Y), (4096–Y), or
(16384–Y) for the CY7C436X6 respectively. An Almost Full
flag is HIGH when the number of words in its FIFO is less than
or equal to [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)] for
the CY7C436X6 respectively.[2]
Two LOW-to-HIGH transitions of the Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [1024/4096/16384–(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the
number of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
words in memory to [1024/4096/16384–(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first
synchronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B/Port C without
putting it in queue. The Mailbox Select (MBA, MBB, MBC)
inputs choose between a mail register and a FIFO for a port
data transfer operation. The usable width of both the Mail1 and
Mail2 registers matches the selected bus size for Port C.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH.
When sending data from Port C to Port A via the Mail2 register,
the following is the case: A LOW-to-HIGH transition on CLKC
writes C0-17 data to the Mail2 register when a Port C write is
selected by WENC with MBC HIGH. If the selected Port C bus
Document #: 38-06023 Rev. *C
size is also 18 bits, then the usable width of the Mail2 register
employs data lines C0-17. If the selected Port C bus size is 9
bits, then the usable width of the Mail2 register employs data
lines C0-8. (In this case, C9-17 are “Don’t Care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is
selected by CSB, RENB, and ENB with MBB HIGH. For an
18-bit bus size, 18 bits of mailbox data are placed on B0–17.
For a 9-bit bus size, 9 bits of mailbox data are placed on B0–8.
(In this case, B9-17 are indeterminate.)
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is
selected by CSA, W/RA, and ENA with MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B and Port C buses can be configured in a 18-bit word
or 9-bit byte format for data read from FIFO1 or written to
FIFO2. The levels applied to the Port B Bus Size Select
(SIZEB) and the Port C Bus Size Select (SIZEC) determine the
width of the buses. The bus size can be selected independently for Ports B and C. These levels should be static
throughout FIFO operation. Both bus size selections are
implemented at the completion of Master Reset, by the time
the Full/Input Ready flag is set HIGH.
Two different methods for sequencing data transfer are
available for Port B when the bus size selection is either byte
or word-size. They are referred to as Big Endian (most significant byte first) and Little Endian (least significant byte first).
The level applied to the Big Endian Select (BE) input during
the LOW-to-HIGH transition of MRS1 and MRS2 selects the
endian method that will be active during FIFO operation. BE is
a “don’t care” input when the bus size selected for Port B is
long-word. The endian method is implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Only 36-bit long-word data is written to or read from the two
FIFO memories on the CY7C436X6. Bus-matching operations
are done after data is read from the FIFO1 RAM and before
data is written to FIFO2 RAM. These bus-matching operations
are not available when transferring data via mailbox registers.
Furthermore, both the word- and byte-size bus selections limit
the width of the data bus that can be used for mail register
operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The
remaining data outputs will be indeterminate. The remaining
data inputs will be “don’t care” inputs. For example, when a
word-size bus is selected, then mailbox data can be transmitted only between A0-17 and B0-17. When a byte-size bus is
selected, then mailbox data can be transmitted only between
A0-8 and B0-8.
Page 9 of 39
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CY7C43666
CY7C43686
Bus-Matching FIFO1 Reads
Retransmit (RT1, RT2)
Data is written to the FIFO1 RAM in 36-bit long-word increments. If byte or word size is implemented on Port B, only the
first one or two bytes appear on the selected portion of the
FIFO1 output register, with the rest of the long-word stored in
auxiliary registers. In this case, subsequent FIFO1 reads
output the rest of the long-word to the FIFO1 output register.
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit
function applies to CY standard mode only.
When reading data from FIFO1 as byte, the unused B9-17
outputs are indeterminate.
Bus-Matching FIFO2 Writes
Data is written to the FIFO2 RAM in 18-bit word increments.
Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The CLKC rising
edge that writes the word to FIFO2 also stores the entire
long-word in FIFO2 RAM.
When reading data from FIFO2 in byte format, the unused
C8–17 outputs are LOW.
Document #: 38-06023 Rev. *C
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth minus 2/4/8 words between the reset of
the FIFO (master or partial) and Retransmit setup. A LOW
pulse on RT1, (RT2) resets the internal read pointer to the first
physical location of the FIFO. CLKA and CLKB may be free
running but RENB and (ENA) must be disabled during and
tRTR after the retransmit pulse. With every valid read cycle
after retransmit, previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer. Flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT1, (RT2) are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Page 10 of 39
CY7C43646
CY7C43666
CY7C43686
PORT B BUS SIZING
BYTE ORDER ON
PORT A:
BE
H
SIZEB
L
A27–35
A18–26
A9–17
A
B
C
B9–17
A
B9–17
C
A0–8
D
Write to FIFO1
B0–8
B
1st: Read from
FIFO1
B0–8
D
2nd: Read from
FIFO1
(A) WORD SIZE – BIG ENDIAN
BE
L
SIZEB
L
B9–17
B0–8
C
D
B9–17
B0–8
A
B
1st: Read from
FIFO1
2nd: Read from
FIFO1
(B) WORD SIZE – LITTLE ENDIAN
BE
H
SIZEB
H
B9–17
B0–8
A
B9–17
B0–8
B
B9–17
2nd: Read from
FIFO1
B0–8
C
B9–17
1st: Read from
FIFO1
3rd: Read from
FIFO1
B0–8
D
4th: Read from
FIFO1
(C) BYTE SIZE – BIG ENDIAN
BE
L
SIZEB
H
B9–17
B0–8
D
B9–17
B0–8
C
B9–17
2nd: Read from
FIFO1
B0–8
B
B9–17
1st: Read from
FIFO1
3rd: Read from
FIFO1
B0–8
A
4th: Read from
FIFO1
(D) BYTE SIZE – LITTLE ENDIAN
Document #: 38-06023 Rev. *C
Page 11 of 39
CY7C43646
CY7C43666
CY7C43686
PORT C BUS SIZING
BYTE ORDER ON
PORT A:
BE
H
SIZEC
L
A27–35
A18–26
A9–17
A
B
C
C9–17
A
C9–17
C
A0–8
D
Read from
FIFO2
C0–8
B
1st: Write to
FIFO2
C0–8
D
2nd: Write to
FIFO2
(A) WORD SIZE – BIG ENDIAN
BE
L
SIZEC
L
C9–17
C0–8
C
D
C9–17
C0–8
A
B
1st: Write to
FIFO2
2nd: Write to
FIFO2
(B) WORD SIZE – LITTLE ENDIAN
BE
H
SIZEC
H
C9–17
C0–8
A
C9–17
C0–8
B
C9–17
2nd: Write to
FIFO2
C0–8
C
C9–17
1st: Write to
FIFO2
3rd: Write to
FIFO2
C0–8
D
4th: Write to
FIFO2
(C) BYTE SIZE – BIG ENDIAN
BE
L
SIZEC
H
C9–17
C0–8
D
C9–17
C0–8
C
C9–17
2nd: Write to
FIFO2
C0–8
B
C9–17
1st: Write to
FIFO2
3rd: Write to
FIFO2
C0–8
A
4th: Write to
FIFO2
(D) BYTE SIZE – LITTLE ENDIAN
Document #: 38-06023 Rev. *C
Page 12 of 39
CY7C43646
CY7C43666
CY7C43686
Table 1. Flag Programming[2]
FS1/SEN
FS0/SD
MRS1
MRS2
X1 and Y1 Registers[3]
X2 and Y2 Registers[4]
H
H
H
↑
X
64
X
H
H
H
X
↑
X
64
H
H
L
↑
X
16
X
H
H
L
X
↑
X
16
H
L
H
↑
X
8
X
H
L
H
X
↑
X
8
H
L
L
↑
↑
Parallel programming via Port A
Parallel programming via Port A
L
H
L
↑
↑
Serial programming via SD
Serial programming via SD
L
H
H
↑
↑
Reserved
Reserved
L
L
H
↑
↑
Reserved
Reserved
L
L
L
↑
↑
Reserved
Reserved
SPM
Table 2. Port A Enable Function Table
CSA
W/RA
ENA
MBA
CLKA
A0–35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
↑
In high-impedance state
FIFO1 write
L
H
H
H
↑
In high-impedance state
Mail1 write
L
L
L
L
X
Active, FIFO2 output register
None
L
L
H
L
↑
Active, FIFO2 output register
FIFO2 read
L
L
L
H
X
Active, Mail2 register
None
L
L
H
H
↑
Active, Mail2 register
Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function Table
CSB
RENB
MBB
CLKB
B0–17 OUTPUTS
PORT FUNCTION
H
X
X
X
In high-impedance state
None
L
L
L
X
Active, FIFO1 output register
None
L
H
L
↑
Active, FIFO1 output register
FIFO1 read
L
L
H
X
Active, Mail1 register
None
L
H
H
↑
Active, Mail1 register
Mail1 read (set MBF1 HIGH)
Table 4. Port C Enable Function Table
WENC
MBC
CLKC
C0–17 INPUTS
PORT FUNCTION
H
L
↑
In high-impedance state
FIFO2 write
H
H
↑
In high-impedance state
Mail2 write
L
L
X
In high-impedance state
None
L
H
X
Active, Mail1 register
None
Notes:
3. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
4. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.
Document #: 38-06023 Rev. *C
Page 13 of 39
CY7C43646
CY7C43666
CY7C43686
Table 5. FIFO1 Flag Operation (CY Standard and FWFT Modes)[2]
Number of Words in FIFO Memory[5, 6, 7, 8]
CY7C43646
CY7C43666
Synchronized to CLKB
CY7C43686
Synchronized to CLKA
EFB/ORB
AEB
AFA
FFA/IRA
0
0
0
L
L
H
H
1 TO X1
1 TO X1
1 TO X1
H
L
H
H
(X1+1) to
[1024–(Y1+1)]
(X1+1) to
[4096–(Y1+1)]
(X1+1) to [16384–
(Y1+1)]
H
H
H
H
(1024–Y1) to 1023
(4096–Y1) to 4095
(16384–Y1) to 16383
H
H
L
H
1024
4096
16384
H
H
L
L
Table 6. FIFO2 FLAG OPERATION (CY Standard and FWFT Modes)[2]
Number of Words in FIFO Memory[6, 7, 9, 10]
CY7C43646
CY7C43666
Synchronized to CLKA
CY7C43686
Synchronized to CLKC
EFA/ORA
AEA
AFC
FFC/IRC
0
0
0
L
L
H
H
1 TO X2
1 TO X2
1 TO X2
H
L
H
H
(X2+1) to
[1024–(Y2+1)]
(X2+1) to
[4096–(Y2+1)]
(X2+1) to
[16384–(Y2+1)]
H
H
H
H
(1024–Y2) to 1023
(4096–Y2) to 4095
(16384–Y2) to 16383
H
H
L
H
1024
4096
16384
H
H
L
L
Table 7. Data Size for Word Writes to FIFO2
Size Mode[11]
Write No.
BM
SIZE
BE
H
L
H
H
L
L
Data Written to FIFO2
C9–17
Data Read From FIFO2
C0–8
A27–35
A18–26
A9–17
A0–8
A
B
C
D
A
B
C
D
1
A
B
2
C
D
1
C
D
2
A
B
Table 8. Data Size for Byte Writes to FIFO2
Size Mode[11]
Write No.
BM
SIZE
BE
H
H
H
H
H
L
Data Written to
FIFO2
Data Read From FIFO2
C0–8
A27–35
A18–26
A9–17
A0–8
1
A
A
B
C
D
2
B
3
C
4
D
1
D
A
B
C
D
2
C
3
B
4
A
Notes:
5. X1 is the Almost Empty offset for FIFO1 used by AEB. Y1 is the Almost Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset
or port A programming.
6. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
7. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the
output register (no read operation necessary), it is not included in the FIFO memory count.
8. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard mode.
9. X2 is the Almost Empty offset for FIFO2 used by AEA. Y2 is the Almost Full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset
or port A programming.
10. The ORA and IRC functions are active during FWFT mode; the EFA and FFC functions are active in CY Standard mode.
11. BE is selected at Master Reset. SIZEC must be static throughout device operation.
Document #: 38-06023 Rev. *C
Page 14 of 39
CY7C43646
CY7C43666
CY7C43686
Table 9. Data Size for Word Reads from FIFO1
Size Mode[11]
Data Written to FIFO1
Read No.
BM
SIZE
BE
A27–35
A18–26
A9–17
A0–8
H
L
H
A
B
C
D
H
L
L
A
B
C
D
Data Read From
FIFO1
B9–17
B0–8
1
A
B
2
C
D
1
C
D
2
A
B
Table 10.Data Size for Byte Reads from FIFO1
Size Mode[11]
Data Written to FIFO1
Read No.
BM
SIZE
BE
A27–35
A18–26
A9–17
A0–8
H
H
H
A
B
C
D
H
H
Document #: 38-06023 Rev. *C
L
A
B
C
D
Data Read From
FIFO1
B0–8
1
A
2
B
3
C
4
D
1
D
2
C
3
B
4
A
Page 15 of 39
CY7C43646
CY7C43666
CY7C43686
DC Input Voltage[13]................................. –0.5V to VCC+0.5V
Maximum Ratings[12, 14]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[13] ....................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Ambient
Temperature
0°C to +70°C
−40°C to +85°C
Range
Commercial
Industrial
VCC[15]
5.0V±0.5V
5.0V±0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output OFF, High-Z Current
VOH
VOL
VIH
VIL
IIX
IOZL
IOZH
ICC1[16]
Test Conditions
VCC = 4.5V., IOH = −4.0 mA
VCC = 4.5V., IOL = 8.0 mA
VCC = Max.
VSS < VO< VCC
Active Power Supply Current
ISB[17]
7C43646/66/86
Min.
Max.
2.4
0.5
2.0
VCC
–0.5
0.8
–10
+10
–10
+10
Unit
V
V
V
V
µA
µA
100
100
10
10
mA
mA
mA
mA
Max.
4
8
Unit
pF
pF
Com’l
Ind
Com’l
Ind
Average Standby Current
Capacitance[18]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
AC Test Loads and Waveforms (-10 and -15)
ALL INPUT PULSES
R1 = 1.1 KΩ
5V
3.0V
OUTPUT
CL = 30 pF
R2 = 680Ω
90%
10%
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
VCC/2
50Ω
I/O
≤ 3 ns
ALL INPUT PULSES
3.0V
90%
10%
GND
Z0 = 50Ω
90%
10%
≤ 3 ns
90%
10%
≤ 3 ns
Notes:
12. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
13. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
14. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
15. Operating VCC Range for -7 speed is 5.0V ± 0.25V.
16. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
17. All inputs = VCC– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
18. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06023 Rev. *C
Page 16 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Characteristics Over the Operating Range
7C43646/
66/86
-7
Parameter
Description
Min.
Max.
7C43646/
66/86
-10
Min.
133
Max.
7C43646/
66/86
-15
Min.
100
Max.
Unit
67
MHz
fS
Clock Frequency, CLKA,CLKB, or CLKC
tCLK
Clock Cycle Time, CLKA,CLKB, or CLKC
7.5
10
15
ns
tCLKH
Pulse Duration, CLKA,CLKB, or CLKC HIGH
3.5
4
6
ns
tCLKL
Pulse Duration, CLKA,CLKB, or CLKC LOW
3.5
4
6
ns
tDS
Set-up Time, A0–35 before CLKA↑ B0–17 before
CLKB↑, and C0–17 before CLKC↑
3
4
5
ns
3
4
5
ns
tENS
Set-up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; RENB and MBB before CLKB↑ and WENC
and MBC before CLKC↑
tRSTS
Set-up Time, MRS1, MRS2, PRS1, PRS2, RT1 or
RT2 LOW before CLKA↑ or CLKB↑[19]
2.5
4
5
ns
tFSS
Set-up Time, FS0 and FS1 before MRS1 and MRS2
HIGH
6
7
7.5
ns
tBES
Set-up Time, BE/FWFT before MRS1 and MRS2
HIGH
5
7
7.5
ns
tSPMS
Set-up Time, SPM before MRS1 and MRS2 HIGH
5
7
7.5
ns
tSDS
Set-up Time, FS0/SD before CLKA↑
3
4
5
ns
tSENS
Set-up Time, FS1/SEN before CLKA↑
3
4
5
ns
tFWS
Set-up Time, FWFT before CLKA↑
0
0
0
ns
tDH
Hold Time, A0–35 before CLKA↑ B0–17 before CLKB↑,
and C0–17 before CLKC↑
0
0
0
ns
0
0
0
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA before
CLKA↑ RENB and MBB before CLKB↑ and WENC
and MBC before CLKC↑
tRSTH
Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2
LOW after CLKA↑ or CLKB↑[19]
1
2
4
ns
tFSH
Hold Time, FS0 and FS1 after MRS1 and MRS2
HIGH
1
1
2
ns
tBEH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
1
1
2
ns
tSPMH
Hold Time, SPM after MRS1 and MRS2 HIGH
1
1
2
ns
tSDH
Hold Time, FS0/SD after CLKA↑
0
0
0
ns
tSENH
Hold Time, FS1/SEN after CLKA↑
0
0
0
ns
tSPH
Hold Time, FS1/SEN HIGH after MRS1 and MRS2
HIGH
0
1
2
ns
tSKEW1[20]
Skew Time between CLKA↑ and CLKB↑ for
EFA/ORA, EFB/ORB, FFA/IRA, and FFC/IRC
5
5
7.5
ns
tSKEW2[20]
Skew Time between CLKA↑ and CLKB↑ for AEA,
AEB, AFA, AFC
7
8
12
ns
tA
Access Time, CLKA↑ to A0–35 and CLKB↑ to B0–17
1
6
1
8
3
10
ns
tWFF
Propagation Delay Time, CLKA↑ to FFA/IRA and
CLKB↑ to FFC/IRC
1
6
1
8
2
8
ns
Notes:
19. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
20. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
Document #: 38-06023 Rev. *C
Page 17 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Characteristics Over the Operating Range (continued)
7C43646/
66/86
-7
Parameter
Description
7C43646/
66/86
-10
7C43646/
66/86
-15
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tREF
Propagation Delay Time, CLKA↑ to EFA/ORA and
CLKB↑ to EFB/ORB
1
6
1
8
1
8
ns
tPAE
Propagation Delay Time, CLKA↑ to AEA and CLKB↑
to AEB
1
6
1
8
1
8
ns
tPAF
Propagation Delay Time, CLKA↑ to AFA and CLKC↑
to AFC
1
6
1
8
1
8
ns
0
6
0
8
0
12
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1
HIGH
tPMR
Propagation Delay Time, CLKA↑ to B0–17[21] and
CLKB↑ to A0–35[22]
1
7
2
11
3
12
ns
tMDV
Propagation Delay Time, MBA to A0–35 Valid and
MBB to B0–17 Valid
1
6
2
9
3
11
ns
1
6
1
10
1
15
ns
tRSF
Propagation Delay Time, MRS1 or PRS1 LOW to
AEB LOW, AFA HIGH, FFA/IRA LOW, EFB/ORB
LOW and MBF1 HIGH and MRS2 or PRS2 LOW to
AEA LOW, AFC HIGH, FFC/IRC LOW, EFA/ORA
LOW and MBF2 HIGH
tEN
Enable Time, CSA or W/RA LOW to A0–35 Active and
CSB LOW and RENB HIGH to B0–17 Active
1
5
2
8
2
10
ns
1
5
1
6
1
8
ns
tDIS
Disable Time, CSA or W/RA HIGH to A0–35 at High
Impedance and CSB HIGH or RENB LOW to B0–17
at High Impedance
Retransmit recovery Time
90
tRTR
90
90
ns
Notes:
21. Writing data to the Mail1 register when the B0–17 outputs are active and MBB is HIGH.
22. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Document #: 38-06023 Rev. *C
Page 18 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms
FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight [23, 24]
CLKA
CLKB
tRSTH
tRSTS
MRS1
tBES
tBEH
tSPMS
tSPMH
tFSS
tFSH
tFWS
BE/FWFT
SPM
FS1/SEN,
FS0/SD
tRSF
tWFF
FFA/IRA
EFB/ORB
tRSF
tRSF
AEB
AFA
tRSF
tRSF
MBF1
Notes:
23. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.
24. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.
Document #: 38-06023 Rev. *C
Page 19 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
FIFO2 Master Reset Loading X1 and Y1 with a Preset Value of Eight [25, 26]
CLKC
CLKA
tRSTS
tRSTS
MRS2
tBES
tBEH
tSPMS
tSPMH
tFSS
tFSH
tFWS
BE/FWFT
SPM
FS1/SEN,
FS0,SD
tRSF
tWFF
FFC/IRC
EFA/ORA
tRSF
tRSF
AEA
AFC
tRSF
tRSF
MBF2
Notes:
25. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.
26. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than the case where BE/FWFT is LOW.
Document #: 38-06023 Rev. *C
Page 20 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
FIFO1 Partial Reset (CY Standard and FWFT Modes)
[24, 27]
CLKA
CLKB
tRSTS
tRSTH
PRS1
tWFF
tRSF
FFA/IRA
tRSF
EFB/ORB
tRSF
AEB
tRSF
AFA
tRSF
MBF1
[26, 28]
FIFO2 Partial Reset (CY Standard and FWFT Modes)
CLKC
CLKA
tRSTS
tRSTH
PRS2
tRSF
tWFF
FFC/IRC
tRSF
EFA/ORA
AEA
tRSF
tRSF
AFC
tRSF
MBF1
Notes:
27. MRS1 must be HIGH during Partial Reset.
28. MRS2 must be HIGH during Partial Reset.
Document #: 38-06023 Rev. *C
Page 21 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes) [29]
CLKA
MRS1, MRS2
tFSS
SPM
tFSS
tFSH
tFSH
FS1/SEN,
FS0/SD
tWFF
FFA/IRA
tENH
tENS
tSKEW1[30]
ENA
tDS
tDH
A0−35
AFA Offset (Y1) AEB Offset
AEA Offset (X2) First Word to
AFC Offset
CLKC
tWF
FFC/IRC
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes) [31]
CLKA
MRS1, MRS2
tFSS tFSH
SPM
tWFF
tSKEW1
FFA/IRA
tFSS
tSPH
tSENS
[32]
tSENS tSEN
tSENH
FS1/SEN
FS0/SD
[33]
tSDS
tSDH
AFA Offset (Y1) MSB
tSDS
tSDH
AEA Offset (X2)
CLKC
tWFF
FFC/IRC
Notes:
29. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
30. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge
of CLKA and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one cycle later than shown.
Document #: 38-06023 Rev. *C
Page 22 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
tCLKH
tCLK
tCLKL
CLKA
FFA/IRA
HIGH
tENS tENH
CSA
tENS tENH
W/RA[34]
tENS tENH
MBA
tENS tENH
tENS tENH
tENS tENH
ENA
tDS
A0–35
tDH
W2[35]
W1[35]
Port C Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKC
FFC/IRC
HIGH
tENH
tENS
tENH
tENS tENH
tENS
tENH
tENS
MBC
WENC
tDS
C0–17
tDH
Port C Byte Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKC
FFC/IRC
HIGH
MBC
tENH
tENS tENH
tENS tENH
tENS
tENH
WENC
tDS tDH
C0–8
Notes:
31. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
32. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge
of CLKA and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one cycle later than show.
33. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
34. If W/RA switches from read to write before the assertion of CSA, tENS = tDIS+tENS.
35. Written to FIFO1.
Document #: 38-06023 Rev. *C
Page 23 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
Port B Byte Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes) [36, 1]
CLKB
EFB/ORB
HIGH
CSB
MBB
tENS tENH
RENB
B0–8
(Standard Mode)
OR
B0–8
(FWFT Mode)
tEN
tEN
tMDV
tA
tA
tA
tA
tMDV
Previous
tA
Read1
tA
Read2
tA
Read3
tA
Read1
Read2
Read3
Read4
No Opera- tDIS
Read4
tDIS
Read5
Port B Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)[1]
CLKB
EFB/ORB
CSB
MBB
B0–17
(Standard Mode)
OR
B0–17
(FWFT Mode)
tENH
tEN
ENB
tEN
tMDV
Previous Data
tEN
tA
tA
tMDV
Read 1
Read 2
tDIS
Read 2
tA
tA
Read 1
No Operation
tDIS
Read 3
Note:
36. Unused bytes B9–17 contain all zeroes for byte-size reads.
Document #: 38-06023 Rev. *C
Page 24 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
[1]
Port A Byte Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKA
tCLKH
tCLK
tCLKL
EFA/ORA
CSA
W/RA[34]
MBA
tENS
tENH
tENS tENH
tENS
tENH
ENA
A0−35
(Standard Mode)
OR
A0−35
(FWFT Mode)
tEN
tA
tMDV
Previous Data
tEN
tMDV
tA
W1[37]
tA
W1[37]
W2[37]
tA
No Operation
tDIS
W2[37]
tDIS
W3[37]
Note:
37. Read From FIFO2.
Document #: 38-06023 Rev. *C
Page 25 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)[38, 39]
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
W/RA
HIGH
tENS tENH
MBA
tENS tENH
ENA
FFA/IRA
HIGH
tDS tDH
A0–35
W1
tSKEW1[40] tCLKH
CLKB
EFB/ORB
CSB
MBB
tCLKL
tCLK
tREF
tREF
FIFO1 Empty
LOW
LOW
tENS tENH
RENB
tA
B0–17
Old Data in FIFO1 Output Register
tA
W1a
W1b
Notes:
38. SIZEB = LOW; If BE = HIGH, W1a is the most significant word, W1b is the least significant word. If BE = LOW, W1a is the least significant word, W1b is the most
significant word.
39. If SIZEB = HIGH (byte size), ORB is set LOW by the last byte read from FIFO2.
40. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of
the first word to the output register may occur one CLKB cycle later than shown.
Document #: 38-06023 Rev. *C
Page 26 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
[38, 41]
EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (CY Standard Mode)
tCLK
tCLKH tCLKL
CLKA
CSA
W/RA
LOW
HIGH
tENS tENH
MBA
tENStENH
ENA
FFA/IRA
HIGH
tDS tDH
A0–35
W1
tSKEW1[42] tCLKH
CLKB
tCLKL
tCLK
EFB/ORB
CSB
MBB
tREF
tREF
FIFO1 Empty
LOW
LOW
tENS tENH
RENB
B0–17
tA
tA
W1a
W1b
Notes:
41. If SIZEB = HIGH (byte size), EFB is set LOW by the last byte read from FIFO2.
42. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06023 Rev. *C
Page 27 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)[43, 44]
tCLK
tCLKH tCLKL
CLKC
MBC
WENC
tENS tENH
tENS tENH
FFC/IRC HIGH
tDS tDH
W1b
W1a
C0–17
tSKEW1[45]
tCLKH
tCLKL
CLKA
tCLK
tREF
tREF
EFA/ORA FIFO2 Empty
CSA
LOW
W/RA
LOW
MBA
LOW
tENStENH
ENA
tA
A0–35
Old Data in FIFO2 Output Register
W1
Notes:
43. SIZEC = LOW; If BE = HIGH, W1a is the most significant word, W1b is the least significant word. If BE = LOW, W1a is the least significant word, W1b is the most
significant word.
44. If SIZEC = HIGH (byte size), tSKEW1 is referenced to the rising CLKC edge that writes the last byte of the long word.
45. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKC edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of
the first word to the output register may occur one CLKA cycle later than shown.
Document #: 38-06023 Rev. *C
Page 28 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode) [43, 44]
tCLK
tCLKH
tCLKL
CLKC
tENStENH
MBC
tENStENH
WENC
FFC/IRC
HIGH
tDS tDH
C0–17
W1a
W1b
tSKEW1[46] tCLKH
CLKA
tCLK
EFA/IRA
FIFO2 Empty
CSA
LOW
W/RA
LOW
MBA
LOW
tCLKL
tREF
tREF
tENS tENH
ENA
tA
A0–35
W1
Notes:
46. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKC edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Document #: 38-06023 Rev. *C
Page 29 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode) [47, 48]
tCLK
tCLKH tCLKL
CLKB
CSB
MBB
LOW
LOW
tENS tENH
RENB
EFB/ORB HIGH
tA
B0–17
Word A
Word B
tSKEW1[49] tCLKH
CLKA
FFA/IRA FIFO1 Full
CSA
LOW
W/RA
HIGH
tCLKL
tCLK
tWFF
tWFF
tENStENH
MBA
tENS tENH
ENA
tDS tDH
A0–35
To FIFO1
Notes:
47. SIZEB = LOW; If BE = HIGH, Word A is the most significant word of the last long word in FIFO1, Word B is the least significant word. If BE = LOW, Word A is the
least significant word of the last long word in FIFO1, Word B is the most significant word.
48. If SIZEB = HIGH (byte size), tSKEW1 is referenced to the rising CLKB edge that reads the last byte write of the long word.
49. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Document #: 38-06023 Rev. *C
Page 30 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)[47,48]
tCLK
tCLKH tCLKL
CLKB
CSB
MBB
LOW
LOW
tEN tENH
ENB
EFB/ORB HIGH
tA
B0–17
Word A
Word B
tSKEW1[50]tCLKH tCLKL
CLKA
FFA/IRA FIFO1 Full
CSA
LOW
W/RA
HIGH
tCLK
tWFF
tWFF
tENS tENH
MBA
tENS tENH
ENA
A0−35
tDS tDH
Note:
50. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Document #: 38-06023 Rev. *C
Page 31 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)[51, 52]
tCLK
tCLKH tCLKL
CLKA
CSA
LOW
W/RA
LOW
MBA
LOW
tENStENH
ENA
EFA/ORA
HIGH
tA
A0–35
Previous Word in
Next Word From FIFO2
FIFO2 Output Register
tCLKH tCLKL
[53]
tSKEW1
CLKC
tCLK
FFC/IRC
tWFF
tWFF
FIFO2 Full
tENS tENH
MBC
tENS tENH
WENC
tDS tDH
C0–17
Word A
Word B
Notes:
51. SIZEC = LOW; If BE = HIGH, Word A is the most significant word of the last long word in FIFO2, Word B is the least significant word. If BE = LOW, Word A is the
least significant word of the last long word in FIFO2, Word B is the most significant word.
52. If SIZEC = HIGH (byte size), IRC is set LOW by the last byte write of the long word.
53. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKC edge for IRC to transition HIGH in the next CLKB cycle. If the time between the rising
CLKA edge and rising CLKC edge is less than tSKEW1, then the transition of IRC HIGH may occur one CLKC cycle later than shown.
Document #: 38-06023 Rev. *C
Page 32 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
FFC Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode) [51, 54]
tCLK
tCLKH tCLKL
CLKA
CSA
LOW
W/RA
LOW
MBA
LOW
tENStENH
ENA
EFA/ORA
HIGH
tA
A0–35
Previous Word in
Next Word From FIFO2
FIFO2 Output Register [55] t
CLKH tCLKL
tSKEW1
CLKC
tCLK
FFC/IRC
tWFF
tWFF
FIFO2 Full
tENS tENH
MBC
tENS tENH
WENC
tDS tDH
C0–17
Word A
Word B
Timing for AEB when FIFO1 is Almost Empty (CY Standard and FWFT Modes)[56, 57, 2]
CLKA
ENA
tENS
CLKB
tSKEW2[58]
AEB
RENB
tENH
(X1+1) Word in FIFO1
X1 Word in FIFO1
tPAE
tPAE
(X1+1)Words in FIFO1
tENS
tENH
Notes:
54. If SIZEC = HIGH (byte size), FFC is set LOW by the last byte write of the long word.
55. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFC to transition HIGH in the next CLKB cycle. If the time between the rising
CLKA edge and rising CLKC edge is less than tSKEW1, then the transition of FFC HIGH may occur one CLKC cycle later than shown.
Document #: 38-06023 Rev. *C
Page 33 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes) [59, 60, 2]
CLKC
tENS
tENH
WENC
tSKEW2[61]
CLKA
tPAE
tPAE
AEA
X2 Word in FIFO2
(X2+1) Words in FIFO2
tENS
(X2+1) Word in FIFO2
tENH
ENA
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes) [2, 62, 63, 64]
tSKEW2[65]
CLKA
ENA
AFA
tENS
tENH
tPAF
[D–(Y1+1)] Words in FIFO1
tPAF
(D–Y1)Words in FIFO1
CLKB
tENS
RENB
tENH
Timing for AFC when FIFO2 is Almost Full (CY Standard and FWFT Modes) [59, 2, 63, 66]
tSKEW2[67]
CLKC
WENC
AFC
tENS
tENH
tPAF
[D–(Y2+1)] Words in FIFO2
(D–Y2)Words in FIFO2
tPAF
CLKA
ENA
tENS
tENH
Notes:
56. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
57. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
58. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
59. FIFO2 Write (MBB = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
60. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
61. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKC edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
62. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
63. D = Maximum FIFO Depth = 1K for the CY7C43646, 4K for the CY7C43666, and 16K for the CY7C43686.
64. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
65. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
66. If Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.
67. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the
rising CLKC edge and rising CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKA cycle later than shown.
Document #: 38-06023 Rev. *C
Page 34 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes) [68,69]
CLKA
tENS
CSA
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tDS
tDH
W/RA[34]
MBA
ENA
A0–35
W1
CLKB
tPMF
tPMF
MBF1
CSB
MBB
tENS
tENH
RENB
tEN
B0–17
tMDV
FIFO1 Output Register
tPMR
tDIS
W1 (Remains valid in Mail1 Register after read)
Note:
68. If Port A is configured for word size, data can be written to the Mail1 Register using A0-17 (A18-35 are “don’t care” inputs). In this first case, B0-17 will have valid
data. If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are “don’t care” inputs). In this second case, B0–8 will have
valid data (B9–17 will be indeterminate).
69. Simultaneous writing to and reading from mailbox register is not allowed.
Document #: 38-06023 Rev. *C
Page 35 of 39
CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes) [69,70]
CLKC
MBC
tENS tENH
WENC
tDS
C0–17
tDH
W1
CLKA
tPMF
tPMF
MBF2
CSA
W/RA[34]
MBA
tENS
ENA
tMDV
tEN
A0−35
FIFO2 Output Reg-
tENH
tPMR
W1 (Remains valid in Mail2 Register after
tDIS
FIFO1 Retransmit Timing [71, 72, 73, 74, 75]
CLKA
CLKB
RT1
ENB
tRSTS
tRSTH
tRTR
EFB/FFA
Notes:
70. If Port C is configured for word size, data can be written to the Mail2 register using C0–17. In this first case A0–17 will have valid data (A18–35 will be indeterminate).
If Port C is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–17 are “don’t care” inputs). In this second case, A0–8 will have valid
data (A9–35 will be indeterminate).
71. Retransmit is performed in the same manner for FIFO2.
72. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one write clock cycle before the falling edge of RT1, and during
the retransmit operation, i.e. when RT1 is LOW and tRTR after the RT1 rising edge.
73. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
74. For the AEA, AEB, AFA, and AFB flags, two clock cycle are necessary after tRTR to update these flags.
75. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial) and
the Retransmit setup.
Document #: 38-06023 Rev. *C
Page 36 of 39
CY7C43646
CY7C43666
CY7C43686
Ordering Information
1K x36/18x2 Tri Bus Synchronous FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
7
CY7C43646-7AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43646-10AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43646-15AC
A128
128-lead Thin Quad Flat Package
Commercial
4K x36/18x2 Tri Bus Synchronous FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
7
CY7C43666-7AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43666-10AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43666-15AC
A128
128-lead Thin Quad Flat Package
Commercial
16K x36/18x2 Tri Bus Synchronous FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
7
CY7C43686-7AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43686-10AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43686-15AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43686–15AI
A128
128-lead Thin Quad Flat Package
Industrial
Document #: 38-06023 Rev. *C
Page 37 of 39
CY7C43646
CY7C43666
CY7C43686
Package Diagram
128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06023 Rev. *C
Page 38 of 39
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C43646
CY7C43666
CY7C43686
Document History Page
Document Title: CY7C43646/CY7C43666/CY7C43686 1K/4K/16K x36/x18/x2 Tri Bus FIFO
Document Number: 38-06023
REV.
Orig. of
ECN No. Issue Date Change
Description of Change
**
106565
05/15/01
SZV
Change from Spec number: 38-00701 to 38-06023
*A
117174
08/28/02
OOR
Added footnote to retransmit timing
Added note to retransmit section
*B
122275
12/26/02
RBI
Power-up requirements added to Maximum Ratings Information
*C
129118
09/30/03
JFU
Added mention of Port C behavior under Signal Description
Changed signal behavior of ORB/EFB, ORA/EFA, IRA/FFA, and IRC/FFC in timing
diagrams
Document #: 38-06023 Rev. *C
Page 39 of 39